rt-thread.git/libcpu/risc-v/e310/start_gcc.S, branch v3.0.2 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/e310/start_gcc.S?h=v3.0.2 2017-08-26T03:02:39Z [BSP] cleanup for hifive1 bsp. 2017-08-26T03:02:39Z Bernard Xiong bernard.xiong@gmail.com 2017-08-26T03:02:39Z urn:sha1:2ac493698ba0c0578147045f6660add7bb4ad2eb fix bug in context_gcc.s and start_gcc.s: 2017-07-31T02:59:59Z zhangjun 2281979437@qq.com 2017-07-31T02:59:59Z urn:sha1:a5305c05df3e97cd60c621bec87926765ba31228 save mie into stack msh running normaly fix bug in rt_hw_context_switch_interrupt_do 2017-07-30T11:46:28Z zhangjun 2281979437@qq.com 2017-07-30T11:46:28Z urn:sha1:b032dff1616fe64a4dfec63e593f0fac634ef3ab save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt) 修改： ../../libcpu/risc-v/e310/context_gcc.S 2017-07-30T07:34:32Z zhangjun 2281979437@qq.com 2017-07-30T07:34:32Z urn:sha1:2d56a27c20d430f678a77e48f1d00591f4fc4c8b enable interrupt after return form rt_hw_context_switch fix trap_entry 2017-07-29T07:37:20Z zhangjun 2281979437@qq.com 2017-07-29T07:37:20Z urn:sha1:3c51848d33d2c13d0029f3e796af9f78a882eac3 remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 2017-07-26T08:07:01Z zhangjun 2281979437@qq.com 2017-07-26T08:07:01Z urn:sha1:98a6896cfa5b577503139363ffc141418d55412f it will lead to interrupt again in interrupt add context_gcc.s 2017-07-17T07:44:00Z zhangjun 2281979437@qq.com 2017-07-17T07:44:00Z urn:sha1:e01455155ab5a564eddd467b02a0226b3fa5ea7d