rt-thread.git/libcpu/risc-v/rv64, branch copilot/create-dfs2-documentationUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/rv64?h=copilot%2Fcreate-dfs2-documentation2025-01-30T01:28:38Zlibcpu: riscv: rv64: fixed warnings2025-01-30T01:28:38ZChen Wangunicorn_wang@outlook.com2025-01-27T06:18:08Zurn:sha1:c66374705a05d1f780c66aeefabe1c88c563e065
When building bsp/cvitek/c906_little, compiler reports:
```
.../rt-thread/libcpu/risc-v/rv64/trap.c:
In function 'handle_trap':
.../rt-thread/libcpu/risc-v/rv64/trap.c:106:13:
warning: implicit declaration of function 'rt_hw_tick_isr';
did you mean 'rt_hw_stack_init'? [-Wimplicit-function-declaration]
106 | rt_hw_tick_isr();
| ^~~~~~~~~~~~~~
| rt_hw_stack_init
.../rt-thread/libcpu/risc-v/rv64/trap.c:110:13:
warning: implicit declaration of function 'rt_hw_irq_isr';
did you mean 'rt_hw_soft_irq_isr'? [-Wimplicit-function-declaration]
110 | rt_hw_irq_isr();
| ^~~~~~~~~~~~~
| rt_hw_soft_irq_isr
```
rt_hw_tick_isr()/rt_hw_irq_isr() are implemented by bsp, but
libcpu/risc-v/rv64 doesn't declare them, so compiler warns.
There are three BSPs using 'rv64' (libcpu/risc-v/rv64):
- `bsp/cvitek/c906_little/rtconfig.py`
- `bsp/juicevm/rtconfig.py`
- `bsp/k210/rtconfig.py`
`handle_trap` in `libcpu/risc-v/rv64` is defined as weak.
BSP can use this function directly or define and overload
it by itself.
If bsp use this function directly, bsp need to pay
attention to the fact that three functions will be called
in this function:
- `rt_hw_soft_irq_isr`
- `rt_hw_tick_isr`
- `rt_hw_irq_isr`
In `libcpu/risc-v/rv64`, `rt_hw_soft_irq_isr` has a weak
definition, while the other two do not. This means that
if the bsp does not overload `handle_trap`, bsp must
define `rt_hw_tick_isr` and `rt_hw_irq_isr` itself.
This is also the practice of `bsp/cvitek/c906_little`.
There is also a similar bsp `bsp/k210`, and the form of
`bsp/juicevm` implements `handle_trap` by itself.
It seems that `rt_hw_tick_isr` and `rt_hw_irq_isr` are
not required to be implemented by all BSPs using
`libcpu/risc-v/rv64`. The premise for BSP to implement
them is that it does not overload `handle_trap`. So
declaring `rt_hw_tick_isr` and `rt_hw_irq_isr` with
extern in `libcpu/risc-v/rv64` is not proper.
In addition, the `rt_hw_tick_isr/rt_hw_irq_isr` are only
used by `libcpu/risc-v/rv64`, so it is not worth putting
the declaration in `./include/rthw.h`.
Sum up, the best solution is to add weak definition to
`rt_hw_tick_isr/rt_hw_irq_isr` as existing `rt_hw_soft_irq_isr`.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[ipc] support of lockless rt_completion (#8887)2024-05-08T01:25:57ZShellsmokewood@qq.com2024-05-08T01:25:57Zurn:sha1:48bd0e49f2687708e0aca2f3791ccc295920c80a
* [ipc] lockless rt_completion implementation
The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: error
* remove useless changes
---------
Signed-off-by: Shell <smokewood@qq.com>[libcpu][SConscript]规范group名为libcpu2024-02-20T00:39:05ZMeco Man920369182@qq.com2024-02-19T19:33:47Zurn:sha1:6d4503363a352c72148bc91da3026f0db096f119add libcpu/risc-v/rv64 (#8511)2024-01-28T05:39:39Zflyingcysflyingcys@163.com2024-01-28T05:39:39Zurn:sha1:3f41bd95d10bf02de049290434af587c5586fde5