rt-thread.git/libcpu/risc-v/t-head, branch copilot/fix-riscv-none-job-failure Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/t-head?h=copilot%2Ffix-riscv-none-job-failure 2026-09-15T14:57:55Z [libcpu][risc-v]Feat: Add OpenSBI SMP support to t-head c908 2026-09-15T14:57:55Z guanxi.cgh guanxi.cgh@alibaba-inc.com 2026-09-04T03:04:21Z urn:sha1:e81494f881526b257165207cf716df1043f1bb2a [libcpu][risc-v]Feat: Add mmu SV48/SV57 mode support and add mmu_demo for C908. 2026-09-15T14:57:55Z guanxi.cgh guanxi.cgh@alibaba-inc.com 2026-08-25T13:25:54Z urn:sha1:a5d9dc884b6f5f61b06664bbf745356416de98cf Ensure that c906 uses only the Xuantie MMU properties 2026-08-21T08:51:33Z rcitach yearsince@yeah.net 2026-08-21T05:29:14Z urn:sha1:5ae08713c8b409aef8ba1d887c3f228566537909 fix[libcpu][risc-v]: 2026-02-26T09:26:47Z shuta.lst shuta.lst@alibaba-inc.com 2026-02-26T07:24:12Z urn:sha1:33f8aff9cf0411f0fe6e6d6231f296448387f247 - Implement _noncache() and _cache() function features; - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration; - Update C908/C906 PTE macro definition configuration; feat[libcpu][t-head][c908]: Support RISC-V Standard Svpbmt Extension For C908; 2026-02-26T01:42:50Z shuta.lst shuta.lst@alibaba-inc.com 2026-02-25T08:29:08Z urn:sha1:0dfc5f326209ea5fabea5a5a66368c19ab975ee5 chore: fix typo in components and libcpu 2026-02-13T13:54:59Z theqengineer zyrhqu@gmail.com 2026-02-13T07:04:27Z urn:sha1:85b656b14dcfe8a3ab27c819e168dde082ab39ef Reorganize Group names in build system for clarity and IDE integration #10923 2025-11-16T03:40:53Z Copilot 198982749+Copilot@users.noreply.github.com 2025-11-16T03:40:53Z urn:sha1:30e1e5e9dcdaff17258edf70b9f9783e08356288 给vector模块添加构建脚本 2024-11-27T10:04:59Z heyuanjie87 943313837@qq.com 2024-11-22T03:58:18Z urn:sha1:d3820ed77e26759c3a3d29dad65bbcca371374c6 [kernel] Specification interrupt nested level variable declaration type (#9568) 2024-10-23T21:08:29Z Yuqiang Wang yifang.wangyq@foxmail.com 2024-10-23T21:08:29Z urn:sha1:b3d59050b049f03d954273e8921f941dd806360a [libcpu]添加对riscv vector的支持 (#9531) 2024-10-16T06:10:09Z heyuanjie87 943313837@qq.com 2024-10-16T06:10:09Z urn:sha1:49b661476393bd9c9fc199362cf4b008c35a9340 [libcpu]添加对riscv vector的支持