rt-thread.git/libcpu/risc-v/t-head, branch master

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

[libcpu][risc-v]Feat: Add OpenSBI SMP support to t-head c908

2026-09-15T14:57:55Z

[libcpu][risc-v]Feat: Add mmu SV48/SV57 mode support and add mmu_demo for C908.

2026-09-15T14:57:55Z

Ensure that c906 uses only the Xuantie MMU properties

2026-08-21T08:51:33Z

fix[libcpu][risc-v]:

2026-02-26T09:26:47Z

- Implement _noncache() and _cache() function features; - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration; - Update C908/C906 PTE macro definition configuration;

feat[libcpu][t-head][c908]: Support RISC-V Standard Svpbmt Extension For C908;

2026-02-26T01:42:50Z

chore: fix typo in components and libcpu

2026-02-13T13:54:59Z

Reorganize Group names in build system for clarity and IDE integration #10923

2025-11-16T03:40:53Z

给vector模块添加构建脚本

2024-11-27T10:04:59Z

[kernel] Specification interrupt nested level variable declaration type (#9568)

2024-10-23T21:08:29Z