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<title>rt-thread.git/libcpu/risc-v/t-head, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/t-head?h=v5.0.2</id>
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<updated>2023-09-09T01:35:56Z</updated>
<entry>
<title>[smart/syscall] fix exit(2) and add exit_group(2) (#8005)</title>
<updated>2023-09-09T01:35:56Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-09-09T01:35:56Z</published>
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<id>urn:sha1:47b183a2978a8b474e25ec38b37ef5741a50d724</id>
<content type='text'>
Signed-off-by: shell &lt;smokewood@qq.com&gt;
Signed-off-by: shell &lt;wangxiaoyao@rt-thread.com&gt;
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[components/mm] add unmap page API (#7834)</title>
<updated>2023-08-16T07:38:59Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-08-16T07:38:59Z</published>
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<id>urn:sha1:d862816a51ab6fec2321f0410e8aea2d05507542</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>rt_hw_cpu_shutdown: implement default weak function</title>
<updated>2023-08-09T02:34:25Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-08-07T16:42:10Z</published>
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<id>urn:sha1:c6a2f5b7bdee378cc868ee9284e760ebbdf635f0</id>
<content type='text'>
and remvoe duplicated default functions in each cpu/bsp level
</content>
</entry>
<entry>
<title>[bsp]add cv1800b (#7753)</title>
<updated>2023-06-29T16:05:55Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-06-29T16:05:55Z</published>
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<id>urn:sha1:c78f64689142cd36357edbe8db3b60a3c5c00e07</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][component][debug] add debug info for gdb (#7033)</title>
<updated>2023-05-14T15:48:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-05-14T15:48:16Z</published>
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<id>urn:sha1:b7554a70d21582cab97028477941fb692ef248b8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/risc-v/c906] add ioremap &amp;&amp; default param (#7345)</title>
<updated>2023-04-24T01:21:15Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-04-24T01:21:15Z</published>
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<id>urn:sha1:cbedb6b40bea151faaa307225d8b594bb3573ec2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[kernel] 将rt_thread结构体改为显式继承rt_object (#7131)</title>
<updated>2023-04-04T13:06:27Z</updated>
<author>
<name>Shicheng Chu</name>
<email>1468559561@qq.com</email>
</author>
<published>2023-04-04T13:06:27Z</published>
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<id>urn:sha1:93f3cb30e48d5de341bda09fa806120e2bc3f3ad</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>add bl60x/bl70x/bl61x/bl808 (#7063)</title>
<updated>2023-03-19T06:41:18Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-19T06:41:18Z</published>
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<id>urn:sha1:c11f5bb2510c9c961819c554c1e4cc69f7f52ab7</id>
<content type='text'>
Co-authored-by: flyingcys &lt;flyingcys!163.com&gt;</content>
</entry>
<entry>
<title>[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)</title>
<updated>2023-03-17T07:11:38Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-17T07:11:38Z</published>
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<id>urn:sha1:18a14cc9351e9c44df539ad21ce825679bc023ca</id>
<content type='text'>
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c</content>
</entry>
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