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<title>rt-thread.git/libcpu/risc-v/t-head, branch v5.3.0-beta</title>
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<updated>2026-08-21T08:51:33Z</updated>
<entry>
<title>Ensure that c906 uses only the Xuantie MMU properties</title>
<updated>2026-08-21T08:51:33Z</updated>
<author>
<name>rcitach</name>
<email>yearsince@yeah.net</email>
</author>
<published>2026-08-21T05:29:14Z</published>
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<entry>
<title>fix[libcpu][risc-v]:</title>
<updated>2026-02-26T09:26:47Z</updated>
<author>
<name>shuta.lst</name>
<email>shuta.lst@alibaba-inc.com</email>
</author>
<published>2026-02-26T07:24:12Z</published>
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<content type='text'>
 - Implement _noncache() and _cache() function features;
 - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration;
 - Update C908/C906 PTE macro definition configuration;
</content>
</entry>
<entry>
<title>feat[libcpu][t-head][c908]: Support RISC-V Standard Svpbmt Extension For C908;</title>
<updated>2026-02-26T01:42:50Z</updated>
<author>
<name>shuta.lst</name>
<email>shuta.lst@alibaba-inc.com</email>
</author>
<published>2026-02-25T08:29:08Z</published>
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<id>urn:sha1:0dfc5f326209ea5fabea5a5a66368c19ab975ee5</id>
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<entry>
<title>chore: fix typo in components and libcpu</title>
<updated>2026-02-13T13:54:59Z</updated>
<author>
<name>theqengineer</name>
<email>zyrhqu@gmail.com</email>
</author>
<published>2026-02-13T07:04:27Z</published>
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<id>urn:sha1:85b656b14dcfe8a3ab27c819e168dde082ab39ef</id>
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</content>
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<entry>
<title>Reorganize Group names in build system for clarity and IDE integration #10923</title>
<updated>2025-11-16T03:40:53Z</updated>
<author>
<name>Copilot</name>
<email>198982749+Copilot@users.noreply.github.com</email>
</author>
<published>2025-11-16T03:40:53Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>给vector模块添加构建脚本</title>
<updated>2024-11-27T10:04:59Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-11-22T03:58:18Z</published>
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<id>urn:sha1:d3820ed77e26759c3a3d29dad65bbcca371374c6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[kernel] Specification interrupt nested level variable declaration type (#9568)</title>
<updated>2024-10-23T21:08:29Z</updated>
<author>
<name>Yuqiang Wang</name>
<email>yifang.wangyq@foxmail.com</email>
</author>
<published>2024-10-23T21:08:29Z</published>
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<entry>
<title>[libcpu]添加对riscv vector的支持 (#9531)</title>
<updated>2024-10-16T06:10:09Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-10-16T06:10:09Z</published>
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<id>urn:sha1:49b661476393bd9c9fc199362cf4b008c35a9340</id>
<content type='text'>
[libcpu]添加对riscv vector的支持</content>
</entry>
<entry>
<title>删除多余空格</title>
<updated>2024-09-23T04:57:53Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-09-20T02:43:13Z</published>
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<id>urn:sha1:8a53e6d63947a0ee0c60da53d322c75e0f5048cc</id>
<content type='text'>
</content>
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<entry>
<title>[libcpu]rv添加c908 cpu</title>
<updated>2024-09-23T04:57:53Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-09-20T02:17:34Z</published>
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