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<title>rt-thread.git/libcpu/risc-v/virt64/plic.c, branch copilot/remove-finish-function-export-alias</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64/plic.c?h=copilot%2Fremove-finish-function-export-alias</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64/plic.c?h=copilot%2Fremove-finish-function-export-alias'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2025-09-03T01:48:22Z</updated>
<entry>
<title>fix(risc-v, virt64, plic): use volatile rw for claim and complete</title>
<updated>2025-09-03T01:48:22Z</updated>
<author>
<name>Haojin Tang</name>
<email>tanghaojin@outlook.com</email>
</author>
<published>2025-09-02T14:04:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=893ae7d7ba4daecfe4732cb51db8f140dc7211ff'/>
<id>urn:sha1:893ae7d7ba4daecfe4732cb51db8f140dc7211ff</id>
<content type='text'>
</content>
</entry>
<entry>
<title>bsp: qemu-virt64-riscv: remove config RISCV_S_MODE</title>
<updated>2025-01-10T09:14:13Z</updated>
<author>
<name>Chen Wang</name>
<email>unicorn_wang@outlook.com</email>
</author>
<published>2025-01-08T08:39:27Z</published>
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<id>urn:sha1:123ed1be1b17161e64b9b775f7fb9deb1d386416</id>
<content type='text'>
RISCV_S_MODE configuration only affects the code in
libcpu/risc-v/virt64, and the only bsp using this
libcpu is qemu-virt64-riscv.

Considering s-mode is the default mode RT-Thread
running on virt64 machine, it seems unnecessary to
make RISCV_S_MODE a Kconfig option.

Solution: Remove RISCV_S_MODE from Kconfig and define
it as a macro in the code in libcpu/risc-v/virt64.

Plus, due to this macro is only related to virt64, rename
RISCV_S_MODE to RISCV_VIRT64_S_MODE.

Update the .config/rtconfig.h in this patch.

Signed-off-by: Chen Wang &lt;unicorn_wang@outlook.com&gt;
</content>
</entry>
<entry>
<title>feat: libcpu/risc-v: unify interrupt &amp; IO on rv64</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T10:02:15Z</published>
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<id>urn:sha1:e244c196c4f1f5a867891df303476947a7769876</id>
<content type='text'>
This patch aims to unify the two currently separated RISC-V 64-bit
architecture ports, 'virt64' and 'c906', into a single generic
'common64' port. The changes include renaming files and updating
includes to use a unified 'interrupt.h' header, as well as making
adjustments to IO and trap handling to be more consistent between the
two architectures.

Changes:
- Renamed 'rt_interrupt.h' to 'interrupt.h' and updated includes accordingly.
- Unified IO register access functions in 'riscv_io.h'.
- Added 'opcode.h' for portable assembly support.
- Updated 'plic.c' and 'plic.h' to handle interrupts in a unified manner.
- Modified 'trap.c' to handle exceptions and interrupts consistently for 'rv64'.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: kernel/libcpu: fit into ilp32d</title>
<updated>2024-09-01T19:12:34Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-08-28T12:54:55Z</published>
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<id>urn:sha1:dfd8ccf262d53723056490d8858807f792ffa013</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[smart][risc-v/libcpu] port rv64 cpu code (#6704)</title>
<updated>2022-12-10T14:16:42Z</updated>
<author>
<name>Shell</name>
<email>maschareno@outlook.com</email>
</author>
<published>2022-12-10T14:16:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e991be9c51c54883b56ee3d9e7f30db33c404192'/>
<id>urn:sha1:e991be9c51c54883b56ee3d9e7f30db33c404192</id>
<content type='text'>
* [risc-v/libcpu] porting Smart &amp; RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ecf2d8215961ca7c539132b62a72df6072cc3e14'/>
<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
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