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<title>rt-thread.git/libcpu/risc-v/virt64/riscv_mmu.h, branch copilot/create-device-driver-model-docs</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64/riscv_mmu.h?h=copilot%2Fcreate-device-driver-model-docs</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64/riscv_mmu.h?h=copilot%2Fcreate-device-driver-model-docs'/>
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<updated>2024-09-11T22:06:51Z</updated>
<entry>
<title>feat: libcpu/risc-v: unify mmu related works</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T09:58:56Z</published>
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<id>urn:sha1:a00aaab2bac3b44baa55f5f25fe08b2d10c27c9b</id>
<content type='text'>
These changes are designed to standardize the memory management across
'virt64' and 'c906', ensuring efficient handling of address spaces and
page tables.

Changes:
- Creation of ASID management files (`asid.c`) for both 'c906' and
  'virt64' architectures, which is essential for maintaining stability.
- Extensive updates to the MMU configuration and handling in `mmu.c` and `mmu.h` files.
- Addition of functions to manage ASID allocation and switching of page tables.
- For c906, accommodated the early memory setup to the one from virt64.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: kernel/libcpu: fit into ilp32d</title>
<updated>2024-09-01T19:12:34Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-08-28T12:54:55Z</published>
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<id>urn:sha1:dfd8ccf262d53723056490d8858807f792ffa013</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[mm] precise &amp; readable mm fault type (#9047)</title>
<updated>2024-06-07T13:34:03Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-06-07T13:34:03Z</published>
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<id>urn:sha1:f00db6381a383d85f1c145cbebac22967e7d2eb8</id>
<content type='text'>
* [smart] fixup: precise mm fault type

Also, fixup arm64 read access fault

* arm64: using meaningful macro on trap

* fixup: renaming macro</content>
</entry>
<entry>
<title>[ci] open ci check with function declaration warning (#8546)</title>
<updated>2024-02-21T03:45:04Z</updated>
<author>
<name>Yuqiang Wang</name>
<email>2053731441@qq.com</email>
</author>
<published>2024-02-21T03:45:04Z</published>
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<id>urn:sha1:c6bdee3c503a287a0967fd0e3cb6b7a1eb6d0b5e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[smart] fixup: mmap support (#8154)</title>
<updated>2023-10-20T05:28:20Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-10-20T05:28:20Z</published>
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<id>urn:sha1:1d678e559670b89a137f3b771df829f160a7ba83</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>Sync dfs lwp (#8123)</title>
<updated>2023-10-17T05:07:59Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-10-17T05:07:59Z</published>
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<id>urn:sha1:ecd29fda6005ef19c625f194f9311259ba907a78</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/risc-v] support noncached normal memory (#7051)</title>
<updated>2023-03-16T02:26:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-16T02:26:55Z</published>
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<id>urn:sha1:2394e75265891c83e3b9a00634a30c9ef1c7b13a</id>
<content type='text'>
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
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