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<title>rt-thread.git/libcpu/risc-v/virt64/trap.c, branch serialX-dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64/trap.c?h=serialX-dev</id>
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<updated>2023-02-24T06:52:16Z</updated>
<entry>
<title>[rt-smart] handling kernel from accessing unmapped user stack (#6957)</title>
<updated>2023-02-24T06:52:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-24T06:52:16Z</published>
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<id>urn:sha1:382e9bcac746b408b5b01ea2f59338428ab203dd</id>
<content type='text'>
[rt-smart] handling kernel from accessing unmapped user stack</content>
</entry>
<entry>
<title>[rt-smart] porting c906 and D1s to mm (#6848)</title>
<updated>2023-01-16T00:24:03Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-16T00:24:03Z</published>
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<id>urn:sha1:f0dadcb3c390e60463afa5892d2d65e6033d82c8</id>
<content type='text'>
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart][risc-v/libcpu] port rv64 cpu code (#6704)</title>
<updated>2022-12-10T14:16:42Z</updated>
<author>
<name>Shell</name>
<email>maschareno@outlook.com</email>
</author>
<published>2022-12-10T14:16:42Z</published>
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<id>urn:sha1:e991be9c51c54883b56ee3d9e7f30db33c404192</id>
<content type='text'>
* [risc-v/libcpu] porting Smart &amp; RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
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