rt-thread.git/libcpu/risc-v/virt64, branch copilot/create-device-driver-model-docs

[libcpu-riscv]: [surpport SMP]: Add SMP support for qemu-virt64-riscv

2025-12-04T07:42:09Z

1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng

Reorganize Group names in build system for clarity and IDE integration #10923

2025-11-16T03:40:53Z

fix(risc-v, virt64, plic): use volatile rw for claim and complete

2025-09-03T01:48:22Z

fix(risc-v/virt64, cpp): add spaces to fix `Wliteral-suffix`

2025-09-01T10:43:04Z

bsp: qemu-virt64-riscv: remove config RISCV_S_MODE

2025-01-10T09:14:13Z

RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang

给vector模块添加构建脚本

2024-11-27T10:04:59Z

[libcpu][riscv]virt64使用通用vector支持代码

2024-11-27T10:04:59Z

feat: remove redundant codes under virt64, c906

2024-09-13T21:35:00Z

Changes: - create new folder name `common64` and save all common codes of rv64 inside Signed-off-by: Shell

feat: libcpu/risc-v: unify low-level bringups

2024-09-11T22:06:51Z

This patch consolidates the separated architecture-specific code for rv64 (virt64 and c906) under a more unified approach. The changes aim to enhance maintainability and code reuse, reducing duplication between these two architectures while adding small improvements in porting compatibility. Changes: - Modified build scripts (SConscript) for both virt64 and c906 to remove ASID and vector dependencies when not required. - Updated c906's sbi.c and sbi.h to use standard integer types (uint32_t) and include the missing header. - Unified inline function declaration for `sbi_call` across both c906 and virt64 using `rt_inline`. - Disabled FPU and vector in c906's startup assembly file, aligning it with the virt64 handling. - Corrected syscall handler type definitions in c906 for consistency. Signed-off-by: Shell

feat: libcpu/risc-v: unify interrupt & IO on rv64

2024-09-11T22:06:51Z

This patch aims to unify the two currently separated RISC-V 64-bit architecture ports, 'virt64' and 'c906', into a single generic 'common64' port. The changes include renaming files and updating includes to use a unified 'interrupt.h' header, as well as making adjustments to IO and trap handling to be more consistent between the two architectures. Changes: - Renamed 'rt_interrupt.h' to 'interrupt.h' and updated includes accordingly. - Unified IO register access functions in 'riscv_io.h'. - Added 'opcode.h' for portable assembly support. - Updated 'plic.c' and 'plic.h' to handle interrupts in a unified manner. - Modified 'trap.c' to handle exceptions and interrupts consistently for 'rv64'. Signed-off-by: Shell