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<title>rt-thread.git/libcpu/risc-v/virt64, branch copilot/create-dfs2-documentation</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/virt64?h=copilot%2Fcreate-dfs2-documentation</id>
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<updated>2025-09-03T01:48:22Z</updated>
<entry>
<title>fix(risc-v, virt64, plic): use volatile rw for claim and complete</title>
<updated>2025-09-03T01:48:22Z</updated>
<author>
<name>Haojin Tang</name>
<email>tanghaojin@outlook.com</email>
</author>
<published>2025-09-02T14:04:10Z</published>
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<id>urn:sha1:893ae7d7ba4daecfe4732cb51db8f140dc7211ff</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix(risc-v/virt64, cpp): add spaces to fix `Wliteral-suffix`</title>
<updated>2025-09-01T10:43:04Z</updated>
<author>
<name>Haojin Tang</name>
<email>tanghaojin@outlook.com</email>
</author>
<published>2025-09-01T06:10:24Z</published>
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<id>urn:sha1:157d8096344089d6fd8c6de039e8799fbfd12cb9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>bsp: qemu-virt64-riscv: remove config RISCV_S_MODE</title>
<updated>2025-01-10T09:14:13Z</updated>
<author>
<name>Chen Wang</name>
<email>unicorn_wang@outlook.com</email>
</author>
<published>2025-01-08T08:39:27Z</published>
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<id>urn:sha1:123ed1be1b17161e64b9b775f7fb9deb1d386416</id>
<content type='text'>
RISCV_S_MODE configuration only affects the code in
libcpu/risc-v/virt64, and the only bsp using this
libcpu is qemu-virt64-riscv.

Considering s-mode is the default mode RT-Thread
running on virt64 machine, it seems unnecessary to
make RISCV_S_MODE a Kconfig option.

Solution: Remove RISCV_S_MODE from Kconfig and define
it as a macro in the code in libcpu/risc-v/virt64.

Plus, due to this macro is only related to virt64, rename
RISCV_S_MODE to RISCV_VIRT64_S_MODE.

Update the .config/rtconfig.h in this patch.

Signed-off-by: Chen Wang &lt;unicorn_wang@outlook.com&gt;
</content>
</entry>
<entry>
<title>给vector模块添加构建脚本</title>
<updated>2024-11-27T10:04:59Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-11-22T03:58:18Z</published>
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<id>urn:sha1:d3820ed77e26759c3a3d29dad65bbcca371374c6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][riscv]virt64使用通用vector支持代码</title>
<updated>2024-11-27T10:04:59Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-11-21T09:18:35Z</published>
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<id>urn:sha1:3268716c4fdd506487f89b39b09b8f5339882ae5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>feat: remove redundant codes under virt64, c906</title>
<updated>2024-09-13T21:35:00Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-12T03:14:12Z</published>
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<id>urn:sha1:57d002b25e26a5df950b087f0ea2dc7b6feeb7e3</id>
<content type='text'>
Changes:

- create new folder name `common64` and save all common codes of rv64
  inside

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: libcpu/risc-v: unify low-level bringups</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T10:03:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=c78a19ed264adf9a5f90180148d3d7cf441f95b1'/>
<id>urn:sha1:c78a19ed264adf9a5f90180148d3d7cf441f95b1</id>
<content type='text'>
This patch consolidates the separated architecture-specific code for
rv64 (virt64 and c906) under a more unified approach. The changes
aim to enhance maintainability and code reuse, reducing duplication
between these two architectures while adding small improvements in
porting compatibility.

Changes:
- Modified build scripts (SConscript) for both virt64 and c906 to
  remove ASID and vector dependencies when not required.
- Updated c906's sbi.c and sbi.h to use standard integer types
  (uint32_t) and include the missing &lt;stdint.h&gt; header.
- Unified inline function declaration for `sbi_call` across both
  c906 and virt64 using `rt_inline`.
- Disabled FPU and vector in c906's startup assembly file, aligning it
  with the virt64 handling.
- Corrected syscall handler type definitions in c906 for consistency.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: libcpu/risc-v: unify interrupt &amp; IO on rv64</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T10:02:15Z</published>
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<id>urn:sha1:e244c196c4f1f5a867891df303476947a7769876</id>
<content type='text'>
This patch aims to unify the two currently separated RISC-V 64-bit
architecture ports, 'virt64' and 'c906', into a single generic
'common64' port. The changes include renaming files and updating
includes to use a unified 'interrupt.h' header, as well as making
adjustments to IO and trap handling to be more consistent between the
two architectures.

Changes:
- Renamed 'rt_interrupt.h' to 'interrupt.h' and updated includes accordingly.
- Unified IO register access functions in 'riscv_io.h'.
- Added 'opcode.h' for portable assembly support.
- Updated 'plic.c' and 'plic.h' to handle interrupts in a unified manner.
- Modified 'trap.c' to handle exceptions and interrupts consistently for 'rv64'.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: libcpu/risc-v: unify mmu related works</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T09:58:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=a00aaab2bac3b44baa55f5f25fe08b2d10c27c9b'/>
<id>urn:sha1:a00aaab2bac3b44baa55f5f25fe08b2d10c27c9b</id>
<content type='text'>
These changes are designed to standardize the memory management across
'virt64' and 'c906', ensuring efficient handling of address spaces and
page tables.

Changes:
- Creation of ASID management files (`asid.c`) for both 'c906' and
  'virt64' architectures, which is essential for maintaining stability.
- Extensive updates to the MMU configuration and handling in `mmu.c` and `mmu.h` files.
- Addition of functions to manage ASID allocation and switching of page tables.
- For c906, accommodated the early memory setup to the one from virt64.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>feat: libcpu/risc-v: unify context on c906, virt64</title>
<updated>2024-09-11T22:06:51Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-09-02T08:38:42Z</published>
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<id>urn:sha1:7528645f595f2b9d0e89a146ca477bb6849e64c5</id>
<content type='text'>
Changes:
- added config for NEW_CTX_SWITCH
- used new context on c906 sched switch routine
- update _rt_hw_stack_init to fit into NEW_CTX_SWITCH
- separated vector ctx from the generic

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
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