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<title>rt-thread.git/libcpu/risc-v, branch copilot/fix-riscv-none-job-failure</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=copilot%2Ffix-riscv-none-job-failure</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=copilot%2Ffix-riscv-none-job-failure'/>
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<updated>2026-09-15T14:57:55Z</updated>
<entry>
<title>[libcpu][risc-v]Feat: Add OpenSBI SMP support to t-head c908</title>
<updated>2026-09-15T14:57:55Z</updated>
<author>
<name>guanxi.cgh</name>
<email>guanxi.cgh@alibaba-inc.com</email>
</author>
<published>2026-09-04T03:04:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e81494f881526b257165207cf716df1043f1bb2a'/>
<id>urn:sha1:e81494f881526b257165207cf716df1043f1bb2a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][risc-v]Feat: Add mmu SV48/SV57 mode support and add mmu_demo for C908.</title>
<updated>2026-09-15T14:57:55Z</updated>
<author>
<name>guanxi.cgh</name>
<email>guanxi.cgh@alibaba-inc.com</email>
</author>
<published>2026-08-25T13:25:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=a5d9dc884b6f5f61b06664bbf745356416de98cf'/>
<id>urn:sha1:a5d9dc884b6f5f61b06664bbf745356416de98cf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>feat[bsp][xuantie]: c908 support rt-smart #11719</title>
<updated>2026-08-28T04:25:32Z</updated>
<author>
<name>BadmintonMaster</name>
<email>guanxi.cgh@alibaba-inc.com</email>
</author>
<published>2026-08-28T04:25:32Z</published>
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<id>urn:sha1:bf38ee2130634ac6571e816dde81b04818d75444</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Ensure that c906 uses only the Xuantie MMU properties</title>
<updated>2026-08-21T08:51:33Z</updated>
<author>
<name>rcitach</name>
<email>yearsince@yeah.net</email>
</author>
<published>2026-08-21T05:29:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=5ae08713c8b409aef8ba1d887c3f228566537909'/>
<id>urn:sha1:5ae08713c8b409aef8ba1d887c3f228566537909</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][risc-v] Fix PLIC interrupt processing order</title>
<updated>2026-04-07T02:14:56Z</updated>
<author>
<name>FurryAcetylCoA</name>
<email>1109673069@qq.com</email>
</author>
<published>2026-03-31T12:02:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e3cfde245d139f4f6d478a5c59339b1b5d1be9ec'/>
<id>urn:sha1:e3cfde245d139f4f6d478a5c59339b1b5d1be9ec</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix[libcpu][risc-v]:</title>
<updated>2026-02-26T09:26:47Z</updated>
<author>
<name>shuta.lst</name>
<email>shuta.lst@alibaba-inc.com</email>
</author>
<published>2026-02-26T07:24:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=33f8aff9cf0411f0fe6e6d6231f296448387f247'/>
<id>urn:sha1:33f8aff9cf0411f0fe6e6d6231f296448387f247</id>
<content type='text'>
 - Implement _noncache() and _cache() function features;
 - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration;
 - Update C908/C906 PTE macro definition configuration;
</content>
</entry>
<entry>
<title>feat[libcpu][t-head][c908]: Support RISC-V Standard Svpbmt Extension For C908;</title>
<updated>2026-02-26T01:42:50Z</updated>
<author>
<name>shuta.lst</name>
<email>shuta.lst@alibaba-inc.com</email>
</author>
<published>2026-02-25T08:29:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=0dfc5f326209ea5fabea5a5a66368c19ab975ee5'/>
<id>urn:sha1:0dfc5f326209ea5fabea5a5a66368c19ab975ee5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp/gd32] fix gd32vw553 bsp</title>
<updated>2026-02-25T06:54:20Z</updated>
<author>
<name>MuChenger</name>
<email>ws1516081466@gmail.com</email>
</author>
<published>2026-02-25T03:22:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=f610f18a3c796ba1bc404c886b408b01ca814cef'/>
<id>urn:sha1:f610f18a3c796ba1bc404c886b408b01ca814cef</id>
<content type='text'>
</content>
</entry>
<entry>
<title>chore: fix typo in components and libcpu</title>
<updated>2026-02-13T13:54:59Z</updated>
<author>
<name>theqengineer</name>
<email>zyrhqu@gmail.com</email>
</author>
<published>2026-02-13T07:04:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=85b656b14dcfe8a3ab27c819e168dde082ab39ef'/>
<id>urn:sha1:85b656b14dcfe8a3ab27c819e168dde082ab39ef</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[components][clock_time] Refactor time subsystem around clock_time (#11111)</title>
<updated>2026-01-31T09:44:27Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2026-01-31T09:44:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=743b614875fc33257be47ab53b6c5e040ec27893'/>
<id>urn:sha1:743b614875fc33257be47ab53b6c5e040ec27893</id>
<content type='text'>
* [components][clock_time] Refactor time subsystem around clock_time

Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.

Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.

Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.

* [components][clock_time] Use BSP-provided clock timer frequency on riscv64

* [risc-v] Use runtime clock timer frequency for tick and delays

* [bsp] Add clock timer frequency hooks for riscv64 boards

* [bsp] Update Renesas RA driver doc clock_timer link

* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh

* [bsp][rk3500] Update rk3500 clock configuration

* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays

* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci

* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk

Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.

* [bsp][raspi3] select clock time for systimer

* [bsp][hpm5300evk] Trim trailing blank line

* [bsp][hpm5301evklite] Trim trailing blank line

* [bsp][hpm5e00evk] Trim trailing blank line

* [bsp][hpm6200evk] Trim trailing blank line

* [bsp][hpm6300evk] Trim trailing blank line

* [bsp][hpm6750evk] Trim trailing blank line

* [bsp][hpm6750evk2] Trim trailing blank line

* [bsp][hpm6750evkmini] Trim trailing blank line

* [bsp][hpm6800evk] Trim trailing blank line

* [bsp][hpm6e00evk] Trim trailing blank line

* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source

* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.

* [docs][clock_time] add clock time documentation

* [docs][clock_time] Update clock time subsystem documentation

- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file

* [kernel][utest] Trim trailing space

* [clock_time] Fix hrtimer wrap handling

* [clock_time] fix the static rt_inline issue

* [clock_time] fix the rt_clock_hrtimer_control result issue</content>
</entry>
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