rt-thread.git/libcpu/risc-v, branch master

[libcpu][risc-v] Fix ticket spinlock stalls under SMP contention

2026-10-22T09:59:29Z

Eight-core boot on SpacemiT K1 could stall with one CPU in the unlock LR/SC loop, two CPUs allocating tickets, and the remaining CPUs waiting for the scheduler lock. Replace LR/SC ticket allocation with amoadd.w.aqrl and release the lock with a halfword owner update. Order critical-section accesses after acquiring ownership and before releasing it. Verified eight-core boot on K1 with temporary diagnostics and reservation-clearing changes removed. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[bsp][spacemit/k1] first version #11132

2026-10-19T10:49:16Z

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

[risc-v][vector] Restore vstart after vector configuration

2026-10-14T01:13:49Z

[libcpu][risc-v]Feat: Add OpenSBI SMP support to t-head c908

2026-09-15T14:57:55Z

[libcpu][risc-v]Feat: Add mmu SV48/SV57 mode support and add mmu_demo for C908.

2026-09-15T14:57:55Z

feat[bsp][xuantie]: c908 support rt-smart #11719

2026-08-28T04:25:32Z

Ensure that c906 uses only the Xuantie MMU properties

2026-08-21T08:51:33Z

[libcpu][risc-v] Fix PLIC interrupt processing order

2026-04-07T02:14:56Z

fix[libcpu][risc-v]:

2026-02-26T09:26:47Z

- Implement _noncache() and _cache() function features; - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration; - Update C908/C906 PTE macro definition configuration;