rt-thread.git/libcpu/risc-v, branch v3.1.5 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=v3.1.5 2021-04-06T09:33:59Z [libcpu]update GPL license to Apache-2.0 2021-04-06T09:33:59Z yangjie yangjiexaut@126.com 2021-04-06T09:24:28Z urn:sha1:8a8c28f3c27caeb1034e064af16ae18fa4e195da [libcpu] add risc-v e310 porting 2018-05-31T06:53:26Z liang yongxiang tanekliang@gmail.com 2018-05-31T05:01:38Z urn:sha1:32c5b2515f29d1b3a7969da294de015547d69646 [libcpu] remove libcpu/risc-v 2018-05-29T04:59:13Z liang yongxiang tanekliang@gmail.com 2018-05-29T04:50:07Z urn:sha1:5faae3350cddbf406d2d9d257e7727ddd80ea69b [BSP] cleanup for hifive1 bsp. 2017-08-26T03:02:39Z Bernard Xiong bernard.xiong@gmail.com 2017-08-26T03:02:39Z urn:sha1:2ac493698ba0c0578147045f6660add7bb4ad2eb modify： drivers/cpuusage.c 2017-07-31T04:05:45Z zhangjun 2281979437@qq.com 2017-07-31T04:05:45Z urn:sha1:72cfe9dd686d5b3568173fbe6b5509fd7e072fca modify： ../../libcpu/risc-v/e310/stack.c rmove unused macro definition modify： ../../src/idle.c Return to the original version new file： ../../libcpu/risc-v/e310/trap.c 2017-07-31T03:12:28Z zhangjun 2281979437@qq.com 2017-07-31T03:12:28Z urn:sha1:e9f1bdf2dac4dbeeed479e8256dd0449ba39a38c add file that forget to submit before auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h no flashing led new file： ../../src/idle.c recover old file fix bug in context_gcc.s and start_gcc.s: 2017-07-31T02:59:59Z zhangjun 2281979437@qq.com 2017-07-31T02:59:59Z urn:sha1:a5305c05df3e97cd60c621bec87926765ba31228 save mie into stack msh running normaly fix bug in rt_hw_context_switch_interrupt_do 2017-07-30T11:46:28Z zhangjun 2281979437@qq.com 2017-07-30T11:46:28Z urn:sha1:b032dff1616fe64a4dfec63e593f0fac634ef3ab save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt) 修改： ../../libcpu/risc-v/e310/context_gcc.S 2017-07-30T07:34:32Z zhangjun 2281979437@qq.com 2017-07-30T07:34:32Z urn:sha1:2d56a27c20d430f678a77e48f1d00591f4fc4c8b enable interrupt after return form rt_hw_context_switch fix trap_entry 2017-07-29T07:37:20Z zhangjun 2281979437@qq.com 2017-07-29T07:37:20Z urn:sha1:3c51848d33d2c13d0029f3e796af9f78a882eac3