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<title>rt-thread.git/libcpu/risc-v, branch v5.0.0</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=v5.0.0</id>
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<updated>2023-03-30T03:06:21Z</updated>
<entry>
<title>[utest][atomic]添加返回值测试 (#7124)</title>
<updated>2023-03-30T03:06:21Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-30T03:06:21Z</published>
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<id>urn:sha1:38eb3fc40f817ea1dce5223a9bac0d2d3b578bd2</id>
<content type='text'>
* [utest][atomic]添加返回值测试
</content>
</entry>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>[bsp]fix esp32_c3 compile error (#7107)</title>
<updated>2023-03-29T11:01:26Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-29T11:01:26Z</published>
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<id>urn:sha1:0cf3bcf49506ee4a8c5444284b0c9dd5afbf2df3</id>
<content type='text'>
* fix rt_hw_interrupt_install return value

* add __rt_rvstack</content>
</entry>
<entry>
<title>[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)</title>
<updated>2023-03-23T12:06:50Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-23T12:06:50Z</published>
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<id>urn:sha1:de4f23748212dbba7d0250fdac3ae583e74fcbed</id>
<content type='text'>
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;</content>
</entry>
<entry>
<title>[bsp] add bl808 lp core (#7069)</title>
<updated>2023-03-19T15:16:12Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-19T15:16:12Z</published>
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<id>urn:sha1:a538b268588ae668ff897c3719b6a7eef9ac8c0a</id>
<content type='text'>
* Add riscv_32e support

* add bl808 lp core

* update README.md</content>
</entry>
<entry>
<title>add bl60x/bl70x/bl61x/bl808 (#7063)</title>
<updated>2023-03-19T06:41:18Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-19T06:41:18Z</published>
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<id>urn:sha1:c11f5bb2510c9c961819c554c1e4cc69f7f52ab7</id>
<content type='text'>
Co-authored-by: flyingcys &lt;flyingcys!163.com&gt;</content>
</entry>
<entry>
<title>[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)</title>
<updated>2023-03-17T07:11:38Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-17T07:11:38Z</published>
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<id>urn:sha1:18a14cc9351e9c44df539ad21ce825679bc023ca</id>
<content type='text'>
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c</content>
</entry>
<entry>
<title>[libcpu/risc-v] support noncached normal memory (#7051)</title>
<updated>2023-03-16T02:26:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-16T02:26:55Z</published>
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<id>urn:sha1:2394e75265891c83e3b9a00634a30c9ef1c7b13a</id>
<content type='text'>
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed</content>
</entry>
<entry>
<title>[libcpu/riscv/virt64] fix (#5979) (#7040)</title>
<updated>2023-03-11T04:34:14Z</updated>
<author>
<name>zilong</name>
<email>52786674+zilongmix@users.noreply.github.com</email>
</author>
<published>2023-03-11T04:34:14Z</published>
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<id>urn:sha1:50e1f6327d2e03b887dfbff0af2dd87fd41d4d48</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/riscv/c906] fix "next_asid" type error (#7031)</title>
<updated>2023-03-09T12:25:54Z</updated>
<author>
<name>chenhy0106</name>
<email>42792255+chenhy0106@users.noreply.github.com</email>
</author>
<published>2023-03-09T12:25:54Z</published>
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<id>urn:sha1:f6847af0cdd345c5903349dc7e7b04992ecef44f</id>
<content type='text'>
MAX_ASID最大为0x10000，在next_asid==MAX_ASID时进入下一个generation。因此next_asid不能只有16位，否则将不能进入下一个generation。修改rt_uint16_t为rt_uint32_t。</content>
</entry>
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