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<title>rt-thread.git/libcpu/risc-v, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=v5.0.2</id>
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<updated>2023-09-09T01:35:56Z</updated>
<entry>
<title>[smart/syscall] fix exit(2) and add exit_group(2) (#8005)</title>
<updated>2023-09-09T01:35:56Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-09-09T01:35:56Z</published>
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<id>urn:sha1:47b183a2978a8b474e25ec38b37ef5741a50d724</id>
<content type='text'>
Signed-off-by: shell &lt;smokewood@qq.com&gt;
Signed-off-by: shell &lt;wangxiaoyao@rt-thread.com&gt;
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[components/mm] add unmap page API (#7834)</title>
<updated>2023-08-16T07:38:59Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-08-16T07:38:59Z</published>
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<id>urn:sha1:d862816a51ab6fec2321f0410e8aea2d05507542</id>
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Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[libcpu][risc-v][common] Fix application crash on risc-v soc if FPU is</title>
<updated>2023-08-12T01:20:28Z</updated>
<author>
<name>Fan YANG</name>
<email>fan.yang@hpmicro.com</email>
</author>
<published>2023-08-11T13:05:52Z</published>
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<id>urn:sha1:5308cc47161d8e2f9fdb680738e023ef16af1e2b</id>
<content type='text'>
enabled

- Defined ARCH_RISCV_FPU once the __riscv_flen macro was detected

Signed-off-by: Fan YANG &lt;fan.yang@hpmicro.com&gt;
</content>
</entry>
<entry>
<title>[libcpu][risc-v][common] Avoid using t0 before being saved</title>
<updated>2023-08-09T05:07:11Z</updated>
<author>
<name>Fan YANG</name>
<email>fan.yang@hpmicro.com</email>
</author>
<published>2023-08-09T02:51:32Z</published>
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<id>urn:sha1:5ac509b6d031b29e2d95c52fc179771e62664378</id>
<content type='text'>
- Fixed the issue that t0 was modified unexpectedly before being saved

Signed-off-by: Fan YANG &lt;fan.yang@hpmicro.com&gt;
</content>
</entry>
<entry>
<title>rt_hw_cpu_shutdown: implement default weak function</title>
<updated>2023-08-09T02:34:25Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-08-07T16:42:10Z</published>
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<id>urn:sha1:c6a2f5b7bdee378cc868ee9284e760ebbdf635f0</id>
<content type='text'>
and remvoe duplicated default functions in each cpu/bsp level
</content>
</entry>
<entry>
<title>🐞 fix(ktime): fix wrong boottime</title>
<updated>2023-07-27T03:35:29Z</updated>
<author>
<name>xqyjlj</name>
<email>xqyjlj@126.com</email>
</author>
<published>2023-07-26T06:48:00Z</published>
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<id>urn:sha1:d23dd56692c6cff65480fbed286362889c96c7ba</id>
<content type='text'>
因为tick从中断到设置中间的时延特别大，因此暂不采用tick做基准时间，直接取gtime的cnt做基准时间
</content>
</entry>
<entry>
<title>[time]时钟框架重构 (#7794)</title>
<updated>2023-07-17T12:11:58Z</updated>
<author>
<name>xqyjlj</name>
<email>xqyjlj@126.com</email>
</author>
<published>2023-07-17T12:11:58Z</published>
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<id>urn:sha1:0eb75ced70a514051fcc6a8f1d232e195b15b4a0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp]add cv1800b (#7753)</title>
<updated>2023-06-29T16:05:55Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-06-29T16:05:55Z</published>
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<id>urn:sha1:c78f64689142cd36357edbe8db3b60a3c5c00e07</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[risc-v][libcpu] 删去无用局部变量 (#7634)</title>
<updated>2023-06-07T21:04:12Z</updated>
<author>
<name>Liu,Yuan</name>
<email>89723088+linshire@users.noreply.github.com</email>
</author>
<published>2023-06-07T21:04:12Z</published>
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<id>urn:sha1:1d8165851b7fef9a4ec4903154b5b7234fe141b5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[atomic] add stdc atomic detection. (#7536)</title>
<updated>2023-05-20T15:41:29Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2023-05-20T15:41:29Z</published>
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<id>urn:sha1:4b4c3c85f2ac82f12d5527ef1a6794b2189a9eee</id>
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