rt-thread.git/libcpu/risc-v, branch v5.2.2Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v?h=v5.2.22025-09-03T01:48:22Zfix(risc-v, virt64, plic): use volatile rw for claim and complete2025-09-03T01:48:22ZHaojin Tangtanghaojin@outlook.com2025-09-02T14:04:10Zurn:sha1:893ae7d7ba4daecfe4732cb51db8f140dc7211fffix(risc-v, mmu): fix type mismatch of `_query`2025-09-01T10:44:24ZHaojin Tangtanghaojin@outlook.com2025-09-01T07:23:29Zurn:sha1:db4fb4c243195f43d5c29caf16f80d9e349c2e78fix(risc-v/virt64, cpp): add spaces to fix `Wliteral-suffix`2025-09-01T10:43:04ZHaojin Tangtanghaojin@outlook.com2025-09-01T06:10:24Zurn:sha1:157d8096344089d6fd8c6de039e8799fbfd12cb9fix(riscv, cpp): remove `rt_hw_cpu_id` in `cpuport.h` to fix error2025-09-01T10:42:08ZHaojin Tangtanghaojin@outlook.com2025-09-01T04:58:57Zurn:sha1:b27e405faa8616afda9ee8874416a36e9b6d3ba3[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access2025-07-23T01:38:35ZYulong Wang2302147681@qq.com2025-07-12T13:10:48Zurn:sha1:e7a40ae6ec1fdcb0d74a4902cfbd50aee7ee8e8f[bsp]增加超睿DP1000 bsp支持2025-05-30T05:32:58ZZhangJing161287203+zhangjing0303@users.noreply.github.com2025-05-30T05:32:58Zurn:sha1:c3d33f39d4d822ed326d52853627e878fb18f7a2移除无用文件，该文件未被任何BSP使用2025-05-30T01:32:08ZYaochenger1516081466@qq.com2025-05-29T05:32:25Zurn:sha1:f4e619a17c17cd093c2cc37e04e0159e0ac79388[libcpu/common] 修正对RV32E的支持，RV32E不支持s2寄存器，修改为s1寄存器2025-05-30T01:32:08ZYaochenger1516081466@qq.com2025-05-29T03:30:04Zurn:sha1:5889db68191a563bc0d8d2439a0e38e6bf9b4ecc[libcpu][risc-v]:add comment for the round down of symb_pc2025-05-28T11:37:51Zzhangjingzhangjing@ultrarisc.com2025-05-28T09:38:54Zurn:sha1:e3d7bbb47c0728f8c4b5a4837a2075513093ab51[libcpu][risc-v] fix:only map the 1GB space where the original code segment is located2025-05-28T11:37:51Zzhangjingzhangjing@ultrarisc.com2025-04-03T02:30:30Zurn:sha1:3922ec7e99c85d9258e90b1c3fccf3abdd3ae939