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<title>rt-thread.git/libcpu, branch copilot/bug-security-related-issue</title>
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<updated>2026-06-08T06:57:37Z</updated>
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<title>[bsp][zynqmp-a53-dfzu2eg] enable full dm</title>
<updated>2026-06-08T06:57:37Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
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<published>2026-03-06T13:10:56Z</published>
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This is a builtin fdt example BSP

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
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<entry>
<title>fix IAR build error</title>
<updated>2026-06-02T10:05:02Z</updated>
<author>
<name>蒙蒙plus</name>
<email>chengmeng_2@outlook.com</email>
</author>
<published>2026-05-28T10:08:24Z</published>
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<entry>
<title>[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management</title>
<updated>2026-05-19T08:34:34Z</updated>
<author>
<name>Evlers</name>
<email>1425295900@qq.com</email>
</author>
<published>2026-05-19T07:07:23Z</published>
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<entry>
<title>feat(core): Add Cortex-M4 interrupt context helpers</title>
<updated>2026-04-08T10:58:33Z</updated>
<author>
<name>wdfk-prog</name>
<email>1425075683@qq.com</email>
</author>
<published>2026-04-08T05:45:46Z</published>
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<entry>
<title>[libcpu][risc-v] Fix PLIC interrupt processing order</title>
<updated>2026-04-07T02:14:56Z</updated>
<author>
<name>FurryAcetylCoA</name>
<email>1109673069@qq.com</email>
</author>
<published>2026-03-31T12:02:59Z</published>
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<entry>
<title>fix(libcpu): correct arm mpu region validation precedence</title>
<updated>2026-04-07T02:13:33Z</updated>
<author>
<name>AFWEF_147</name>
<email>olm_cse@hust.edu.cn</email>
</author>
<published>2026-03-26T13:55:23Z</published>
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<entry>
<title>fix(libcpu): validate ia32 pic irq vectors</title>
<updated>2026-04-07T02:08:17Z</updated>
<author>
<name>AFWEF_147</name>
<email>olm_cse@hust.edu.cn</email>
</author>
<published>2026-03-26T13:55:23Z</published>
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<id>urn:sha1:dedff58dd303498516a60953482991be745d0b30</id>
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<entry>
<title>fix(libcpu): validate arm irq vectors before masking</title>
<updated>2026-04-07T02:07:41Z</updated>
<author>
<name>AFWEF_147</name>
<email>olm_cse@hust.edu.cn</email>
</author>
<published>2026-03-26T13:55:23Z</published>
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<id>urn:sha1:21d223f08986e3252eb0e8ff4510efe0e0e3877c</id>
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<entry>
<title>[docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S</title>
<updated>2026-04-03T12:13:35Z</updated>
<author>
<name>laidene</name>
<email>228526434@qq.com</email>
</author>
<published>2026-04-02T01:36:07Z</published>
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<id>urn:sha1:11a1348ed6d2490a54e0e248fdf031119d5779ff</id>
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<entry>
<title>feat[bsp][xuantie]: c/r serial cpus support SMP;</title>
<updated>2026-03-20T07:47:42Z</updated>
<author>
<name>shuta.lst</name>
<email>shuta.lst@alibaba-inc.com</email>
</author>
<published>2026-03-17T14:36:10Z</published>
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