rt-thread.git/libcpu, branch copilot/create-device-driver-model-docs

[docs][libcpu][arm][cortex-a] update comment for start_gcc.S #11089

2025-12-26T13:04:23Z

[libcpu][aarch64] Update for DM

2025-12-19T13:18:54Z

1. PSCI port to system power. 2. Support builtin fdt. 3. Update system aspace size. 4. Support DMA memory probe. 5. Fixup not backtrace in Serror for device bus fault. Signed-off-by: GuEe-GUI <2991707448@qq.com>

update: [libcpu][risc-v][common] allow overriding isr numbers for MCU

2025-12-11T09:04:14Z

- allow overriding the isr numbers via RT_HW_ISR_NUM macro Signed-off-by: Fan YANG

[libcpu-riscv]: [surpport SMP]: Add SMP support for qemu-virt64-riscv

2025-12-04T07:42:09Z

1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng

Reorganize Group names in build system for clarity and IDE integration #10923

2025-11-16T03:40:53Z

[libcpu][cortex-a] Refactor FPU stack initialization for maintainability (#10919)

2025-11-11T20:34:34Z

* Initial plan * [libcpu][cortex-a] Improve FPU stack initialization implementation Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> * [libcpu][cortex-a] Replace FPU init loop with rt_memset Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

[Components] Remove vbus component and realview-a8-vmm libcpu (#10863)

2025-11-07T09:03:05Z

* Initial plan * Remove vbus component and related code Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

[libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch

2025-11-02T08:23:31Z

The context_gcc.S file was incorrectly marked as cortex-m4 in both the doxygen comment and .cpu directive, while the IAR and KEIL versions correctly specify cortex-m33. This file uses ARMv8-M specific features (PSPLIM register, TrustZone support) that are not available in Cortex-M4. Changes: - Update doxygen group from cortex-m4 to cortex-m33 - Change .cpu directive from cortex-m4 to cortex-m33

aarch64: document the CNTFRQ_EL0

2025-10-23T14:08:05Z

Signed-off-by: Yonggang Luo

[aarch64] Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000

2025-10-21T02:12:35Z