rt-thread.git/libcpu, branch copilot/fix-riscv-none-job-failure

[libcpu][risc-v]Feat: Add OpenSBI SMP support to t-head c908

2026-09-15T14:57:55Z

[libcpu][risc-v]Feat: Add mmu SV48/SV57 mode support and add mmu_demo for C908.

2026-09-15T14:57:55Z

[libcpu] Fix RZ/N2L interrupt dispatch

2026-09-10T02:09:17Z

fix[arm][cortex-m4]: clarify MPU permission expressions

2026-09-01T01:39:10Z

feat[bsp][xuantie]: c908 support rt-smart #11719

2026-08-28T04:25:32Z

[arm][cortex-m4] Add hardware stack guard support

2026-08-26T02:37:02Z

Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only available on Cortex-M7 and Cortex-M33. Core porting (libcpu/arm/cortex-m4/): - Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only difference is the default memory type attribute: Cortex-M4 has no L1 cache, so the cacheability bits are reduced to three cases. - Add rt_hw_stack_guard_init() to cpuport.c. - Add missing #include to context_gcc.S and invoke rt_hw_mpu_table_switch() in the PendSV context switch path. - Update SConscript to exclude mpu.c when memory protection is disabled. BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/): - board.h: include rtthread.h and define NUM_STATIC_REGIONS. - board.c: define static_regions[] marking the Flash region read-only, guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.

Ensure that c906 uses only the Xuantie MMU properties

2026-08-21T08:51:33Z

[bsp/raspberry-pi] update DM support

2026-08-16T11:56:03Z

- reorganize common Raspberry Pi drivers under the device framework - add the Raspberry Pi 5 BSP, configuration and documentation - add BCM2712 and DesignWare AXI DMA controller support - distinguish BCM2712 DMA32 and DMA40 channels by channel mask - restore DesignWare AXI DMA enable bits after controller reset - support a shared AXI maximum burst length across DMA channels Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][dma] Update DMA (#11678)

2026-08-14T04:42:01Z

* [dm][dma] update DMA interface Extend DMA mapping to honor OFW dma-ranges even when no reserved memory pool is present, and add PCI host-bridge DMA-region translation for PCI devices. Prefer 32-bit-addressable allocations for translated devices, improve pool allocation fallbacks and synchronization, and establish a linear mapping for installed DMA pools when possible. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [dm][dma] fixup PL330 work flow Fix PL330 channel allocation so device-tree cells select peripheral request lines rather than execution channels. Generate proper peripheral DMA microcode using DMAWFP, DMALDP, DMASTP, and DMAFLUSHP, encode burst lengths correctly, honor transfer direction and non-secure attributes, and allocate microcode from DMA-coherent memory. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format * drivers: dma: fix diagnostic format types * style: format DMA changes for current master --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

refactor(pic): dispatch NVIC IRQs through traps

2026-08-12T04:54:50Z