rt-thread.git/libcpu, branch copilot/refactor-hwtimer-ktime-cputime

[libcpu-riscv]: [surpport SMP]: Add SMP support for qemu-virt64-riscv

2025-12-04T07:42:09Z

1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng

Reorganize Group names in build system for clarity and IDE integration #10923

2025-11-16T03:40:53Z

[libcpu][cortex-a] Refactor FPU stack initialization for maintainability (#10919)

2025-11-11T20:34:34Z

* Initial plan * [libcpu][cortex-a] Improve FPU stack initialization implementation Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> * [libcpu][cortex-a] Replace FPU init loop with rt_memset Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

[Components] Remove vbus component and realview-a8-vmm libcpu (#10863)

2025-11-07T09:03:05Z

* Initial plan * Remove vbus component and related code Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

[libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch

2025-11-02T08:23:31Z

The context_gcc.S file was incorrectly marked as cortex-m4 in both the doxygen comment and .cpu directive, while the IAR and KEIL versions correctly specify cortex-m33. This file uses ARMv8-M specific features (PSPLIM register, TrustZone support) that are not available in Cortex-M4. Changes: - Update doxygen group from cortex-m4 to cortex-m33 - Change .cpu directive from cortex-m4 to cortex-m33

aarch64: document the CNTFRQ_EL0

2025-10-23T14:08:05Z

Signed-off-by: Yonggang Luo

[aarch64] Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000

2025-10-21T02:12:35Z

Remove unused rt_hw_set_gtimer_frq

2025-10-13T13:44:36Z

bsp/w60x: fixes cppcheck: (#10781)

2025-10-11T01:28:52Z

[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError] [cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]

Remove rarely used rt_time_t

2025-10-10T12:21:40Z

next_delay should be rt_tick_t Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME