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<title>rt-thread.git/libcpu, branch stable-v3.0.x</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu?h=stable-v3.0.x</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu?h=stable-v3.0.x'/>
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<updated>2018-05-31T06:53:26Z</updated>
<entry>
<title>[libcpu] add risc-v e310 porting</title>
<updated>2018-05-31T06:53:26Z</updated>
<author>
<name>liang yongxiang</name>
<email>tanekliang@gmail.com</email>
</author>
<published>2018-05-31T05:01:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=32c5b2515f29d1b3a7969da294de015547d69646'/>
<id>urn:sha1:32c5b2515f29d1b3a7969da294de015547d69646</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge pull request #1484 from TanekLiang/riscv-update</title>
<updated>2018-05-29T08:20:39Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2018-05-29T08:20:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=fe691c2ab3c97f491fae2f8d24a8cd019bb21469'/>
<id>urn:sha1:fe691c2ab3c97f491fae2f8d24a8cd019bb21469</id>
<content type='text'>
remove hifive1 bsp and risc-v/e310 porting</content>
</entry>
<entry>
<title>[libcpu] remove nds32 porting</title>
<updated>2018-05-29T04:59:54Z</updated>
<author>
<name>liang yongxiang</name>
<email>tanekliang@gmail.com</email>
</author>
<published>2018-05-29T04:52:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=46b9be6038f2456a2e16d1866934aec1b94f34a7'/>
<id>urn:sha1:46b9be6038f2456a2e16d1866934aec1b94f34a7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] remove libcpu/risc-v</title>
<updated>2018-05-29T04:59:13Z</updated>
<author>
<name>liang yongxiang</name>
<email>tanekliang@gmail.com</email>
</author>
<published>2018-05-29T04:50:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=5faae3350cddbf406d2d9d257e7727ddd80ea69b'/>
<id>urn:sha1:5faae3350cddbf406d2d9d257e7727ddd80ea69b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp/ls1cdev]跟上一提交，漏提两个文件</title>
<updated>2018-05-12T11:36:08Z</updated>
<author>
<name>zhuangwei123</name>
<email>zhuangwei@nblink-tech.com</email>
</author>
<published>2018-05-12T11:36:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=330bdf6989bf06df6e5df5fa1e5426e8577717fa'/>
<id>urn:sha1:330bdf6989bf06df6e5df5fa1e5426e8577717fa</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp/ls1cdev]添加自引导特性，添加配置选项</title>
<updated>2018-05-12T11:33:32Z</updated>
<author>
<name>zhuangwei123</name>
<email>zhuangwei@nblink-tech.com</email>
</author>
<published>2018-05-12T11:33:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=9a7caed323b8f111b5e9ad7e22462a12516ae1d6'/>
<id>urn:sha1:9a7caed323b8f111b5e9ad7e22462a12516ae1d6</id>
<content type='text'>
1、添加自引导特性，添加配置选项
2、修复cpuport.c的bug
3、修复ls1c_pin.c不能默认复用的bug
</content>
</entry>
<entry>
<title>[libcpu]: fixed #1196 FPU FPCA issue.</title>
<updated>2018-01-31T10:54:11Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2018-01-31T10:54:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=dd1041bb7fe056c2b89463eccbbbac701a16bea2'/>
<id>urn:sha1:dd1041bb7fe056c2b89463eccbbbac701a16bea2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge pull request #1124 from SummerGGift/add_arm_8-byte_alignment</title>
<updated>2017-12-21T09:07:34Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2017-12-21T09:07:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=d78f5eb6740310649db8e7f4ba81afeca826a5d5'/>
<id>urn:sha1:d78f5eb6740310649db8e7f4ba81afeca826a5d5</id>
<content type='text'>
[libcpu]: add 8-byte alignment for arm architecture &amp;&amp; optimize code …</content>
</entry>
<entry>
<title>[libcpu]: add 8-byte alignment for arm architecture &amp;&amp; optimize code format</title>
<updated>2017-12-21T08:37:38Z</updated>
<author>
<name>SummerGift</name>
<email>zy_770077@qq.com</email>
</author>
<published>2017-12-21T08:32:35Z</published>
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<id>urn:sha1:fc7a5abc7635a1b37bd9202072f279e9930e5eb5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge pull request #1123 from SummerGGift/8-byte_alignment</title>
<updated>2017-12-21T07:36:21Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2017-12-21T07:36:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=cc75366fdafcf34fbe916a77ce82194c885d3f13'/>
<id>urn:sha1:cc75366fdafcf34fbe916a77ce82194c885d3f13</id>
<content type='text'>
[libcpu]: add 8-byte alignment for armv6 architecture</content>
</entry>
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