[bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 (#11870)

2026-10-22T07:42:35Z

* [bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 - Adapt ESP32-C3/C6 BSP to ESP-IDF v6.1; bump RISC-V toolchain to gcc 15.2 - C6: re-enable SPI with board-local drv_spi.c; add devices.spi to CI attachconfig; drop shared drv_spi.c spi_command_t hack - C6: fix ADC oneshot multi-channel unit handle and mutex - C3: fix portTRY_ENTER_CRITICAL_SAFE expansion in portmacro.h - Compat with RT-Thread-packages/esp-idf rtt-dev used by CI: map SYSTIMER_* to SYSTIMER_LL_* (C3 and C6 board.c), accept uart_periph.h from hal/ or soc/ - Fix clang-format and cppcheck issues in the compat code Signed-off-by: seteiro Co-Authored-By: Grok * ci: retrigger after esp-idf#18 merged * bsp: ESP: fix C6 ADC for IDF 6.1 (adc_ll bus clock) Replace removed PERIPH_SARADC_MODULE with adc_ll_enable_bus_clock / adc_ll_reset_register when ESP_IDF_VERSION >= 6.0.0. --------- Signed-off-by: seteiro Co-authored-by: Grok

[action/ci] add cpu and arch

2024-08-25T14:54:47Z

[action] add toolchain download link

2024-08-25T05:36:50Z

[action/ci] Add bsp detail python script

2024-08-25T05:36:50Z

rt-thread.git/tools/ci/bsp_detail.py, branch master

[bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 (#11870)

[action/ci] add cpu and arch

[action] add toolchain download link

[action/ci] Add bsp detail python script