diff options
| author | Fan YANG <[email protected]> | 2024-08-12 16:53:02 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2024-08-26 10:41:15 +0800 |
| commit | 6c085218a3efc54509e7d5e250b3eb890483834a (patch) | |
| tree | 7ce6cdf1c84a26609898ea12c37a62879c5bbe86 | |
| parent | e19b63e5fbc287dd8d554d7128aaf3db5db84549 (diff) | |
[bsp][hpmicro][hpm6e00evk] add hpm6e00evk support
- added hpm6e00evk support
Signed-off-by: Fan YANG <[email protected]>
43 files changed, 10243 insertions, 0 deletions
diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 6c15807f67..26c8053f71 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -341,6 +341,7 @@ jobs: - "hpmicro/hpm5300evk" - "hpmicro/hpm5301evklite" - "hpmicro/hpm6800evk" + - "hpmicro/hpm6e00evk" - RTT_BSP: "llvm-arm" RTT_TOOL_CHAIN: "llvm-arm" SUB_RTT_BSP: diff --git a/bsp/hpmicro/hpm6e00evk/.config b/bsp/hpmicro/hpm6e00evk/.config new file mode 100644 index 0000000000..c4b6d48af8 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/.config @@ -0,0 +1,1194 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6E00=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_PWMV2 is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/hpmicro/hpm6e00evk/Kconfig b/bsp/hpmicro/hpm6e00evk/Kconfig new file mode 100644 index 0000000000..73238d3a13 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hpmicro/hpm6e00evk/README.md b/bsp/hpmicro/hpm6e00evk/README.md new file mode 100644 index 0000000000..d01a32f084 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/README.md @@ -0,0 +1,115 @@ +# HPMicro HPM6E00EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6E00EVK development board. + +The document consists of the following parts: + +- HPM6E00EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, Audio, motor control，etc. + + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6800EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/README_zh.md b/bsp/hpmicro/hpm6e00evk/README_zh.md new file mode 100644 index 0000000000..9ac8ba5b46 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/README_zh.md @@ -0,0 +1,114 @@ +# 先楫 HPM6E00EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6E00EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6E00EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。 + +开发板外观如下图所示： + + + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6800EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/SConscript b/bsp/hpmicro/hpm6e00evk/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6e00evk/SConstruct b/bsp/hpmicro/hpm6e00evk/SConstruct new file mode 100644 index 0000000000..d4047fc180 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6e00evk/applications/SConscript b/bsp/hpmicro/hpm6e00evk/applications/SConscript new file mode 100644 index 0000000000..a65aa4d855 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6e00evk/applications/main.c b/bsp/hpmicro/hpm6e00evk/applications/main.c new file mode 100644 index 0000000000..a5a7f07c73 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/applications/main.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6e00evk/board/Kconfig b/bsp/hpmicro/hpm6e00evk/board/Kconfig new file mode 100644 index 0000000000..180c7d1a05 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/Kconfig @@ -0,0 +1,302 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6E00 + bool + select SOC_SERIES_HPM6E00 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_ENET_PHY_RTL8211 + bool + default n + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI7 + bool "Enable SPI7" + default n + if BSP_USING_SPI7 + config BSP_SPI7_USING_DMA + bool "Enable SPI7 DMA" + default n + choice + prompt "Select SPI7 CS TYPE" + default BSP_SPI7_USING_SOFT_CS + config BSP_SPI7_USING_SOFT_CS + bool "Enable SPI7 software cs" + config BSP_SPI7_USING_HARD_CS + bool "Enable SPI7 hardware cs" + endchoice + endif + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + default BSP_USING_ETH0 + + config BSP_USING_ETH0 + bool "Enable ETH0" + select BSP_USING_ENET_PHY_RTL8211 + endchoice + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + endif + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + endif + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S3 + bool "Enable I2S3" + default y + config BSP_USING_AUDIO_CODEC_WM8960 + bool "Enable audio codec on board" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + select RT_USING_CACHE + default n + endif + + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_PWMV2 + bool "Enable PWM" + default n + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + config BSP_USING_MCAN4 + bool "Enable MCAN4" + default n + config BSP_USING_MCAN5 + bool "Enable MCAN5" + default n + config BSP_USING_MCAN6 + bool "Enable MCAN6" + default n + config BSP_USING_MCAN7 + bool "Enable MCAN7" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + endif + endif + +endmenu + +endmenu + diff --git a/bsp/hpmicro/hpm6e00evk/board/SConscript b/bsp/hpmicro/hpm6e00evk/board/SConscript new file mode 100644 index 0000000000..d6bfd64ec2 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + hpm_wm8960.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6880'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6e00evk/board/board.c b/bsp/hpmicro/hpm6e00evk/board/board.c new file mode 100644 index 0000000000..fc95b92eea --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/board.c @@ -0,0 +1,1132 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_pcfg_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_femc_drv.h" +#include "hpm_pwmv2_drv.h" +#include "hpm_esc_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb0)); + printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif)); + printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis)); + printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic)); + printf("axin:\t\t %dHz\n", clock_get_frequency(clock_axin)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_print_banner(void) +{ + const uint8_t banner[] = { "\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n" }; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +static void board_turnoff_rgb_led(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PE_SET(BOARD_LED_OFF_LEVEL); + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; + + HPM_IOC->PAD[IOC_PAD_PE14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PE15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = pad_ctl; +} + +void board_init(void) +{ + board_turnoff_rgb_led(); + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_core1(void) +{ + board_init_console(); + board_init_pmp(); +} + +void board_init_sdram_pins(void) +{ + init_femc_pins(); +} + +uint32_t board_init_femc_clock(void) +{ + clock_add_to_group(clock_femc, 0); + + /* Default FEMC clock is 166MHz */ + + /* Configure the FEMC to 133MHz */ + /* clock_set_source_divider(clock_femc, clk_src_pll1_clk0, 6U); */ + + return clock_get_frequency(clock_femc); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + } else if (ptr == HPM_I2C4) { + clock_add_to_group(clock_i2c4, 0); + } else if (ptr == HPM_I2C5) { + clock_add_to_group(clock_i2c5, 0); + } else if (ptr == HPM_I2C6) { + clock_add_to_group(clock_i2c6, 0); + } else if (ptr == HPM_I2C7) { + clock_add_to_group(clock_i2c7, 0); + } else { + ; + } + + /* Configure the I2C clock to 24MHz */ + /* clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); */ + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + /* SPI1 clock configure */ + clock_add_to_group(clock_spi1, 0); + /* clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); */ + + return clock_get_frequency(clock_spi1); + } else if (ptr == HPM_SPI3) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi3, 0); + /* clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); */ + + return clock_get_frequency(clock_spi3); + } else if (ptr == HPM_SPI6) { + /* SPI6 clock configure */ + clock_add_to_group(clock_spi6, 0); + /* clock_set_source_divider(clock_spi6, clk_src_pll0_clk0, 5U); */ + + return clock_get_frequency(clock_spi6); + } else if (ptr == HPM_SPI7) { + /* SPI6 clock configure */ + clock_add_to_group(clock_spi7, 0); + /* clock_set_source_divider(clock_spi6, clk_src_pll0_clk0, 5U); */ + + return clock_get_frequency(clock_spi7); + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + /* Key A*/ + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); + /* Key B*/ + gpio_set_pin_input(BOARD_APP_GPIO_CTRL2, BOARD_APP_GPIO_INDEX2, BOARD_APP_GPIO_PIN2); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_led_pins(void) +{ + board_turnoff_rgb_led(); + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_led_toggle(void) +{ +#ifdef BOARD_LED_TOGGLE_RGB + static uint8_t i; + switch (i) { + case 1: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + + case 2: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL); + break; + + case 0: + default: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + } + i++; + i = i % 3; +#else + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +#endif +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +static void set_rgb_output_off(PWMV2_Type *ptr, uint8_t counter, uint8_t channel, uint8_t shadow_id, uint8_t cmp_id) +{ + +} + +void board_init_rgb_pwm_pins(void) +{ + board_turnoff_rgb_led(); + + set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_COUNTER_INDEX, BOARD_RED_PWM_OUT_CH, BOARD_RED_PWM_SHADOW_ID, BOARD_RED_PWM_CMP_ID); + set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_COUNTER_INDEX, BOARD_GREEN_PWM_OUT_CH, BOARD_GREEN_PWM_SHADOW_ID, BOARD_GREEN_PWM_CMP_ID); + set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_COUNTER_INDEX, BOARD_BLUE_PWM_OUT_CH, BOARD_BLUE_PWM_SHADOW_ID, BOARD_BLUE_PWM_CMP_ID); + + init_led_pins_as_pwm(); + +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwmv2_channel_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT_CH); + break; + case BOARD_RGB_GREEN: + pwmv2_channel_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT_CH); + break; + case BOARD_RGB_BLUE: + pwmv2_channel_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT_CH); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwmv2_channel_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT_CH); + break; + case BOARD_RGB_GREEN: + pwmv2_channel_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT_CH); + break; + case BOARD_RGB_BLUE: + pwmv2_channel_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT_CH); + break; + default: + while (1) { + ; + } + } +} + +void board_init_pmp(void) +{ + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } + pmp_config(&pmp_entry[0], index); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32ul * 1000ul * 9u); + + /* select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_ahb0, 0); + clock_add_to_group(clock_axif, 0); + clock_add_to_group(clock_axis, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_axin, 0); + clock_add_to_group(clock_rom0, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_ram1, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_femc, 0); + + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_gptmr4, 0); + clock_add_to_group(clock_gptmr5, 0); + clock_add_to_group(clock_gptmr6, 0); + clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_ptpc, 0); + + clock_add_to_group(clock_puart, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_watchdog1, 0); + clock_add_to_group(clock_watchdog2, 0); + clock_add_to_group(clock_watchdog3, 0); + clock_add_to_group(clock_pwdg, 0); + + clock_add_to_group(clock_qei0, 0); + clock_add_to_group(clock_qei1, 0); + clock_add_to_group(clock_qei2, 0); + clock_add_to_group(clock_qei3, 0); + clock_add_to_group(clock_qeo0, 0); + clock_add_to_group(clock_qeo1, 0); + clock_add_to_group(clock_qeo2, 0); + clock_add_to_group(clock_qeo3, 0); + clock_add_to_group(clock_pwm0, 0); + clock_add_to_group(clock_pwm1, 0); + clock_add_to_group(clock_pwm2, 0); + clock_add_to_group(clock_pwm3, 0); + clock_add_to_group(clock_rdc0, 0); + clock_add_to_group(clock_rdc1, 0); + clock_add_to_group(clock_sdm0, 0); + clock_add_to_group(clock_sdm1, 0); + clock_add_to_group(clock_plb0, 0); + clock_add_to_group(clock_sei0, 0); + clock_add_to_group(clock_mtg0, 0); + clock_add_to_group(clock_mtg1, 0); + clock_add_to_group(clock_vsc0, 0); + clock_add_to_group(clock_vsc1, 0); + clock_add_to_group(clock_clc0, 0); + clock_add_to_group(clock_clc1, 0); + clock_add_to_group(clock_emds, 0); + + clock_add_to_group(clock_cmp0, 0); + clock_add_to_group(clock_cmp1, 0); + clock_add_to_group(clock_cmp2, 0); + clock_add_to_group(clock_cmp3, 0); + + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_mbx1, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_ppi0, 0); + clock_add_to_group(clock_lobs, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_pka, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_ffa0, 0); + + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_esc0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_ptp0, 0); + clock_add_to_group(clock_ntmr0, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_tsn1, 0); + clock_add_to_group(clock_tsn2, 0); + clock_add_to_group(clock_tsn3, 0); + + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + clock_add_to_group(clock_adc3, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_cpu1, 0); + clock_add_to_group(clock_mchtmr1, 1); + + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); + + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); + + clock_update_core_clock(); +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); + } else { + /* Not supported */ + } + return freq; +} + +#ifdef INIT_EXT_RAM_FOR_DATA +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t femc_clk_in_hz; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); + + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; + + femc_default_config(HPM_FEMC, &config); + femc_init(HPM_FEMC, &config); + + femc_get_typical_sdram_config(HPM_FEMC, &sdram_config); + + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; + + sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ + sdram_config.refresh_recover_in_ns = 60; /* Trc */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */ + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.delay_cell_disable = true; + sdram_config.delay_cell_value = 0; + + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); + + HPM_FEMC->SDRCTRL0 |= FEMC_SDRCTRL0_HIGHBAND_MASK; /* use data[31:16] for 16bit SDRAM */ +} +#endif + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ + (void) usb_index; + (void) level; +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + board_config_i2s_clock(DAO_I2S, 48000); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + board_config_i2s_clock(PDM_I2S, 16000); + + return clock_get_frequency(clock_pdm); +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud0, clk_src_pll2_clk0, 21); /* default 24576000Hz */ + } + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 21); /* default 24576000Hz */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc2); + } else if (ptr == (void *)HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ana3); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_MCAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_MCAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_MCAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } else if (ptr == HPM_MCAN4) { + /* Set the CAN4 peripheral clock to 80MHz */ + clock_add_to_group(clock_can4, 0); + clock_set_source_divider(clock_can4, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can4); + } else if (ptr == HPM_MCAN5) { + /* Set the CAN5 peripheral clock to 80MHz */ + clock_add_to_group(clock_can5, 0); + clock_set_source_divider(clock_can5, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can5); + } else if (ptr == HPM_MCAN6) { + /* Set the CAN6 peripheral clock to 80MHz */ + clock_add_to_group(clock_can6, 0); + clock_set_source_divider(clock_can6, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can6); + } else if (ptr == HPM_MCAN7) { + /* Set the CAN7 peripheral clock to 80MHz */ + clock_add_to_group(clock_can7, 0); + clock_set_source_divider(clock_can7, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */ + } else if (ptr == HPM_ENET1) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ + /* clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); */ /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + (void) ptr; + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1, 15); + /* set eth clock frequency at 50MHz for enet0 */ + /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */ + } else { + return status_fail; + } + } + } else { + return status_invalid_argument; + } + + enet_rmii_enable_clock(ptr, internal); /* defined in hpm_enet_soc_drv.h, not sure */ + + return status_success; +} + +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); /* defined in hpm_enet_soc_drv.h, not sure */ + } + + return status_invalid_argument; +} + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} + +void board_init_ethercat(ESC_Type *ptr) +{ + (void)ptr; + init_esc_pins(); + /* keep ECAT PHY reset */ + gpio_set_pin_output_with_initial(BOARD_ECAT_PHY0_RESET_GPIO, BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY0_RESET_PIN_INDEX, BOARD_ECAT_PHY_RESET_LEVEL); + gpio_set_pin_output_with_initial(BOARD_ECAT_PHY1_RESET_GPIO, BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY1_RESET_PIN_INDEX, BOARD_ECAT_PHY_RESET_LEVEL); +} + +/* input and output pin for ethercat io test */ +void board_init_switch_led(void) +{ + init_esc_in_out_pin(); + + gpio_set_pin_input(BOARD_ECAT_IN1_GPIO, BOARD_ECAT_IN1_GPIO_PORT_INDEX, BOARD_ECAT_IN1_GPIO_PIN_INDEX); + gpio_set_pin_input(BOARD_ECAT_IN2_GPIO, BOARD_ECAT_IN2_GPIO_PORT_INDEX, BOARD_ECAT_IN2_GPIO_PIN_INDEX); + + gpio_set_pin_output_with_initial(BOARD_ECAT_OUT1_GPIO, BOARD_ECAT_OUT1_GPIO_PORT_INDEX, BOARD_ECAT_OUT1_GPIO_PIN_INDEX, 0); + gpio_set_pin_output_with_initial(BOARD_ECAT_OUT2_GPIO, BOARD_ECAT_OUT2_GPIO_PORT_INDEX, BOARD_ECAT_OUT2_GPIO_PIN_INDEX, 0); +} + +void board_init_tsw(TSW_Type *ptr) +{ + (void)ptr; + + init_tsw_pins(); + + /* PORT1/PORT2: JL1111 RST(PA10) */ + gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DO_GPIOA, 10, 0); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 10, 0); + board_delay_ms(100); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 10, 1); + + /* PORT3: RTL8211 RST(PA10) */ + gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DO_GPIOA, 14, 0); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, 0); + board_delay_ms(100); + gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, 1); + + /* Enable XI clock for JL1111 */ + esc_core_enable_clock(HPM_ESC, true); + esc_phy_enable_clock(HPM_ESC, true); +} + +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + init_sei_pins(ptr, sei_ctrl_idx); +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr3); + } + else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, 0); + clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr4); + } + else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, 0); + clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr5); + } + else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, 0); + clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr6); + } + else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, 0); + clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk0, 8); + freq = clock_get_frequency(clock_gptmr7); + } + else { + /* Invalid instance */ + } +} + +uint32_t board_init_pwm_clock(PWMV2_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_pwm2, 0); + freq = clock_get_frequency(clock_pwm2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_pwm3, 0); + freq = clock_get_frequency(clock_pwm3); + } else { + + } + return freq; +} diff --git a/bsp/hpmicro/hpm6e00evk/board/board.h b/bsp/hpmicro/hpm6e00evk/board/board.h new file mode 100644 index 0000000000..75e9f2e12a --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/board.h @@ -0,0 +1,714 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include <stdio.h> +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm6e00evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) +#define BOARD_CPU_FREQ (600000000UL) + +#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP0 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP0_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */ + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART1 +#define BOARD_APP_UART_IRQ IRQn_UART1 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart1 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART1_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART1_TX +#endif + +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PF27 + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* enet section */ +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_RMII_RST_GPIO +#define BOARD_ENET_RMII_RST_GPIO_INDEX +#define BOARD_ENET_RMII_RST_GPIO_PIN +#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RMII_PPS0_PINOUT (1) + +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (23U) /* PC23 should align with used pin in pinmux configuration */ + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#else +#define BOARD_CONSOLE_UART_BASE HPM_UART1 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart1 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART1 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART1_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART1_RX +#endif +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 + +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOY +#define BOARD_I2C_SCL_GPIO_PIN 2 +#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOY +#define BOARD_I2C_SDA_GPIO_PIN 3 + +/* i2c for i2s codec section */ +#define BOARD_CODEC_I2C_BASE HPM_I2C1 +#define BOARD_CODEC_I2C_CLK_NAME clock_i2c1 + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (0U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM1 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm1 +#define BOARD_APP_PWM_OUT1 pwm_channel_0 +#define BOARD_APP_PWM_OUT2 pwm_channel_1 +#define BOARD_APP_PWM_OUT3 pwm_channel_2 +#define BOARD_APP_PWM_OUT4 pwm_channel_3 +#define BOARD_APP_PWM_FAULT_PIN (5) +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM1 +#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR4 +#define BOARD_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_GPTMR_PWM HPM_GPTMR4 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR4_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr4 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 0 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_APP_GPIO_PIN 24 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_B + +#define BOARD_APP_GPIO_CTRL2 HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX2 GPIO_DI_GPIOB +#define BOARD_APP_GPIO_PIN2 25 +#define BOARD_APP_GPIO_IRQ2 IRQn_GPIO0_B + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI7 +#define BOARD_APP_SPI_CLK_NAME clock_spi7 +#define BOARD_APP_SPI_IRQ IRQn_SPI7 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI7_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI7_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PF27 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (15U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN4 +#define BOARD_APP_CAN_IRQn IRQn_MCAN4 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* USB section */ +#define BOARD_USB HPM_USB0 + +/* LED */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_R_GPIO_PIN 14 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_G_GPIO_PIN 15 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_B_GPIO_PIN 4 + +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_LED_GPIO_PIN 15 +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL 1 + +#define BOARD_LED_TOGGLE_RGB 1 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT_CH 6 +#define BOARD_RED_PWM_SHADOW_ID 1 +#define BOARD_RED_PWM_CMP_ID 6 +#define BOARD_RED_PWM_COUNTER_INDEX 2 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT_CH 7 +#define BOARD_GREEN_PWM_SHADOW_ID 2 +#define BOARD_GREEN_PWM_CMP_ID 7 +#define BOARD_GREEN_PWM_COUNTER_INDEX 2 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT_CH 4 +#define BOARD_BLUE_PWM_SHADOW_ID 3 +#define BOARD_BLUE_PWM_CMP_ID 4 +#define BOARD_BLUE_PWM_COUNTER_INDEX 1 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* enet section */ +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOA +#define BOARD_ENET_RGMII_RST_GPIO_PIN (14U) + +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (0U) + +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) + +/* TSW section */ +#define BOARD_TSW HPM_TSW + +/* MOTOR */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/*BLDC PWM */ +#define BOARD_BLDCPWM HPM_PWM1 +#define BOARD_BLDC_UH_PWM_OUTPIN (pwm_channel_0) +#define BOARD_BLDC_UL_PWM_OUTPIN (pwm_channel_1) +#define BOARD_BLDC_VH_PWM_OUTPIN (pwm_channel_2) +#define BOARD_BLDC_VL_PWM_OUTPIN (pwm_channel_3) +#define BOARD_BLDC_WH_PWM_OUTPIN (pwm_channel_4) +#define BOARD_BLDC_WL_PWM_OUTPIN (pwm_channel_5) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (16U) + +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC ADC */ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (14U) +#define BOARD_BLDC_ADC_CH_V (10U) +#define BOARD_BLDC_ADC_CH_W (11U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRIG_OUT_CHN (0U) + +/* BLDC TRGM */ +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 +#define BOARD_BLDC_TRIGMUX_OUT_NUM_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_BLDC_TRIGMUX_OUT_NUM_VSC HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 + +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC0 trgm_adc_matrix_output_to_vsc0_adc0 +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC1 trgm_adc_matrix_output_to_vsc0_adc1 +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC2 trgm_adc_matrix_output_to_vsc0_adc2 +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_U trgm_adc_matrix_in_from_adc0 +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_V trgm_adc_matrix_in_from_adc1 +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_W trgm_adc_matrix_in_from_adc2 + +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_ID_ADC trgm_adc_matrix_output_to_clc0_id_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_IQ_ADC trgm_adc_matrix_output_to_clc0_iq_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_ID_ADC trgm_adc_matrix_in_from_vsc0_id_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_IQ_ADC trgm_adc_matrix_in_from_vsc0_iq_adc + +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VD_DAC trgm_dac_matrix_output_to_qeo0_vd_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VQ_DAC trgm_dac_matrix_output_to_qeo0_vq_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VD_DAC trgm_dac_matrix_in_from_clc0_vd_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VQ_DAC trgm_dac_matrix_in_from_clc0_vq_dac + +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC0 trgm_dac_matrix_output_to_pwm1_dac0 +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC1 trgm_dac_matrix_output_to_pwm1_dac1 +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC2 trgm_dac_matrix_output_to_pwm1_dac2 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC0 trgm_dac_matrix_in_from_qeo0_dac0 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC1 trgm_dac_matrix_in_from_qeo0_dac1 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC2 trgm_dac_matrix_in_from_qeo0_dac2 + +#define BOARD_BLDC_TRGM_POS_MATRIX_TO_VSC trgm_pos_matrix_output_to_vsc0 +#define BOARD_BLDC_TRGM_POS_MATRIX_TO_QEO trgm_pos_matrix_output_to_qeo0 +#define BOARD_BLDC_TRGM_POS_MATRIX_FROM_QEI trgm_pos_matrix_in_from_qei0 + +/* BLDC TIMER */ +#define BOARD_BLDC_TMR_BASE HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_PERIOD_MS (1u) + +/* HALL */ + +/* RDC */ +#define BOARD_RDC_BASE HPM_RDC0 +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 +#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 +#define BOARD_RDC_TRG_ADC_NUM HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 +#define BOARD_RDC_ADC_I_CHN (14U) +#define BOARD_RDC_ADC_Q_CHN (10U) +#define BOARD_RDC_ADC_IRQn IRQn_ADC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_rdc0_adc0 +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_rdc0_adc1 +#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_I trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_Q trgm_adc_matrix_in_from_adc1 + +/* QEIV2 */ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI0 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_qei0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +#define BOARD_APP_QEIV2_BASE HPM_QEI3 +#define BOARD_APP_QEIV2_IRQ IRQn_QEI3 +#define BOARD_APP_QEI_CLOCK_SOURCE clock_qei3 +#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC2 +#define BOARD_APP_QEI_ADC_COS_CHN (11U) +#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC0 +#define BOARD_APP_QEI_ADC_SIN_CHN (14U) +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei3_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei3_adc1 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc2 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc0 + +/* PLB */ +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0) +#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32) +#define BOARD_PLB_TYPEB_INPUT0 (TRGM_TRGOCFG_PLB_IN_32) +#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO5) +#define BOARD_PLB_IO_TRG_SHIFT (5) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +/* QEO */ +#define BOARD_QEO HPM_QEO0 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 + +#define BOARD_QEO_PWM HPM_QEO1 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */ +#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo1 + +/* SEI */ +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI_1 +#define BOARD_TRGM_POS_SOURCE_SEI trgm_pos_matrix_in_from_sei_pos1 + +/* MTG */ +#define BOARD_TRGM_POS_DEST_MTG trgm_pos_matrix_output_to_mtg0 + +/* VSC */ +#define BOARD_VSC HPM_VSC0 +#define BOARD_VSC_IRQn IRQn_VSC0 + +/* CLC */ +#define BOARD_CLC HPM_CLC0 +#define BOARD_CLC_IRQn IRQn_CLC0_0 + +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 4 +#define BOARD_TAMP_LOW_LEVEL_CH 3 + +/* sdm section */ +#define BOARD_SDM HPM_SDM0 +#define BOARD_SDM_IRQ IRQn_SDM0 +#define BOARD_SDM_CHANNEL 0 +#define BOARD_SDM_TRGM HPM_TRGM0 +#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CH 2 +#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 +#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15 +#define BOARD_SDM_TRGM_SYNC_SRC (15) +/* need to provide clock to sdm sensor */ +#define BOARD_SDM_SENSOR_REQUIRE_CLK true +#define BOARD_SDM_CLK_PWM HPM_PWM2 +#define BOARD_SDM_CLK_PWM_CLK_NAME clock_pwm2 +#define BOARD_SDM_CLK_PWM_OUT (3) + + + +/* EtherCAT definitions */ +/* ECAT PORT0 must support */ +#define BOARD_ECAT_SUPPORT_PORT1 (1) +#define BOARD_ECAT_SUPPORT_PORT2 (0) + +#define BOARD_ECAT_PHY0_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA +#define BOARD_ECAT_PHY0_RESET_PIN_INDEX (10) + +#define BOARD_ECAT_PHY1_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA +#define BOARD_ECAT_PHY1_RESET_PIN_INDEX (10) +#define BOARD_ECAT_PHY_RESET_LEVEL (0) + +#define BOARD_ECAT_IN1_GPIO HPM_GPIO0 +#define BOARD_ECAT_IN1_GPIO_PORT_INDEX GPIO_DO_GPIOC +#define BOARD_ECAT_IN1_GPIO_PIN_INDEX (31U) + +#define BOARD_ECAT_IN2_GPIO HPM_GPIO0 +#define BOARD_ECAT_IN2_GPIO_PORT_INDEX GPIO_DO_GPIOD +#define BOARD_ECAT_IN2_GPIO_PIN_INDEX (9U) + +#define BOARD_ECAT_OUT1_GPIO HPM_GPIO0 +#define BOARD_ECAT_OUT1_GPIO_PORT_INDEX GPIO_DO_GPIOD +#define BOARD_ECAT_OUT1_GPIO_PIN_INDEX (8U) + +#define BOARD_ECAT_OUT2_GPIO BOARD_R_GPIO_CTRL /* reuse RGB red led */ +#define BOARD_ECAT_OUT2_GPIO_PORT_INDEX BOARD_R_GPIO_INDEX +#define BOARD_ECAT_OUT2_GPIO_PIN_INDEX BOARD_R_GPIO_PIN + +#define BOARD_ECAT_OUT_ON_LEVEL (1) /* ECAT control LED on level */ + +#define BOARD_ECAT_NMII_LINK0_CTRL_INDEX 3 +#define BOARD_ECAT_NMII_LINK1_CTRL_INDEX 0 +#define BOARD_ECAT_LED_RUN_CTRL_INDEX 1 +#define BOARD_ECAT_LED_ERROR_CTRL_INDEX 6 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR6 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR6 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* LOBS */ +#define BOARD_LOBS_TRIG_GROUP 5 /* group5 <--> PF */ +#define BOARD_LOBS_TRIG_PIN 26 + +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_I2S_SPI_CS_GPIO_PIN 6 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA06 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 2 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR4 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 0 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr4 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 0 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_core1(void); +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_can(MCAN_Type *ptr); +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +uint8_t board_get_led_gpio_off_level(void); +void board_init_led_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); +uint32_t board_init_femc_clock(void); +uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb); +void board_init_i2s_pins(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); +void board_init_dao_pins(void); +void board_init_adc16_pins(void); +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); +void board_init_ethercat(ESC_Type *ptr); +void board_init_switch_led(void); +void board_init_tsw(TSW_Type *ptr); +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void board_init_adc_qeiv2_pins(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +uint32_t board_init_pwm_clock(PWMV2_Type *ptr); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg new file mode 100644 index 0000000000..3147f1b559 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/boards/hpm6e00evk.cfg @@ -0,0 +1,80 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..b9ae112104 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg new file mode 100644 index 0000000000..3776573604 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-dual-core.cfg @@ -0,0 +1,63 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# + + +set _CHIP hpm6e00 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr { 0x100000 | [dmi_read 0x38] }] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} + +proc release_core1 {} { + dmi_write_memory 0xF4002C00 0x1000 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event examine-start { + release_core1 +} + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET0 arp_poll + release_core1 +} + +$_TARGET0 configure -event reset-end { + $::_TARGET0 riscv dmi_write 0x39 0xF4002010 + $::_TARGET0 riscv dmi_write 0x3C 0x2 +} + +proc reset_soc {} { + $::_TARGET0 riscv dmi_write 0x39 0xF410001C + $::_TARGET0 riscv dmi_write 0x3C 24000000 +} diff --git a/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg new file mode 100644 index 0000000000..b80ad2027b --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/debug_scripts/openocd/soc/hpm6e80-single-core.cfg @@ -0,0 +1,18 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6e00 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +proc reset_soc {} { + $::_TARGET0 riscv dmi_write 0x39 0xF410001C + $::_TARGET0 riscv dmi_write 0x3C 24000000 +} diff --git a/bsp/hpmicro/hpm6e00evk/board/fal_cfg.h b/bsp/hpmicro/hpm6e00evk/board/fal_cfg.h new file mode 100644 index 0000000000..3533c1fbb2 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/fal_cfg.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include <rtconfig.h> +#include <board.h> + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#ifdef CONFIG_WEBNET_FAL_FS +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \ +} +#else +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ +} +#endif +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c new file mode 100644 index 0000000000..6960ab7f67 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include <rtthread.h> +#include <rthw.h> +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.c b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.c new file mode 100644 index 0000000000..bbb1b25beb --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <stdio.h> +#include "hpm_wm8960.h" + +#ifndef HPM_WM8960_MCLK_TOLERANCE +#define HPM_WM8960_MCLK_TOLERANCE (4U) +#endif + +/* wm8960 register default value */ +static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* store reg value */ +static uint16_t wm8960_reg_val[WM8960_REG_NUM]; + +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) +{ + assert(control != NULL); + assert(config != NULL); + + hpm_stat_t stat = status_success; + + (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); + + /* Reset */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); + + /* Power on input modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); + /* Power on output modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); + /* Power on PGA and mixer */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + + /* ADC and DAC uses same clock */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); + + /* set data protocol */ + HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); + + /* set wm8960 as slave */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + + /* invert LRCLK */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); + + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); + + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); + + /* Digital DAC volume, 0dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); + + /* Headphone volume, LOUT1 and ROUT1, 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); + + /* speaker volume 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); + /* enable class D output */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); + + /* Unmute DAC. */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + + HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); + + /* set data route */ + HPM_CHECK_RET(wm8960_set_data_route(control, config)); + + return status_success; +} + +hpm_stat_t wm8960_deinit(wm8960_control_t *control) +{ + hpm_stat_t stat = status_success; + + /* power off all modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); + + return status_success; +} + +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) +{ + return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); +} + +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) +{ + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); + break; + case wm8960_module_dac: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); + break; + case wm8960_module_vref: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); + break; + case wm8960_module_ana_in: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); + break; + case wm8960_module_lineout: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); + break; + case wm8960_module_micbais: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, + ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); + break; + case wm8960_module_speaker: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); + break; + case wm8960_module_output_mixer: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) +{ + hpm_stat_t stat = status_success; + + /* select left input */ + HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); + /* select right input */ + HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); + /* select source to output mixer */ + HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); + + switch (config->route) { + case wm8960_route_bypass: + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback: + /* I2S_IN-> DAC-> HP */ + /* Set power for DAC */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback_and_record: + /* Set power */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_record: + /* ANA_IN->ADC->I2S_OUT */ + /* Power up ADC and AIN */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + /* Update volume */ + vol = (uint16_t)(0x100U | volume); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + } + break; + case wm8960_module_dac: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + } + break; + case wm8960_module_headphone: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + } + break; + case wm8960_module_ana_in: + if (volume > 0x3FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + } + break; + case wm8960_module_speaker: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + } + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; + + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } + + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } + } + + if (!clock_meet_requirement) { + return status_invalid_argument; + } + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + + /* set sample bit */ + switch (bits) { + case 16: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); + break; + case 20: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); + break; + case 24: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); + break; + case 32: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) +{ + hpm_stat_t stat = status_success; + + if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); + } + + return stat; +} + + +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) +{ + /* The first 7 bits (B15 to B9) are address bits that select which control register */ + /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ + rt_size_t size; + rt_uint8_t data[2]; + data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + data[1] = (uint8_t)(val & 0xFFU); + + size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); + if (size != 2) { + return status_fail; + } + + wm8960_reg_val[reg] = val; + return status_success; +} + +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_REG_NUM) { + return status_invalid_argument; + } + *val = wm8960_reg_val[reg]; + + return status_success; +} + +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) +{ + hpm_stat_t stat = 0; + uint16_t reg_val; + + /* Read the register value out */ + stat = wm8960_read_reg(reg, ®_val); + if (stat != status_success) { + return status_fail; + } + + /* Modify the value */ + reg_val &= (uint16_t)~mask; + reg_val |= val; + + /* Write the data to register */ + stat = wm8960_write_reg(control, reg, reg_val); + if (stat != status_success) { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h new file mode 100644 index 0000000000..a288b08db9 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_H_ +#define _HPM_WM8960_H_ + +//#include "hpm_i2c_drv.h" +//#include "hpm_common.h" +#include <rtthread.h> +#include <rtdevice.h> +#include "rtt_board.h" +#include "drivers/i2c.h" +#include "hpm_wm8960_regs.h" + +#define WM8960_I2C_ADDR 0x1A + +typedef enum wm8960_module { + wm8960_module_adc = 0, /* ADC module in WM8960 */ + wm8960_module_dac = 1, /* DAC module in WM8960 */ + wm8960_module_vref = 2, /* VREF module */ + wm8960_module_headphone = 3, /* Headphone */ + wm8960_module_micbais = 4, /* Mic bias */ + wm8960_module_ana_in = 6, /* Analog in PGA */ + wm8960_module_lineout = 7, /* Line out module */ + wm8960_module_speaker = 8, /* Speaker module */ + wm8960_module_output_mixer = 9, /* Output mixer */ +} wm8960_module_t; + +/* wm8960 play source for output mixer */ +typedef enum wm8960_play_source { + wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ + wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ + wm8960_play_source_dac = 4, /* DAC to Output Mixer */ +} wm8960_play_source_t; + +/* WM8960 data route */ +typedef enum wm8960_route { + wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ + wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ + wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ + wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ +} wm8960_route_t; + +/* The audio data transfer protocol choice */ +typedef enum wm8960_protocol { + wm8960_bus_i2s = 2, /* I2S type */ + wm8960_bus_left_justified = 1, /* Left justified mode */ + wm8960_bus_right_justified = 0, /* Right justified mode */ + wm8960_bus_pcma = 3, /* PCM A mode */ + wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ +} wm8960_protocol_t; + +/* wm8960 input source */ +typedef enum wm8960_input { + wm8960_input_closed = 0, /* Input device is closed */ + wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ + wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ + wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ + wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ + wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ +} wm8960_input_t; + +/* wm8960 audio format */ +typedef struct wm8960_audio_format { + uint32_t mclk_hz; /* master clock frequency */ + uint32_t sample_rate; /* sample rate */ + uint32_t bit_width; /* bit width */ +} wm8960_audio_format_t; + +/* configure structure of WM8960 */ +typedef struct wm8960_config { + wm8960_route_t route; /* Audio data route.*/ + wm8960_protocol_t bus; /* Audio transfer protocol */ + bool enable_speaker; /* True means enable class D speaker as output, false means no */ + wm8960_input_t left_input; /* Left input source for WM8960 */ + wm8960_input_t right_input; /* Right input source for wm8960 */ + wm8960_play_source_t play_source; /* play source */ + wm8960_audio_format_t format; /* Audio format */ +} wm8960_config_t; + +typedef struct { + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ + uint8_t slave_address; /* code device address */ +} wm8960_control_t; + + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief WM8960 initialize function. + * + * @param control WM8960 control structure. + * @param config WM8960 configuration structure. + */ +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param control WM8960 control structure pointer. + */ +hpm_stat_t wm8960_deinit(wm8960_control_t *control); + +/** + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. + * + * @param control WM8960 control structure. + * @param config Audio configure structure in WM8960. + */ +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Set left audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set right audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set the audio transfer protocol. + * + * @param control WM8960 control structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); + +/** + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db + * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db + * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db + * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * + * + * @param control WM8960 control structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); + +/** + * @brief Enable/disable expected module. + * + * @param control WM8960 control structure. + * @param module Module expected to enable. + * @param enable Enable or disable moudles. + */ +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); + +/** + * @brief SET the WM8960 play source. + * + * @param control WM8960 control structure. + * @param play_source play source + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); + +/** + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param control WM8960 control structure pointer. + * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); + + +/** + * @brief Write register to WM8960 using I2C. + * + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); + +/** + * @brief Read register from WM8960 using I2C. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); + +/** + * @brief Modify some bits in the register using I2C. + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); + + +#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960_regs.h b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960_regs.h new file mode 100644 index 0000000000..a484f2937c --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960_regs.h @@ -0,0 +1,2139 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_REG_H_ +#define _HPM_WM8960_REG_H_ + +/* WM8960 register number */ +#define WM8960_REG_NUM 56U + +/* Define the register address of WM8960 */ +#define WM8960_LINVOL 0x0U /* Left Input Volume */ +#define WM8960_RINVOL 0x1U /* Right Input Volume */ +#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ +#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ +#define WM8960_CLOCK1 0x4U /* Clocking(1) */ +#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ +#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ +#define WM8960_IFACE1 0x7U /* Audio Interface */ +#define WM8960_CLOCK2 0x8U /* Clocking(2) */ +#define WM8960_IFACE2 0x9U /* Audio Interface */ +#define WM8960_LDAC 0xaU /* Left DAC */ +#define WM8960_RDAC 0xbU /* Right DAC Volume */ +#define WM8960_RESET 0xfU /* RESET */ +#define WM8960_3D 0x10U /* 3D Control */ +#define WM8960_ALC1 0x11U /* ALC (1) */ +#define WM8960_ALC2 0x12U /* ALC (2) */ +#define WM8960_ALC3 0x13U /* ALC (3) */ +#define WM8960_NOISEG 0x14U /* Noise Gate */ +#define WM8960_LADC 0x15U /* Left ADC Volume */ +#define WM8960_RADC 0x16U /* Right ADC Volume */ +#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ +#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ +#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ +#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ +#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ +#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ +#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ +#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ +#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ +#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ +#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ +#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ +#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ +#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ +#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ +#define WM8960_MONO 0x2aU /* OUT3 Volume */ +#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ +#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ +#define WM8960_BYPASS1 0x2dU /* Left Bypass */ +#define WM8960_BYPASS2 0x2eU /* Right Bypass */ +#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ +#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ +#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ +#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ +#define WM8960_PLL1 0x34U /* PLL (1) */ +#define WM8960_PLL2 0x35U /* PLL (2) */ +#define WM8960_PLL3 0x36U /* PLL (3) */ +#define WM8960_PLL4 0x37U /* PLL (4) */ + +/* Bitfield definition for register: LINVO */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_LINVO_IPVU_MASK (0x100U) +#define WM8960_LINVO_IPVU_SHIFT (8U) +#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) +#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) + +/* + * LINMUTE (RW) + * + * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. + */ +#define WM8960_LINVO_LINMUTE_MASK (0x80U) +#define WM8960_LINVO_LINMUTE_SHIFT (7U) +#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) +#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) + +/* + * LIZC (RW) + * + * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately + */ +#define WM8960_LINVO_LIZC_MASK (0x40U) +#define WM8960_LINVO_LIZC_SHIFT (6U) +#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) +#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) + +/* + * LINVOL (RW) + * + * Left Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_LINVO_LINVOL_MASK (0x3FU) +#define WM8960_LINVO_LINVOL_SHIFT (0U) +#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) +#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) + +/* Bitfield definition for register: RINVOL */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right + * input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_RINVOL_IPVU_MASK (0x100U) +#define WM8960_RINVOL_IPVU_SHIFT (8U) +#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) +#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) + +/* + * RINMUTE (RW) + * + * Right Input PGA Analogue Mute + * 1 = Enable Mute + * 0 = Disable Mute + * Note: IPVU must be set to un-mute. + */ +#define WM8960_RINVOL_RINMUTE_MASK (0x80U) +#define WM8960_RINVOL_RINMUTE_SHIFT (7U) +#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) +#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) + +/* + * RIZC (RW) + * + * Right Input PGA Zero Cross Detector + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_RINVOL_RIZC_MASK (0x40U) +#define WM8960_RINVOL_RIZC_SHIFT (6U) +#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) +#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) + +/* + * RINVOL (RW) + * + * Right Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_RINVOL_RINVOL_MASK (0x3FU) +#define WM8960_RINVOL_RINVOL_SHIFT (0U) +#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) +#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) + +/* Bitfield definition for register: LOUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_LOUT1_OUT1VU_MASK (0x100U) +#define WM8960_LOUT1_OUT1VU_SHIFT (8U) +#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) +#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) + +/* + * LO1ZC (RW) + * + * Left Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_LOUT1_LO1ZC_MASK (0x80U) +#define WM8960_LOUT1_LO1ZC_SHIFT (7U) +#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) +#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) + +/* + * LOUT1VOL (RW) + * + * LOUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) +#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) +#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) +#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) + +/* Bitfield definition for register: ROUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_ROUT1_OUT1VU_MASK (0x100U) +#define WM8960_ROUT1_OUT1VU_SHIFT (8U) +#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) +#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) + +/* + * RO1ZC (RW) + * + * Right Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_ROUT1_RO1ZC_MASK (0x80U) +#define WM8960_ROUT1_RO1ZC_SHIFT (7U) +#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) +#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) + +/* + * ROUT1VOL (RW) + * + * ROUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) +#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) +#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) +#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) + +/* Bitfield definition for register: CLOCK1 */ +/* + * ADCDIV (RW) + * + * ADC Sample rate divider (Also determines + * ADCLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) +#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) +#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) +#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) + +/* + * DACDIV (RW) + * + * DAC Sample rate divider (Also determines + * DACLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_DACDIV_MASK (0x38U) +#define WM8960_CLOCK1_DACDIV_SHIFT (3U) +#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) +#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) + +/* + * SYSCLKDIV (RW) + * + * SYSCLK Pre-divider. Clock source (MCLK or + * PLL output) will be divided by this value to + * generate SYSCLK. + * 00 = Divide SYSCLK by 1 + * 01 = Reserved + * 10 = Divide SYSCLK by 2 + * 11 = Reserved + */ +#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) +#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) +#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) +#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) + +/* + * CLKSEL (RW) + * + * SYSCLK Selection + * 0 = SYSCLK derived from MCLK + * 1 = SYSCLK derived from PLL output + */ +#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) +#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) +#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) +#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) + +/* Bitfield definition for register: DACCTL1 */ +/* + * DACDIV2 (RW) + * + * DAC 6dB Attenuate Enable + * 0 = Disabled (0dB) + * 1 = -6dB Enabled + */ +#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) +#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) +#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) +#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) + +/* + * ADCPOL (RW) + * + * ADC polarity control: + * 00 = Polarity not inverted + * 01 = ADC L inverted + * 10 = ADC R inverted + * 11 = ADC L and R inverted + */ +#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) +#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) +#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) +#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) + +/* + * DACMU (RW) + * + * DAC Digital Soft Mute + * 1 = Mute + * 0 = No mute (signal active) + */ +#define WM8960_DACCTL1_DACMU_MASK (0x8U) +#define WM8960_DACCTL1_DACMU_SHIFT (3U) +#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) +#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) + +/* + * DEEMPH (RW) + * + * De-emphasis Control + * 11 = 48kHz sample rate + * 10 = 44.1kHz sample rate + * 01 = 32kHz sample rate + * 00 = No de-emphasis + */ +#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) +#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) +#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) +#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) + +/* + * ADCHPD (RW) + * + * ADC High Pass Filter Disable + * 0 = Enable high pass filter on left and right channels + * 1 = Disable high pass filter on left and right channels + */ +#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) +#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) +#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) +#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) + +/* Bitfield definition for register: DACCTL2 */ +/* + * DACPOL (RW) + * + * DAC polarity control: + * 00 = Polarity not inverted + * 01 = DAC L inverted + * 10 = DAC R inverted + * 11 = DAC L and R inverted + */ +#define WM8960_DACCTL2_DACPOL_MASK (0x60U) +#define WM8960_DACCTL2_DACPOL_SHIFT (5U) +#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) +#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) + +/* + * DACSMM (RW) + * + * DAC Soft Mute Mode + * 0 = Disabling soft-mute (DACMU=0) will cause + * the volume to change immediately to the + * LDACVOL / RDACVOL settings + * 1 = Disabling soft-mute (DACMU=0) will cause + * the volume to ramp up gradually to the + * LDACVOL / RDACVOL settings + */ +#define WM8960_DACCTL2_DACSMM_MASK (0x8U) +#define WM8960_DACCTL2_DACSMM_SHIFT (3U) +#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) +#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) + +/* + * DACMR (RW) + * + * DAC Soft Mute Ramp Rate + * 0 = Fast ramp (24kHz at fs=48k, providing + * maximum delay of 10.7ms) + * 1 = Slow ramp (1.5kHz at fs=48k, providing + * maximum delay of 171ms) + */ +#define WM8960_DACCTL2_DACMR_MASK (0x4U) +#define WM8960_DACCTL2_DACMR_SHIFT (2U) +#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) +#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) + +/* + * DACSLOPE (RW) + * + * Selects DAC filter characteristics + * 0 = Normal mode + * 1 = Sloping stopband + */ +#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) +#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) +#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) +#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) + +/* Bitfield definition for register: IFACE1 */ +/* + * ALRSWAP (RW) + * + * Left/Right ADC Channel Swap + * 1 = Swap left and right ADC data in audio + * interface + * 0 = Output left and right data as normal + */ +#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) +#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) +#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) +#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) + +/* + * BCLKINV (RW) + * + * BCLK invert bit (for master and slave modes) + * 0 = BCLK not inverted + * 1 = BCLK inverted + */ +#define WM8960_IFACE1_BCLKINV_MASK (0x80U) +#define WM8960_IFACE1_BCLKINV_SHIFT (7U) +#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) +#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) + +/* + * MS (RW) + * + * Master / Slave Mode Control + * 0 = Enable slave mode + * 1 = Enable master mode + */ +#define WM8960_IFACE1_MS_MASK (0x40U) +#define WM8960_IFACE1_MS_SHIFT (6U) +#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) +#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) + +/* + * DLRSWAP (RW) + * + * Left/Right DAC Channel Swap + * 0 = Output left and right data as normal + * 1 = Swap left and right DAC data in audio interface + */ +#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) +#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) +#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) +#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) + +/* + * LRP (RW) + * + * Right, left and I2S modes – LRCLK polarity + * 0 = normal LRCLK polarity + * 1 = invert LRCLK polarity + * DSP Mode – mode A/B select + * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) + * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) + */ +#define WM8960_IFACE1_LRP_MASK (0x10U) +#define WM8960_IFACE1_LRP_SHIFT (4U) +#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) +#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) + +/* + * WL (RW) + * + * Audio Data Word Length + * 00 = 16 bits + * 01 = 20 bits + * 10 = 24 bits + * 11 = 32 bits (see Note) + */ +#define WM8960_IFACE1_WL_MASK (0xCU) +#define WM8960_IFACE1_WL_SHIFT (2U) +#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) +#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) + +/* + * FORMAT (RW) + * + * 00 = Right justified + * 01 = Left justified + * 10 = I2S Format + * 11 = DSP Mode + */ +#define WM8960_IFACE1_FORMAT_MASK (0x3U) +#define WM8960_IFACE1_FORMAT_SHIFT (0U) +#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) +#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) + +/* Bitfield definition for register: CLOCK2 */ +/* + * DCLKDIV (RW) + * + * Class D switching clock divider. + * 000 = SYSCLK / 1.5 (Not recommended) + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 6 + * 101 = SYSCLK / 8 + * 110 = SYSCLK / 12 + * 111 = SYSCLK / 16 + */ +#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) +#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) +#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) +#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) + +/* + * BCLKDIV (RW) + * + * BCLK Frequency (Master Mode) + * 0000 = SYSCLK + * 0001 = SYSCLK / 1.5 + * 0010 = SYSCLK / 2 + * 0011 = SYSCLK / 3 + * 0100 = SYSCLK / 4 + * 0101 = SYSCLK / 5.5 + * 0110 = SYSCLK / 6 + * 0111 = SYSCLK / 8 + * 1000 = SYSCLK / 11 + * 1001 = SYSCLK / 12 + * 1010 = SYSCLK / 16 + * 1011 = SYSCLK / 22 + * 1100 = SYSCLK / 24 + * 1101 to 1111 = SYSCLK / 32 + */ +#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) +#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) +#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) +#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) + +/* Bitfield definition for register: IFACE2 */ +/* + * ALRCGPIO (RW) + * + * ADCLRC/GPIO1 Pin Function Select + * 0 = ADCLRC frame clock for ADC + * 1 = GPIO pin + */ +#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) +#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) +#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) +#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) + +/* + * WL8 (RW) + * + * 8-Bit Word Length Select (Used with + * companding) + * 0 = Off + * 1 = Device operates in 8-bit mode. + */ +#define WM8960_IFACE2_WL8_MASK (0x20U) +#define WM8960_IFACE2_WL8_SHIFT (5U) +#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) +#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) + +/* + * DACCOMP (RW) + * + * DAC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_DACCOMP_MASK (0x18U) +#define WM8960_IFACE2_DACCOMP_SHIFT (3U) +#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) +#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) + +/* + * ADCCOMP (RW) + * + * ADC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) +#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) +#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) +#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) + +/* + * LOOPBACK (RW) + * + * Digital Loopback Function + * 0 = No loopback. + * 1 = Loopback enabled, ADC data output is fed + * directly into DAC data input + */ +#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) +#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) +#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) +#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) + +/* Bitfield definition for register: LDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_LDAC_DACVU_MASK (0x100U) +#define WM8960_LDAC_DACVU_SHIFT (8U) +#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) +#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) + +/* + * LDACVOL (RW) + * + * Left DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_LDAC_LDACVOL_MASK (0xFFU) +#define WM8960_LDAC_LDACVOL_SHIFT (0U) +#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) +#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) + +/* Bitfield definition for register: RDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_RDAC_DACVU_MASK (0x100U) +#define WM8960_RDAC_DACVU_SHIFT (8U) +#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) +#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) + +/* + * RDACVOL (RW) + * + * Right DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_RDAC_RDACVOL_MASK (0xFFU) +#define WM8960_RDAC_RDACVOL_SHIFT (0U) +#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) +#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) + +/* Bitfield definition for register: RESET */ +/* + * RESET (RW) + * + * Writing to this register resets all registers to their default state. + */ +#define WM8960_RESET_RESET_MASK (0x1FFU) +#define WM8960_RESET_RESET_SHIFT (0U) +#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) +#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) + +/* Bitfield definition for register: 3D */ +/* + * 3DUC (RW) + * + * 3D Enhance Filter Upper Cut-Off Frequency + * 0 = High (Recommended for fs>=32kHz) + * 1 = Low (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DUC_MASK (0x40U) +#define WM8960_3D_3DUC_SHIFT (6U) +#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) +#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) + +/* + * 3DLC (RW) + * + * 3D Enhance Filter Lower Cut-Off Frequency + * 0 = Low (Recommended for fs>=32kHz) + * 1 = High (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DLC_MASK (0x20U) +#define WM8960_3D_3DLC_SHIFT (5U) +#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) +#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) + +/* + * 3DDEPTH (RW) + * + * 3D Stereo Depth + * 0000 = 0% (minimum 3D effect) + * 0001 = 6.67% + * .... + * 1110 = 93.3% + * 1111 = 100% (maximum 3D effect) + */ +#define WM8960_3D_3DDEPTH_MASK (0x1EU) +#define WM8960_3D_3DDEPTH_SHIFT (1U) +#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) +#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) + +/* + * 3DEN (RW) + * + * 3D Stereo Enhancement Enable + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_3D_3DEN_MASK (0x1U) +#define WM8960_3D_3DEN_SHIFT (0U) +#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) +#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) + +/* Bitfield definition for register: ALC1 */ +/* + * ALCSEL (RW) + * + * ALC Function Select + * 00 = ALC off (PGA gain set by register) + * 01 = Right channel only + * 10 = Left channel only + * 11 = Stereo (PGA registers unused) Note: + * ensure that LINVOL and RINVOL settings + * (reg. 0 and 1) are the same before entering this mode. + */ +#define WM8960_ALC1_ALCSEL_MASK (0x180U) +#define WM8960_ALC1_ALCSEL_SHIFT (7U) +#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) +#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) + +/* + * MAXGAIN (RW) + * + * Set Maximum Gain of PGA (During ALC + * operation) + * 111 : +30dB + * 110 : +24dB + * ….(-6dB steps) + * 001 : -6dB + * 000 : -12dB + */ +#define WM8960_ALC1_MAXGAIN_MASK (0x70U) +#define WM8960_ALC1_MAXGAIN_SHIFT (4U) +#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) +#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) + +/* + * ALCL (RW) + * + * ALC Target (Sets signal level at ADC input) + * 0000 = -22.5dB FS + * 0001 = -21.0dB FS + * … (1.5dB steps) + * 1101 = -3.0dB FS + * 1110 = -1.5dB FS + * 1111 = -1.5dB FS + */ +#define WM8960_ALC1_ALCL_MASK (0xFU) +#define WM8960_ALC1_ALCL_SHIFT (0U) +#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) +#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) + +/* Bitfield definition for register: ALC2 */ +/* + * MINGAIN (RW) + * + * Set Minimum Gain of PGA (During ALC + * operation) + * 000 = -17.25dB + * 001 = -11.25dB + * 010 = -5.25dB + * 011 = +0.75dB + * 100 = +6.75dB + * 101 = +12.75dB + * 110 = +18.75dB + * 111 = +24.75dB + */ +#define WM8960_ALC2_MINGAIN_MASK (0x70U) +#define WM8960_ALC2_MINGAIN_SHIFT (4U) +#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) +#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) + +/* + * HLD (RW) + * + * ALC hold time before gain is increased. + * 0000 = 0ms + * 0001 = 2.67ms + * 0010 = 5.33ms + * … (time doubles with every step) + * 1111 = 43.691s + */ +#define WM8960_ALC2_HLD_MASK (0xFU) +#define WM8960_ALC2_HLD_SHIFT (0U) +#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) +#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) + +/* Bitfield definition for register: ALC3 */ +/* + * ALCMODE (RW) + * + * Determines the ALC mode of operation: + * 0 = ALC mode + * 1 = Limiter mode + */ +#define WM8960_ALC3_ALCMODE_MASK (0x100U) +#define WM8960_ALC3_ALCMODE_SHIFT (8U) +#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) +#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) + +/* + * DCY (RW) + * + * ALC decay (gain ramp-up) time + * 0000 = 24ms + * 0001 = 48ms + * 0010 = 96ms + * … (time doubles with every step) + * 1010 or higher = 24.58s + */ +#define WM8960_ALC3_DCY_MASK (0xF0U) +#define WM8960_ALC3_DCY_SHIFT (4U) +#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) +#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) + +/* + * ATK (RW) + * + * ALC attack (gain ramp-down) time + * 0000 = 6ms + * 0001 = 12ms + * 0010 = 24ms + * … (time doubles with every step) + * 1010 or higher = 6.14s + */ +#define WM8960_ALC3_ATK_MASK (0xFU) +#define WM8960_ALC3_ATK_SHIFT (0U) +#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) +#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) + +/* Bitfield definition for register: NOISEG */ +/* + * NGTH (RW) + * + * Noise gate threshold + * 00000 -76.5dBfs + * 00001 -75dBfs + * … 1.5 dB steps + * 11110 -31.5dBfs + * 11111 -30dBfs + */ +#define WM8960_NOISEG_NGTH_MASK (0xF8U) +#define WM8960_NOISEG_NGTH_SHIFT (3U) +#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) +#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) + +/* + * NGAT (RW) + * + * Noise gate function enable + * 0 = disable + * 1 = enable + */ +#define WM8960_NOISEG_NGAT_MASK (0x1U) +#define WM8960_NOISEG_NGAT_SHIFT (0U) +#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) +#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) + +/* Bitfield definition for register: LADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and + * RADCVOL) + */ +#define WM8960_LADC_ADCVU_MASK (0x100U) +#define WM8960_LADC_ADCVU_SHIFT (8U) +#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) +#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) + +/* + * LADCVOL (RW) + * + * Left ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_LADC_LADCVOL_MASK (0xFFU) +#define WM8960_LADC_LADCVOL_SHIFT (0U) +#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) +#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) + +/* Bitfield definition for register: RADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and RADCVOL) + */ +#define WM8960_RADC_ADCVU_MASK (0x100U) +#define WM8960_RADC_ADCVU_SHIFT (8U) +#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) +#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) + +/* + * RADCVOL (RW) + * + * Right ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_RADC_RADCVOL_MASK (0xFFU) +#define WM8960_RADC_RADCVOL_SHIFT (0U) +#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) +#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) + +/* Bitfield definition for register: ADDCTL1 */ +/* + * TSDEN (RW) + * + * Thermal Shutdown Enable + * 0 = Thermal shutdown disabled + * 1 = Thermal shutdown enabled + * (TSENSEN must be enabled for this function to work) + */ +#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) +#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) +#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) +#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) + +/* + * VSEL (RW) + * + * Analogue Bias Optimisation + * 00 = Reserved + * 01 = Increased bias current optimized for + * AVDD=2.7V + * 1X = Lowest bias current, optimized for + * AVDD=3.3V + */ +#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) +#define WM8960_ADDCTL1_VSEL_SHIFT (6U) +#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) +#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) + +/* + * DMONOMIX (RW) + * + * DAC Mono Mix + * 0 = Stereo + * 1 = Mono (Mono MIX output on enabled DACs + */ +#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) +#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) +#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) +#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) + +/* + * DATSEL (RW) + * + * ADC Data Output Select + * 00: left data = left ADC; right data =right ADC + * 01: left data = left ADC; right data = left ADC + * 10: left data = right ADC; right data =right ADC + * 11: left data = right ADC; right data = left ADC + */ +#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) +#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) +#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) +#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) + +/* + * TOCLKSEL (RW) + * + * Slow Clock Select (Used for volume update + * timeouts and for jack detect debounce) + * 0 = SYSCLK / 221 (Slower Response) + * 1 = SYSCLK / 219 (Faster Response) + */ +#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) +#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) +#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) +#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) + +/* + * TOEN (RW) + * + * Enables Slow Clock for Volume Update Timeout + * and Jack Detect Debounce + * 0 = Slow clock disabled + * 1 = Slow clock enabled + */ +#define WM8960_ADDCTL1_TOEN_MASK (0x1U) +#define WM8960_ADDCTL1_TOEN_SHIFT (0U) +#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) +#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) + +/* Bitfield definition for register: ADDCTL2 */ +/* + * HPSWEN (RW) + * + * Headphone Switch Enable + * 0 = Headphone switch disabled + * 1 = Headphone switch enabled + */ +#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) +#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) +#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) +#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) + +/* + * HPSWPOL (RW) + * + * Headphone Switch Polarity + * 0 = HPDETECT high = headphone + * 1 = HPDETECT high = speaker + */ +#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) +#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) +#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) +#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) + +/* + * TRIS (RW) + * + * Tristates ADCDAT and switches ADCLRC, + * DACLRC and BCLK to inputs. + * 0 = ADCDAT is an output; ADCLRC, DACLRC + * and BCLK are inputs (slave mode) or outputs + * (master mode) + * 1 = ADCDAT is tristated; DACLRC and BCLK + * are inputs; ADCLRC is an input (when not + * configured as a GPIO) + */ +#define WM8960_ADDCTL2_TRIS_MASK (0x8U) +#define WM8960_ADDCTL2_TRIS_SHIFT (3U) +#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) +#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) + +/* + * LRCM (RW) + * + * Selects disable mode for ADCLRC and DACLRC + * (Master mode) + * 0 = ADCLRC disabled when ADC (Left and + * Right) disabled; DACLRC disabled when + * DAC (Left and Right) disabled. + * 1 = ADCLRC and DACLRC disabled only when + * ADC (Left and Right) and DAC (Left and Right) + * are disabled. + */ +#define WM8960_ADDCTL2_LRCM_MASK (0x4U) +#define WM8960_ADDCTL2_LRCM_SHIFT (2U) +#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) +#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) + +/* Bitfield definition for register: POWER1 */ +/* + * VMIDSEL (RW) + * + * Vmid Divider Enable and Select + * 00 = Vmid disabled (for OFF mode) + * 01 = 2 x 50k divider enabled (for playback / + * record) + * 10 = 2 x 250k divider enabled (for low-power + * standby) + * 11 = 2 x 5k divider enabled (for fast start-up) + */ +#define WM8960_POWER1_VMIDSEL_MASK (0x180U) +#define WM8960_POWER1_VMIDSEL_SHIFT (7U) +#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) +#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) + +/* + * VREF (RW) + * + * VREF (necessary for all other functions) + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_VREF_MASK (0x40U) +#define WM8960_POWER1_VREF_SHIFT (6U) +#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) +#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) + +/* + * AINL (RW) + * + * Analogue in PGA Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINL_MASK (0x20U) +#define WM8960_POWER1_AINL_SHIFT (5U) +#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) +#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) + +/* + * AINR (RW) + * + * Analogue in PGA Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINR_MASK (0x10U) +#define WM8960_POWER1_AINR_SHIFT (4U) +#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) +#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) + +/* + * ADCL (RW) + * + * ADC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCL_MASK (0x8U) +#define WM8960_POWER1_ADCL_SHIFT (3U) +#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) +#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) + +/* + * ADCR (RW) + * + * ADC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCR_MASK (0x4U) +#define WM8960_POWER1_ADCR_SHIFT (2U) +#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) +#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) + +/* + * MICB (RW) + * + * MICBIAS + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_MICB_MASK (0x2U) +#define WM8960_POWER1_MICB_SHIFT (1U) +#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) +#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) + +/* + * DIGENB (RW) + * + * Master Clock Disable + * 0 = Master clock enabled + * 1 = Master clock disabled + */ +#define WM8960_POWER1_DIGENB_MASK (0x1U) +#define WM8960_POWER1_DIGENB_SHIFT (0U) +#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) +#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) + +/* Bitfield definition for register: POWER2 */ +/* + * DACL (RW) + * + * DAC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACL_MASK (0x100U) +#define WM8960_POWER2_DACL_SHIFT (8U) +#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) +#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) + +/* + * DACR (RW) + * + * DAC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACR_MASK (0x80U) +#define WM8960_POWER2_DACR_SHIFT (7U) +#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) +#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) + +/* + * LOUT1 (RW) + * + * LOUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_LOUT1_MASK (0x40U) +#define WM8960_POWER2_LOUT1_SHIFT (6U) +#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) +#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) + +/* + * ROUT1 (RW) + * + * ROUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_ROUT1_MASK (0x20U) +#define WM8960_POWER2_ROUT1_SHIFT (5U) +#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) +#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) + +/* + * SPKL (RW) + * + * SPK_LP/SPK_LN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKL_MASK (0x10U) +#define WM8960_POWER2_SPKL_SHIFT (4U) +#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) +#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) + +/* + * SPKR (RW) + * + * SPK_RP/SPK_RN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKR_MASK (0x8U) +#define WM8960_POWER2_SPKR_SHIFT (3U) +#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) +#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) + +/* + * OUT3 (RW) + * + * OUT3 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_OUT3_MASK (0x2U) +#define WM8960_POWER2_OUT3_SHIFT (1U) +#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) +#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) + +/* + * PLL_EN (RW) + * + * PLL Enable + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_PLL_EN_MASK (0x1U) +#define WM8960_POWER2_PLL_EN_SHIFT (0U) +#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) +#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) + +/* Bitfield definition for register: ADDCTL3 */ +/* + * VROI (RW) + * + * VREF to Analogue Output Resistance (Disabled + * Outputs) + * 0 = 500 VMID to output + * 1 = 20k VMID to output + */ +#define WM8960_ADDCTL3_VROI_MASK (0x40U) +#define WM8960_ADDCTL3_VROI_SHIFT (6U) +#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) +#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) + +/* + * OUT3CAP (RW) + * + * Capless Mode Headphone Switch Enable + * 0 = OUT3 unaffected by jack detect events + * 1 = OUT3 enabled and disabled together with + * HP_L and HP_R in response to jack detect + * events + */ +#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) +#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) +#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) +#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) + +/* + * ADC_ALC_SR (RW) + * + * ALC Sample Rate + * 000 = 44.1k / 48k + * 001 = 32k + * 010 = 22.05k / 24k + * 011 = 16k + * 100 = 11.25k / 12k + * 101 = 8k + * 110 and 111 = Reserved + */ +#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) +#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) + +/* Bitfield definition for register: APOP1 */ +/* + * POBCTRL (RW) + * + * Selects the bias current source for output + * amplifiers and VMID buffer + * 0 = VMID / R bias + * 1 = VGS / R bias + */ +#define WM8960_APOP1_POBCTRL_MASK (0x80U) +#define WM8960_APOP1_POBCTRL_SHIFT (7U) +#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) +#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) + +/* + * BUFDCOPEN (RW) + * + * Enables the VGS / R current generator + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) +#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) +#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) +#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) + +/* + * BUFIOEN (RW) + * + * Enables the VGS / R current generator and the + * analogue input and output bias + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFIOEN_MASK (0x8U) +#define WM8960_APOP1_BUFIOEN_SHIFT (3U) +#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) +#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) + +/* + * SOFT_ST (RW) + * + * Enables VMID soft start + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_SOFT_ST_MASK (0x4U) +#define WM8960_APOP1_SOFT_ST_SHIFT (2U) +#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) +#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) + +/* + * HPSTBY (RW) + * + * Headphone Amplifier Standby + * 0 = Standby mode disabled (Normal operation) + * 1 = Standby mode enabled + */ +#define WM8960_APOP1_HPSTBY_MASK (0x1U) +#define WM8960_APOP1_HPSTBY_SHIFT (0U) +#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) +#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) + +/* Bitfield definition for register: APOP2 */ +/* + * DISOP (RW) + * + * Discharges the DC-blocking headphone + * capacitors on HP_L and HP_R + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP2_DISOP_MASK (0x40U) +#define WM8960_APOP2_DISOP_SHIFT (6U) +#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) +#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) + +/* + * DRES (RW) + * + * DRES determines the value of the resistors used + * to discharge the DC-blocking headphone + * capacitors when DISOP=1 + * DRES[1:0] Resistance (Ohms) + * 0 0 400 + * 0 1 200 + * 1 0 600 + * 1 1 150 + */ +#define WM8960_APOP2_DRES_MASK (0x30U) +#define WM8960_APOP2_DRES_SHIFT (4U) +#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) +#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) + +/* Bitfield definition for register: LINPATH */ +/* + * LMN1 (RW) + * + * Connect LINPUT1 to inverting input of Left Input + * PGA + * 0 = LINPUT1 not connected to PGA + * 1 = LINPUT1 connected to PGA + */ +#define WM8960_LINPATH_LMN1_MASK (0x100U) +#define WM8960_LINPATH_LMN1_SHIFT (8U) +#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) +#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) + +/* + * LMP3 (RW) + * + * Connect LINPUT3 to non-inverting input of Left + * Input PGA + * 0 = LINPUT3 not connected to PGA + * 1 = LINPUT3 connected to PGA (Constant input + * impedance) + */ +#define WM8960_LINPATH_LMP3_MASK (0x80U) +#define WM8960_LINPATH_LMP3_SHIFT (7U) +#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) +#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) + +/* + * LMP2 (RW) + * + * Connect LINPUT2 to non-inverting input of Left + * Input PGA + * 0 = LINPUT2 not connected to PGA + * 1 = LINPUT2 connected to PGA (Constant input impedance) + */ +#define WM8960_LINPATH_LMP2_MASK (0x40U) +#define WM8960_LINPATH_LMP2_SHIFT (6U) +#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) +#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) + +/* + * LMICBOOST (RW) + * + * Left Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) +#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) +#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) +#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) + +/* + * LMIC2B (RW) + * + * Connect Left Input PGA to Left Input Boost Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_LINPATH_LMIC2B_MASK (0x8U) +#define WM8960_LINPATH_LMIC2B_SHIFT (3U) +#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) +#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) + +/* Bitfield definition for register: RINPATH */ +/* + * RMN1 (RW) + * + * Connect RINPUT1 to inverting input of Right + * Input PGA + * 0 = RINPUT1 not connected to PGA + * 1 = RINPUT1 connected to PGA + */ +#define WM8960_RINPATH_RMN1_MASK (0x100U) +#define WM8960_RINPATH_RMN1_SHIFT (8U) +#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) +#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) + +/* + * RMP3 (RW) + * + * Connect RINPUT3 to non-inverting input of Right + * Input PGA + * 0 = RINPUT3 not connected to PGA + * 1 = RINPUT3 connected to PGA (Constant input impedance) + */ +#define WM8960_RINPATH_RMP3_MASK (0x80U) +#define WM8960_RINPATH_RMP3_SHIFT (7U) +#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) +#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) + +/* + * RMP2 (RW) + * + * Connect RINPUT2 to non-inverting input of Right + * Input PGA + * 0 = RINPUT2 not connected to PGA + * 1 = RINPUT2 connected to PGA (Constant input + * impedance) + */ +#define WM8960_RINPATH_RMP2_MASK (0x40U) +#define WM8960_RINPATH_RMP2_SHIFT (6U) +#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) +#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) + +/* + * RMICBOOST (RW) + * + * Right Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) +#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) +#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) +#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) + +/* + * RMIC2B (RW) + * + * Connect Right Input PGA to Right Input Boost + * Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_RINPATH_RMIC2B_MASK (0x8U) +#define WM8960_RINPATH_RMIC2B_SHIFT (3U) +#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) +#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) + +/* Bitfield definition for register: LOUTMIX */ +/* + * LD2LO (RW) + * + * Left DAC to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) +#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) +#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) +#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) + +/* + * LI2LO (RW) + * + * LINPUT3 to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) +#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) +#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) +#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) + +/* + * LI2LOVOL (RW) + * + * LINPUT3 to Left Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) +#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) +#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) +#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) + +/* Bitfield definition for register: ROUTMIX */ +/* + * RD2RO (RW) + * + * Right DAC to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) +#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) +#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) +#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) + +/* + * RI2RO (RW) + * + * RINPUT3 to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) +#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) +#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) +#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) + +/* + * RI2ROVOL (RW) + * + * RINPUT3 to Right Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) +#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) +#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) +#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) + +/* Bitfield definition for register: MONOMIX1 */ +/* + * L2MO (RW) + * + * Left Output Mixer to Mono Output Mixer Control + * 0 = Left channel mix disabled + * 1 = Left channel mix enabled + */ +#define WM8960_MONOMIX1_L2MO_MASK (0x80U) +#define WM8960_MONOMIX1_L2MO_SHIFT (7U) +#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) +#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) + +/* Bitfield definition for register: MONOMIX2 */ +/* + * R2MO (RW) + * + * Right Output Mixer to Mono Output Mixer Control + * 0 = Right channel mix disabled + * 1 = Right channel mix enabled + */ +#define WM8960_MONOMIX2_R2MO_MASK (0x80U) +#define WM8960_MONOMIX2_R2MO_SHIFT (7U) +#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) +#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) + +/* Bitfield definition for register: LOUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_LOUT2_SPKVU_MASK (0x100U) +#define WM8960_LOUT2_SPKVU_SHIFT (8U) +#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) +#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) + +/* + * SPKLZC (RW) + * + * Left Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_LOUT2_SPKLZC_MASK (0x80U) +#define WM8960_LOUT2_SPKLZC_SHIFT (7U) +#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) +#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) + +/* + * SPKLVOL (RW) + * + * SPK_LP/SPK_LN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) +#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) +#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) +#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) + +/* Bitfield definition for register: ROUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right + * speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_ROUT2_SPKVU_MASK (0x100U) +#define WM8960_ROUT2_SPKVU_SHIFT (8U) +#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) +#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) + +/* + * SPKRZC (RW) + * + * Right Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_ROUT2_SPKRZC_MASK (0x80U) +#define WM8960_ROUT2_SPKRZC_SHIFT (7U) +#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) +#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) + +/* + * SPKRVOL (RW) + * + * SPK_RP/SPK_RN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) +#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) +#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) +#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) + +/* Bitfield definition for register: MONO */ +/* + * MOUTVOL (RW) + * + * Mono Output Mixer Volume Control + * 0 = 0dB + * 1 = -6dB + */ +#define WM8960_MONO_MOUTVOL_MASK (0x40U) +#define WM8960_MONO_MOUTVOL_SHIFT (6U) +#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) +#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) + +/* Bitfield definition for register: INBMIX1 */ +/* + * LIN3BOOST (RW) + * + * LINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) +#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) + +/* + * LIN2BOOST (RW) + * + * LINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) +#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) + +/* Bitfield definition for register: INBMIX2 */ +/* + * RIN3BOOST (RW) + * + * RINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) +#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) + +/* + * RIN2BOOST (RW) + * + * RINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) +#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) + +/* Bitfield definition for register: BYPASS1 */ +/* + * LB2LO (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS1_LB2LO_MASK (0x80U) +#define WM8960_BYPASS1_LB2LO_SHIFT (7U) +#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) +#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) + +/* + * LB2LOVOL (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) +#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) +#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) +#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) + +/* Bitfield definition for register: BYPASS2 */ +/* + * RB2RO (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS2_RB2RO_MASK (0x80U) +#define WM8960_BYPASS2_RB2RO_SHIFT (7U) +#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) +#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) + +/* + * RB2ROVOL (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) +#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) +#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) +#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) + +/* Bitfield definition for register: POWER3 */ +/* + * LMIC (RW) + * + * Left Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINL = 1) + */ +#define WM8960_POWER3_LMIC_MASK (0x20U) +#define WM8960_POWER3_LMIC_SHIFT (5U) +#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) +#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) + +/* + * RMIC (RW) + * + * Right Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINR = 1) + */ +#define WM8960_POWER3_RMIC_MASK (0x10U) +#define WM8960_POWER3_RMIC_SHIFT (4U) +#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) +#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) + +/* + * LOMIX (RW) + * + * Left Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_LOMIX_MASK (0x8U) +#define WM8960_POWER3_LOMIX_SHIFT (3U) +#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) +#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) + +/* + * ROMIX (RW) + * + * Right Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_ROMIX_MASK (0x4U) +#define WM8960_POWER3_ROMIX_SHIFT (2U) +#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) +#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) + +/* Bitfield definition for register: ADDCTL4 */ +/* + * GPIOPOL (RW) + * + * GPIO Polarity Invert + * 0 = Non inverted + * 1 = Inverted + */ +#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) +#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) +#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) +#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) + +/* + * GPIOSEL (RW) + * + * ADCLRC/GPIO1 GPIO Function Select: + * 000 = Jack detect input + * 001 = Reserved + * 010 = Temperature ok + * 011 = Debounced jack detect output + * 100 = SYSCLK output + * 101 = PLL lock + * 110 = Logic 0 + * 111 = Logic 1 + */ +#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) +#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) +#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) +#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) + +/* + * HPSEL (RW) + * + * Headphone Switch Input Select + * 0X = GPIO1 used for jack detect input (Requires + * ADCLRC pin to be configured as a GPIO) + * 10 = JD2 used for jack detect input + * 11 = JD3 used for jack detect input + */ +#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) +#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) +#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) +#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) + +/* + * TSENSEN (RW) + * + * Temperature Sensor Enable + * 0 = Temperature sensor disabled + * 1 = Temperature sensor enabled + */ +#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) +#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) +#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) +#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) + +/* + * MBSEL (RW) + * + * Microphone Bias Voltage Control + * 0 = 0.9 * AVDD + * 1 = 0.65 * AVDD + */ +#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) +#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) +#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) +#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) + +/* Bitfield definition for register: CLASSD1 */ +/* + * SPK_OP_EN (RW) + * + * Enable Class D Speaker Outputs + * 00 = Off + * 01 = Left speaker only + * 10 = Right speaker only + * 11 = Left and right speakers enabled + */ +#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) +#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) +#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) +#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) + +/* Bitfield definition for register: CLASSD3 */ +/* + * DCGAIN (RW) + * + * DC Speaker Boost (Boosts speaker DC output + * level by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) +#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) +#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) +#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) + +/* + * ACGAIN (RW) + * + * AC Speaker Boost (Boosts speaker AC output + * signal by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) +#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) +#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) +#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) + +/* Bitfield definition for register: PLL1 */ +/* + * OPCLKDIV (RW) + * + * SYSCLK Output to GPIO Clock Division ratio + * 000 = SYSCLK + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 5.5 + * 101 = SYSCLK / 6 + */ +#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) +#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) +#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) +#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) + +/* + * SDM (RW) + * + * Enable Integer Mode + * 0 = Integer mode + * 1 = Fractional mode + */ +#define WM8960_PLL1_SDM_MASK (0x20U) +#define WM8960_PLL1_SDM_SHIFT (5U) +#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) +#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) + +/* + * PLLPRESCALE (RW) + * + * Divide MCLK by 2 before input to PLL + * 0 = Divide by 1 + * 1 = Divide by 2 + */ +#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) +#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) +#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) +#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) + +/* + * PLLN (RW) + * + * Integer (N) part of PLL input/output frequency + * ratio. Use values greater than 5 and less than 13 + */ +#define WM8960_PLL1_PLLN_MASK (0xFU) +#define WM8960_PLL1_PLLN_SHIFT (0U) +#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) +#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) + +/* Bitfield definition for register: PLL2 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL2_PLLK_MASK (0xFFU) +#define WM8960_PLL2_PLLK_SHIFT (0U) +#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) +#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) + +/* Bitfield definition for register: PLL3 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL3_PLLK_MASK (0xFFU) +#define WM8960_PLL3_PLLK_SHIFT (0U) +#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) +#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) + +/* Bitfield definition for register: PLL4 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL4_PLLK_MASK (0xFFU) +#define WM8960_PLL4_PLLK_SHIFT (0U) +#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) +#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) + + +#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..16d433aa93 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,297 @@ +/* + * Copyright 2021-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + +} diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 0000000000..26ed72c84a --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,316 @@ +/* + * Copyright 2021-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..79769ad59d --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,248 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 512K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01280000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + +} diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.c b/bsp/hpmicro/hpm6e00evk/board/pinmux.c new file mode 100644 index 0000000000..27f72fa1cb --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.c @@ -0,0 +1,699 @@ +/* + * Copyright (c) 2023-2024 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART1) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART1_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART1_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; + } else if (ptr == HPM_UART14) { + HPM_IOC->PAD[IOC_PAD_PF24].FUNC_CTL = IOC_PF24_FUNC_CTL_UART14_TXD; + HPM_IOC->PAD[IOC_PAD_PF25].FUNC_CTL = IOC_PF25_FUNC_CTL_UART14_RXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PURT_TXD; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PURT_RXD; + } else { + ; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PA00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_GPIO_A_00; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_GPIO_A_01; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY02].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PY03].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_PY_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_SOC_PY_03; + + } else if (ptr == HPM_I2C1) { + /* WM8960 audio_codec */ + HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PF12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PF13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PF12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PF13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + ; + } +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_GPIO_Y_02; + HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_GPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + } else if (ptr == HPM_I2C1) { +#if 1 + /* WM8960 audio_codec */ + HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; +#else + /* raspberry-Pi_IF */ + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_GPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_GPIO_Y_07; +#endif + } else { + ; + } +} + +void init_femc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_A_00; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_A_01; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_A_02; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_A_03; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_A_04; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_A_05; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_FEMC_A_06; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_07; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_A_08; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_A_09; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_A_10; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_A_11; /* SRAM: NWE */ + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_A_12; /* SRAM: NOE */ + + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_FEMC_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_FEMC_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_FEMC_DQ_02; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_FEMC_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_FEMC_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_FEMC_DQ_05; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_FEMC_DQ_06; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_FEMC_DQ_07; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_FEMC_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_FEMC_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_FEMC_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_FEMC_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_FEMC_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_FEMC_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_FEMC_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_FEMC_DQ_15; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQ_16; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_DQ_17; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_DQ_18; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_DQ_19; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_DQ_20; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_DQ_21; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_FEMC_DQ_22; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_DQ_23; + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_FEMC_DQ_24; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_FEMC_DQ_25; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_FEMC_DQ_26; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_DQ_27; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_DQ_28; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_DQ_29; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_DQ_30; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_DQ_31; + + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_FEMC_DM_0; /* SRAM: NLB */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_FEMC_DM_1; /* SRAM: NUB */ + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_DM_2; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_DM_3; + + HPM_IOC->PAD[IOC_PAD_PX07].FUNC_CTL = IOC_PX07_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + + /* SDRAM */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_BA0; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_BA1; /* SRAM: NADV */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_RAS; + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_CAS; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_CKE; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_CLK_0; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_WE; + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_FEMC_CS_0; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_CS_1; + + /* SRAM */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_SCLK_0; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_SCLK_1; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_SCS_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_SCS_1; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_FEMC_SRDY; +} + +void init_ppi_pins(void) +{ + /* DQ Group A */ + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PPI0_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PPI0_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PPI0_DQ_02; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PPI0_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_PPI0_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_PPI0_DQ_05; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_PPI0_DQ_06; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_PPI0_DQ_07; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_PPI0_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_PPI0_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_PPI0_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_PPI0_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_PPI0_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_PPI0_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_PPI0_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_PPI0_DQ_15; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_PPI0_DQ_16; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_PPI0_DQ_17; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PPI0_DQ_18; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PPI0_DQ_19; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PPI0_DQ_20; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PPI0_DQ_21; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PPI0_DQ_22; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_PPI0_DQ_23; + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PPI0_DQ_24; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PPI0_DQ_25; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PPI0_DQ_26; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PPI0_DQ_27; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PPI0_DQ_28; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_PPI0_DQ_29; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_PPI0_DQ_30; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_PPI0_DQ_31; + + /* DM Group A */ + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_PPI0_DM_0; + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_PPI0_DM_1; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_PPI0_DM_2; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_PPI0_DM_3; + + /* CS */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_PPI0_CS_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_PPI0_CS_1; + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_PPI0_CS_2; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_PPI0_CS_3; + + /* CTRL */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_PPI0_CTR_0; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_PPI0_CTR_1; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_PPI0_CTR_2; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_PPI0_CTR_3; + HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PPI0_CTR_4; + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PPI0_CTR_5; + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_PPI0_CTR_6; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PPI0_CTR_7; + + /* CLK */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_PPI0_CLK; + + /* DQ Group B */ + /* + * HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PPI0_DQ_00; + * HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PPI0_DQ_01; + * HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PPI0_DQ_02; + * HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PPI0_DQ_03; + * HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_PPI0_DQ_04; + * HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_PPI0_DQ_05; + * HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_PPI0_DQ_06; + * HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_PPI0_DQ_07; + * HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_PPI0_DQ_08; + * HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_PPI0_DQ_09; + * HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PPI0_DQ_10; + * HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_PPI0_DQ_11; + * HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_PPI0_DQ_12; + * HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PPI0_DQ_13; + * HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_PPI0_DQ_14; + * HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_PPI0_DQ_15; + */ + + /* DM Group B */ + /* + * HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_PPI0_DM_0; + * HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_PPI0_DM_1; + */ +} + +void init_sdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF17].FUNC_CTL = IOC_PF17_FUNC_CTL_SDM0_CLK_0; + HPM_IOC->PAD[IOC_PAD_PF16].FUNC_CTL = IOC_PF16_FUNC_CTL_SDM0_DAT_0; +} + +void init_pwm_pin_as_sdm_clock(void) +{ + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_PWM2_P_3; +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_GPIO_B_25; + HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; + HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI7) { + HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_SPI7_CS_0; + HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO; + HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI; + } else { + ; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI7) { + HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_GPIO_F_27; + HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO; + HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI; + } +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR4) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR4_COMP_0; + } + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_GPTMR0_COMP_0; + } + if (ptr == HPM_GPTMR5) { + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_GPTMR5_COMP_2; + + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; + HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_GPIO_B_25; + HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = pad_ctl; +} + +void init_acmp_pins(void) +{ + /* configure to CMP0_INN4 function */ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm_fault_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05; +} + +void init_pwm_pins(PWMV2_Type *ptr) +{ + if (ptr == HPM_PWM1) { + HPM_IOC->PAD[IOC_PAD_PE08].FUNC_CTL = IOC_PE08_FUNC_CTL_PWM1_P_0; + HPM_IOC->PAD[IOC_PAD_PE09].FUNC_CTL = IOC_PE09_FUNC_CTL_PWM1_P_1; + HPM_IOC->PAD[IOC_PAD_PE10].FUNC_CTL = IOC_PE10_FUNC_CTL_PWM1_P_2; + HPM_IOC->PAD[IOC_PAD_PE11].FUNC_CTL = IOC_PE11_FUNC_CTL_PWM1_P_3; + HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_PWM1_P_4; + HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_PWM1_P_5; + } else { + ; + } +} + +void init_usb_pins(void) +{ + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR; +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2S0_FCLK; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_I2S0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2S0_RXD_0; + } else { + ; + } +} + +void init_qeo_pins(QEOV2_Type *ptr) +{ + if (ptr == HPM_QEO0) { + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_QEO0_A; /* Motor CON3 */ + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_QEO0_B; + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_QEO0_Z; + } else { + ; + } +} + +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + if (ptr == HPM_SEI) { + if (sei_ctrl_idx == SEI_CTRL_1) { + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_SEI1_DE; + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_SEI1_CK; + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_SEI1_TX; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_SEI1_RX; + } else { + ; + } + } +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_QEI0_Z; + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_QEI0_Z; + } +} + +void init_rdc_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 PWN_P */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.10 / ADC1.10 PWN_N */ + HPM_IOC->PAD[IOC_PAD_PE08].FUNC_CTL = IOC_PE08_FUNC_CTL_RDC0_PWM_N; +/*The GPIO is designed for debug */ +#ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_TRGM_P_00; +#endif +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_DAO_RP; + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_DAO_RN; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_PDM0_D_0; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_ETH0_MDIO; + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_ETH0_MDC; + + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH0_RXDV; + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_ETH0_RXD_3; + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ETH0_RXCK; + + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PE29_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_ETH0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_ETH0_TXEN; + } +} + +void init_enet_pps_pins(void) +{ + +} + +void init_adc16_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */ + HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.10 / ADC1.10 */ + HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC2.11 / ADC3.11 */ + + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.1 / ADC1.1 */ + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.15 / ADC1.15 */ + HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC2.00 / ADC3.00 */ + HPM_IOC->PAD[IOC_PAD_PF20].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC2.03 / ADC3.03 */ + +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC2.11 / ADC3.11 cos_ch */ + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 sin_ch */ +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN4) { + HPM_IOC->PAD[IOC_PAD_PZ00].FUNC_CTL = IOC_PZ00_FUNC_CTL_MCAN4_TXD; + HPM_BIOC->PAD[IOC_PAD_PZ00].FUNC_CTL = BIOC_PZ00_FUNC_CTL_SOC_PZ_00; + HPM_IOC->PAD[IOC_PAD_PZ01].FUNC_CTL = IOC_PZ01_FUNC_CTL_MCAN4_RXD; + HPM_BIOC->PAD[IOC_PAD_PZ01].FUNC_CTL = BIOC_PZ01_FUNC_CTL_SOC_PZ_01; + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_MCAN4_STBY; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02; + } else { + /* Invalid CAN instance */ + } +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15; +} + +void init_led_pins_as_pwm(void) +{ + /* Red */ + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_PWM1_P_6; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_PWM1_P_7; + /* BLUE */ + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM0_P_4; +} + +void init_plb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05; +} + +void init_esc_pins(void) +{ + /* ESC */ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_ESC0_MDIO; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_ESC0_MDC; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_ESC0_SDA; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_ESC0_SCL; + + /* ESC needs to configure these pins for specific functions, see ESC IOCFG registers */ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; /* GPIO to reset PHY */ + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_ESC0_CTR_3; /* NMII_LINK0(PORTA_LINK) function */ + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_ESC0_CTR_0; /* NMII_LINK1(PORTB_LINK) function */ + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ESC0_CTR_6; /* LED_ERROR function */ + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ESC0_CTR_1; /* LED_RUN function */ + + /* ESC PORTA */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_ESC0_P0_TXCK; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_ESC0_P0_TXEN; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ESC0_P0_RXCK; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ESC0_P0_RXDV; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ESC0_P0_RXER; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3; + + /* ESC PORTB */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_ESC0_P1_TXCK; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_ESC0_P1_TXEN; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_ESC0_P1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_ESC0_P1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_ESC0_P1_TXD_2; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_ESC0_P1_TXD_3; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_ESC0_P1_RXCK; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_ESC0_P1_RXDV; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_ESC0_P1_RXER; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_ESC0_P1_RXD_0; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_ESC0_P1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_ESC0_P1_RXD_2; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_ESC0_P1_RXD_3; +} + +void init_tsw_pins(void) +{ + /* PORT1 */ + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_TSW0_P1_RXDV; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_TSW0_P1_RXCK; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_TSW0_P1_RXD_0; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_TSW0_P1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_TSW0_P1_RXD_2; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TSW0_P1_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_TSW0_P1_TXEN; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_TSW0_P1_TXCK; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_TSW0_P1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TSW0_P1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_TSW0_P1_TXD_2; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_TSW0_P1_TXD_3; + + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TSW0_P1_RXER; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_TSW0_P1_MDC; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_TSW0_P1_MDIO; + + /* PORT2 */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TSW0_P2_RXDV; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_TSW0_P2_RXCK; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TSW0_P2_RXD_0; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_TSW0_P2_RXD_1; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_TSW0_P2_RXD_2; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_TSW0_P2_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TSW0_P2_TXEN; + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_TSW0_P2_TXCK; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_TSW0_P2_TXD_0; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_TSW0_P2_TXD_1; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TSW0_P2_TXD_2; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TSW0_P2_TXD_3; + + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_TSW0_P2_RXER; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_TSW0_P2_MDC; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_TSW0_P2_MDIO; + + /* PORT1/PORT2 PHY RST */ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; + + /* XI */ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK; + + /* PORT3 PE */ + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_TSW0_P3_RXDV; + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_TSW0_P3_RXCK; + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_TSW0_P3_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_TSW0_P3_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_TSW0_P3_RXD_2; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_TSW0_P3_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_TSW0_P3_TXEN; + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_TSW0_P3_TXCK; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_TSW0_P3_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_TSW0_P3_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PE29_FUNC_CTL_TSW0_P3_TXD_2; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_TSW0_P3_TXD_3; + + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_TSW0_P3_MDC; + HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_TSW0_P3_MDIO; + + /* PORT3 PHY INT */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; + + /* PORT3 PHY RST */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14; +} + +void init_tamper_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_TAMP_PZ_03; +} + +void init_esc_in_out_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_GPIO_C_31; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_GPIO_D_08; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_GPIO_D_09; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14; +} + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PF27].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_GPIO_F_27; +}
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.h b/bsp/hpmicro/hpm6e00evk/board/pinmux.h new file mode 100644 index 0000000000..13633d1160 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_femc_pins(void); +void init_ppi_pins(void); +void init_sdm_pins(void); +void init_pwm_pin_as_sdm_clock(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWMV2_Type *ptr); +void init_usb_pins(void); +void init_i2s_pins(I2S_Type *ptr); +void init_qeo_pins(QEOV2_Type *ptr); +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_rdc_pin(void); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_enet_pps_pins(void); +void init_adc16_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_pins(void); +void init_esc_pins(void); +void init_esc_in_out_pin(void); +void init_tsw_pins(void); +void init_tamper_pins(void); +void init_pwm_fault_pins(void); +void init_uart_break_signal_pin(void); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm6e00evk/board/rtt_board.c b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c new file mode 100644 index 0000000000..ac67a31d8a --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include <rthw.h> +#include <rtthread.h> +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); + gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + case 1: + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state); + break; + case 2: + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif diff --git a/bsp/hpmicro/hpm6e00evk/board/rtt_board.h b/bsp/hpmicro/hpm6e00evk/board/rtt_board.h new file mode 100644 index 0000000000..0c056aec76 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/rtt_board.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" + +/* gpio section */ +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOE +#define APP_LED0_GPIO_PIN 14 +#define APP_LED1_GPIO_CTRL HPM_GPIO0 +#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOE +#define APP_LED1_GPIO_PIN 15 +#define APP_LED2_GPIO_CTRL HPM_GPIO0 +#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOE +#define APP_LED2_GPIO_PIN 4 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can4" +#define BOARD_CAN_HWFILTER_INDEX (4U) + +/* UART section */ +#define BOARD_UART_NAME "uart1" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART1_RX_BUFSIZE + + +/* audio section */ +#define BOARD_AUDIO_CODEC_I2C_NAME "i2c0" +#define BOARD_AUDIO_CODEC_I2S_NAME "i2s0" + +/* PWM section */ +#define BOARD_PWM_NAME "pwm1" +#define BOARD_PWM_CHANNEL (0U) + +#define IRQn_PendSV IRQn_DEBUG0 + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6e00evk/figures/board.png b/bsp/hpmicro/hpm6e00evk/figures/board.png Binary files differnew file mode 100644 index 0000000000..1795e32e21 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/figures/board.png diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.h b/bsp/hpmicro/hpm6e00evk/rtconfig.h new file mode 100644 index 0000000000..83bbddc032 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.h @@ -0,0 +1,337 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_HPM6E00 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.py b/bsp/hpmicro/hpm6e00evk/rtconfig.py new file mode 100644 index 0000000000..0ef49a45d8 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.py @@ -0,0 +1,110 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +SOC_FAMILY='HPM6E00' +CHIP_NAME='HPM6E80' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/SConscript b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/SConscript new file mode 100644 index 0000000000..a1ec2c8e79 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c new file mode 100644 index 0000000000..1831ade775 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include <rtthread.h> + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S new file mode 100644 index 0000000000..2708b48e45 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S new file mode 100644 index 0000000000..63433e71ae --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include <rtconfig.h> + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..cc6604ec3b --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/vectors.S @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_V IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_W IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_V IRQ handler */ + IRQ_HANDLER 19 /* GPIO1_W IRQ handler */ + IRQ_HANDLER 20 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 23 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 24 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 25 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 26 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 27 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 28 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 29 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 30 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* I2C0 IRQ handler */ + IRQ_HANDLER 40 /* I2C1 IRQ handler */ + IRQ_HANDLER 41 /* I2C2 IRQ handler */ + IRQ_HANDLER 42 /* I2C3 IRQ handler */ + IRQ_HANDLER 43 /* SPI0 IRQ handler */ + IRQ_HANDLER 44 /* SPI1 IRQ handler */ + IRQ_HANDLER 45 /* SPI2 IRQ handler */ + IRQ_HANDLER 46 /* SPI3 IRQ handler */ + IRQ_HANDLER 47 /* TSNS IRQ handler */ + IRQ_HANDLER 48 /* MBX0A IRQ handler */ + IRQ_HANDLER 49 /* MBX0B IRQ handler */ + IRQ_HANDLER 50 /* MBX1A IRQ handler */ + IRQ_HANDLER 51 /* MBX1B IRQ handler */ + IRQ_HANDLER 52 /* EWDG0 IRQ handler */ + IRQ_HANDLER 53 /* EWDG1 IRQ handler */ + IRQ_HANDLER 54 /* EWDG2 IRQ handler */ + IRQ_HANDLER 55 /* EWDG3 IRQ handler */ + IRQ_HANDLER 56 /* HDMA IRQ handler */ + IRQ_HANDLER 57 /* LOBS IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_HANDLER 60 /* ADC2 IRQ handler */ + IRQ_HANDLER 61 /* ADC3 IRQ handler */ + IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */ + IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */ + IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */ + IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */ + IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */ + IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */ + IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */ + IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */ + IRQ_HANDLER 70 /* I2S0 IRQ handler */ + IRQ_HANDLER 71 /* I2S1 IRQ handler */ + IRQ_HANDLER 72 /* DAO IRQ handler */ + IRQ_HANDLER 73 /* PDM IRQ handler */ + IRQ_HANDLER 74 /* UART8 IRQ handler */ + IRQ_HANDLER 75 /* UART9 IRQ handler */ + IRQ_HANDLER 76 /* UART10 IRQ handler */ + IRQ_HANDLER 77 /* UART11 IRQ handler */ + IRQ_HANDLER 78 /* UART12 IRQ handler */ + IRQ_HANDLER 79 /* UART13 IRQ handler */ + IRQ_HANDLER 80 /* UART14 IRQ handler */ + IRQ_HANDLER 81 /* UART15 IRQ handler */ + IRQ_HANDLER 82 /* I2C4 IRQ handler */ + IRQ_HANDLER 83 /* I2C5 IRQ handler */ + IRQ_HANDLER 84 /* I2C6 IRQ handler */ + IRQ_HANDLER 85 /* I2C7 IRQ handler */ + IRQ_HANDLER 86 /* SPI4 IRQ handler */ + IRQ_HANDLER 87 /* SPI5 IRQ handler */ + IRQ_HANDLER 88 /* SPI6 IRQ handler */ + IRQ_HANDLER 89 /* SPI7 IRQ handler */ + IRQ_HANDLER 90 /* MCAN0 IRQ handler */ + IRQ_HANDLER 91 /* MCAN1 IRQ handler */ + IRQ_HANDLER 92 /* MCAN2 IRQ handler */ + IRQ_HANDLER 93 /* MCAN3 IRQ handler */ + IRQ_HANDLER 94 /* MCAN4 IRQ handler */ + IRQ_HANDLER 95 /* MCAN5 IRQ handler */ + IRQ_HANDLER 96 /* MCAN6 IRQ handler */ + IRQ_HANDLER 97 /* MCAN7 IRQ handler */ + IRQ_HANDLER 98 /* PTPC IRQ handler */ + IRQ_HANDLER 99 /* QEI0 IRQ handler */ + IRQ_HANDLER 100 /* QEI1 IRQ handler */ + IRQ_HANDLER 101 /* QEI2 IRQ handler */ + IRQ_HANDLER 102 /* QEI3 IRQ handler */ + IRQ_HANDLER 103 /* PWM0 IRQ handler */ + IRQ_HANDLER 104 /* PWM1 IRQ handler */ + IRQ_HANDLER 105 /* PWM2 IRQ handler */ + IRQ_HANDLER 106 /* PWM3 IRQ handler */ + IRQ_HANDLER 107 /* RDC0 IRQ handler */ + IRQ_HANDLER 108 /* RDC1 IRQ handler */ + IRQ_HANDLER 109 /* SDM0 IRQ handler */ + IRQ_HANDLER 110 /* SDM1 IRQ handler */ + IRQ_HANDLER 111 /* SEI[0] IRQ handler */ + IRQ_HANDLER 112 /* SEI[1] IRQ handler */ + IRQ_HANDLER 113 /* SEI[2] IRQ handler */ + IRQ_HANDLER 114 /* SEI[3] IRQ handler */ + IRQ_HANDLER 115 /* MTG0 IRQ handler */ + IRQ_HANDLER 116 /* MTG1 IRQ handler */ + IRQ_HANDLER 117 /* VSC0 IRQ handler */ + IRQ_HANDLER 118 /* VSC1 IRQ handler */ + IRQ_HANDLER 119 /* CLC0[0] IRQ handler */ + IRQ_HANDLER 120 /* CLC0[1] IRQ handler */ + IRQ_HANDLER 121 /* CLC1[0] IRQ handler */ + IRQ_HANDLER 122 /* CLC1[1] IRQ handler */ + IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 125 /* ENET0 IRQ handler */ + IRQ_HANDLER 126 /* NTMR0 IRQ handler */ + IRQ_HANDLER 127 /* USB0 IRQ handler */ + IRQ_HANDLER 128 /* TSW[0] IRQ handler */ + IRQ_HANDLER 129 /* TSW[1] IRQ handler */ + IRQ_HANDLER 130 /* TSW[2] IRQ handler */ + IRQ_HANDLER 131 /* TSW[3] IRQ handler */ + IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ + IRQ_HANDLER 133 /* ESC IRQ handler */ + IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */ + IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */ + IRQ_HANDLER 136 /* ESC_RESET IRQ handler */ + IRQ_HANDLER 137 /* XPI0 IRQ handler */ + IRQ_HANDLER 138 /* FEMC IRQ handler */ + IRQ_HANDLER 139 /* PPI IRQ handler */ + IRQ_HANDLER 140 /* XDMA IRQ handler */ + IRQ_HANDLER 141 /* FFA IRQ handler */ + IRQ_HANDLER 142 /* SDP IRQ handler */ + IRQ_HANDLER 143 /* RNG IRQ handler */ + IRQ_HANDLER 144 /* PKA IRQ handler */ + IRQ_HANDLER 145 /* PSEC IRQ handler */ + IRQ_HANDLER 146 /* PGPIO IRQ handler */ + IRQ_HANDLER 147 /* PEWDG IRQ handler */ + IRQ_HANDLER 148 /* PTMR IRQ handler */ + IRQ_HANDLER 149 /* PUART IRQ handler */ + IRQ_HANDLER 150 /* FUSE IRQ handler */ + IRQ_HANDLER 151 /* SECMON IRQ handler */ + IRQ_HANDLER 152 /* RTC IRQ handler */ + IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 154 /* BGPIO IRQ handler */ + IRQ_HANDLER 155 /* BVIO IRQ handler */ + IRQ_HANDLER 156 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 157 /* SYSCTL IRQ handler */ + IRQ_HANDLER 158 /* CPU0 IRQ handler */ + IRQ_HANDLER 159 /* CPU1 IRQ handler */ + IRQ_HANDLER 160 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 161 /* DEBUG1 IRQ handler */
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/trap.c b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/trap.c new file mode 100644 index 0000000000..470b3fe266 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/trap.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include <rtthread.h> +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +}
\ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/startup/SConscript b/bsp/hpmicro/hpm6e00evk/startup/SConscript new file mode 100644 index 0000000000..de51a7c0d6 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs')
\ No newline at end of file |
