[bsp][renesas]add hwtimer device for renesas

17 files changed, 861 insertions, 14 deletions

diff --git a/bsp/renesas/docs/RA系列使用FSP配置外设驱动.md b/bsp/renesas/docs/RA系列使用FSP配置外设驱动.md
index 760e651b7a..c35fe6eeb1 100644
--- a/bsp/renesas/docs/RA系列使用FSP配置外设驱动.md
+++ b/bsp/renesas/docs/RA系列使用FSP配置外设驱动.md
@@ -77,7 +77,7 @@ RA系列已更新 **FSP 3.5.0** 版本的支持，请使用 **FSP 3.5.0** 版本
    {
        rt_kprintf("\n IRQ00 triggered \n");
    }
-
+   
    void icu_sample(void)
    {
        /* init */
@@ -192,6 +192,35 @@ RA系列已更新 **FSP 3.5.0** 版本的支持，请使用 **FSP 3.5.0** 版本
 
 4. 在 menuconfig 中打开对应的通道
 
+### Timer（GPT）
+
+GPT 定时器在该芯片中可作为通用定时器，可以用于计时功能。
+
+1、添加 GPT 设备
+
+![img](figures/add_gpt.png)
+
+2、对 GPT 较为关键的配置如图所示，具体解释如下：
+
+1. 设置开启的定时器名称，比如 timer0/1...
+2. 设置定时器通道，需要和定时器名称后缀名相同，比如 0/1...
+3. 设置定时器中断回调函数，比如 timer0—>**timer0_callback**，timer1—>**timer1_callback**
+4. 设置定时器中断优先级
+
+![img](figures/set_gpt.png)
+
+3、在 env 中配置 timer 外设：
+
+* 使能 timer 外设
+
+![img](figures/en_timer.png)
+
+* 选择需要打开的某个定时器
+
+![img](figures/en_timerx.png)
+
+* 最后使用 scons --target=mdk5 等方式生成工程
+
 ### PWM（GPT）
 
 GPT 定时器在该芯片中可作为通用定时器，也可以用于产生 PWM 信号。在将其用于产生 PWM 信号时，GPT 定时器提供了 gpt0 - gpt9 总共 10 个通道，每个通道可以设定两个输出端口。当前版本的 PWM 驱动将每个通道都看做一个单独的 PWM 设备，每个设备都只有一个通道。用户可以选择开启一个通道的任意一个输出端口，或将两个端口均开启，但在同时开启两个端口的情况下，它们输出的波形将完全一致。
diff --git a/bsp/renesas/docs/figures/add_gpt.png b/bsp/renesas/docs/figures/add_gpt.png
new file mode 100644
index 0000000000..b29c53e1fe
--- /dev/null
+++ b/bsp/renesas/docs/figures/add_gpt.png
diff --git a/bsp/renesas/docs/figures/en_timer.png b/bsp/renesas/docs/figures/en_timer.png
new file mode 100644
index 0000000000..eede25b4b4
--- /dev/null
+++ b/bsp/renesas/docs/figures/en_timer.png
diff --git a/bsp/renesas/docs/figures/en_timerx.png b/bsp/renesas/docs/figures/en_timerx.png
new file mode 100644
index 0000000000..90306097dc
--- /dev/null
+++ b/bsp/renesas/docs/figures/en_timerx.png
diff --git a/bsp/renesas/docs/figures/set_gpt.png b/bsp/renesas/docs/figures/set_gpt.png
new file mode 100644
index 0000000000..e10e7e4ca4
--- /dev/null
+++ b/bsp/renesas/docs/figures/set_gpt.png
diff --git a/bsp/renesas/libraries/HAL_Drivers/SConscript b/bsp/renesas/libraries/HAL_Drivers/SConscript
index 16a76beb58..86c1caa8de 100644
--- a/bsp/renesas/libraries/HAL_Drivers/SConscript
+++ b/bsp/renesas/libraries/HAL_Drivers/SConscript
@@ -53,6 +53,9 @@ if GetDepend(['BSP_USING_ONCHIP_FLASH']):
 if GetDepend(['BSP_USING_PWM']):
     src += ['drv_pwm.c']
 
+if GetDepend(['BSP_USING_TIM']):
+    src += ['drv_hwtimer.c']
+
 if GetDepend(['BSP_USING_ETH']):
     src += ['drv_eth.c']
 
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h b/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
index 0cd74a2e01..b3e011e474 100644
--- a/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -40,7 +40,31 @@ extern "C"
 #endif
 #endif /* SOC_SERIES_R7FA6M5 */
 
-#if (defined(SOC_SERIES_R7FA6M3)) || (defined(SOC_SERIES_R7FA6M4))
+#if defined(SOC_SERIES_R7FA6M3)
+#include "ra6m3/uart_config.h"
+
+#ifdef BSP_USING_ADC
+#include "ra6m3/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra6m3/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra6m3/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_TIM
+#include "ra6m3/timer_config.h"
+#endif
+
+#ifdef BSP_USING_CAN
+#include "ra6m3/can_config.h"
+#endif
+#endif /* SOC_SERIES_R7FA6M3 */
+
+#if defined(SOC_SERIES_R7FA6M4)
 #include "ra6m4/uart_config.h"
 
 #ifdef BSP_USING_ADC
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h
new file mode 100644
index 0000000000..d0856ae9db
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+struct ra_adc_map
+{
+    char name;
+    const adc_cfg_t *g_cfg;
+    const adc_instance_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+
+struct ra_dev
+{
+    rt_adc_device_t     ra_adc_device_t;
+    struct ra_adc_map  *ra_adc_dev;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/can_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/can_config.h
new file mode 100644
index 0000000000..9b63a0c56b
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/can_config.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                                                 \
+    {                                                               \
+        .name = "can0",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0,             \
+        .p_api_ctrl = &g_can0_ctrl,                                \
+        .p_cfg = &g_can0_cfg,                                      \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                                 \
+    {                                                               \
+        .name = "can1",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1,             \
+        .p_api_ctrl = &g_can1_ctrl,                                \
+        .p_cfg = &g_can1_cfg,                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/dac_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/dac_config.h
new file mode 100644
index 0000000000..99c30532b2
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/dac_config.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/pwm_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/pwm_config.h
new file mode 100644
index 0000000000..217cbc0b64
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/pwm_config.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-26     KevinXu           first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/timer_config.h
new file mode 100644
index 0000000000..adbd4f27e4
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/timer_config.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-09-04     Rbb666       first version
+ */
+
+#ifndef __TIMER_CONFIG_H__
+#define __TIMER_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define PLCKD_PRESCALER_MAX_SELECT     7
+
+/* RA6M3: Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64) */
+#define PLCKD_PRESCALER_120M           (BSP_FEATURE_GPT_ODC_FREQ_MAX)
+#define PLCKD_PRESCALER_60M            (BSP_FEATURE_GPT_ODC_FREQ_MAX / 2)
+#define PLCKD_PRESCALER_30M            (BSP_FEATURE_GPT_ODC_FREQ_MAX / 4)
+#define PLCKD_PRESCALER_15M            (BSP_FEATURE_GPT_ODC_FREQ_MAX / 8)
+#define PLCKD_PRESCALER_7_5M           (BSP_FEATURE_GPT_ODC_FREQ_MAX / 16)
+#define PLCKD_PRESCALER_3_75M          (BSP_FEATURE_GPT_ODC_FREQ_MAX / 32)
+#define PLCKD_PRESCALER_1_875M         (BSP_FEATURE_GPT_ODC_FREQ_MAX / 64)
+
+#ifndef TMR_DEV_INFO_CONFIG
+#define TMR_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 120000000,                   \
+        .minfreq = 1875000,                     \
+        .maxcnt  = 0XFFFFFFFF,                  \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+enum
+{
+#ifdef BSP_USING_TIM0
+    BSP_TIMER0_INDEX,
+#endif
+#ifdef BSP_USING_TIM1
+    BSP_TIMER1_INDEX,
+#endif
+    BSP_TIMERS_NUM
+};
+
+#define TIMER_DRV_INITIALIZER(num)      \
+    {                                   \
+        .name = "timer" #num,           \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_CONFIG_H__ */
diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/uart_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/uart_config.h
new file mode 100644
index 0000000000..a374567b36
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/uart_config.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .p_api_ctrl = &g_uart0_ctrl,                                \
+        .p_cfg = &g_uart0_cfg,                                      \
+    }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .p_api_ctrl = &g_uart1_ctrl,                                \
+        .p_cfg = &g_uart1_cfg,                                      \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .p_api_ctrl = &g_uart2_ctrl,                                \
+        .p_cfg = &g_uart2_cfg,                                      \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .p_api_ctrl = &g_uart3_ctrl,                                \
+        .p_cfg = &g_uart3_cfg,                                      \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .p_api_ctrl = &g_uart4_ctrl,                                \
+        .p_cfg = &g_uart4_cfg,                                      \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .p_api_ctrl = &g_uart5_ctrl,                                \
+        .p_cfg = &g_uart5_cfg,                                      \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .p_api_ctrl = &g_uart6_ctrl,                                \
+        .p_cfg = &g_uart6_cfg,                                      \
+    }
+#endif /* UART6_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .p_api_ctrl = &g_uart7_ctrl,                                \
+        .p_cfg = &g_uart7_cfg,                                      \
+    }
+#endif /* UART7_CONFIG */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .p_api_ctrl = &g_uart8_ctrl,                                \
+        .p_cfg = &g_uart8_cfg,                                      \
+    }
+#endif /* UART8_CONFIG */
+#endif /* BSP_USING_UART8 */
+
+#if defined(BSP_USING_UART9)
+#ifndef UART9_CONFIG
+#define UART9_CONFIG                                                \
+    {                                                               \
+        .name = "uart9",                                            \
+        .p_api_ctrl = &g_uart9_ctrl,                                \
+        .p_cfg = &g_uart9_cfg,                                      \
+    }
+#endif /* UART9_CONFIG */
+#endif /* BSP_USING_UART9 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.c
new file mode 100644
index 0000000000..dfe733655f
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-09-04     Rbb666       first version
+ */
+
+#include "board.h"
+#include "drv_hwtimer.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.timer"
+#include <rtdbg.h>
+
+#ifdef RT_USING_HWTIMER
+
+static struct ra_hwtimer ra_hwtimer_obj[BSP_TIMERS_NUM] =
+{
+#ifdef BSP_USING_TIM0
+    [BSP_TIMER0_INDEX] = TIMER_DRV_INITIALIZER(0),
+#endif
+#ifdef BSP_USING_TIM1
+    [BSP_TIMER1_INDEX] = TIMER_DRV_INITIALIZER(1),
+#endif
+};
+
+const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] =
+{
+#ifdef SOC_SERIES_R7FA6M3
+    PLCKD_PRESCALER_120M,
+    PLCKD_PRESCALER_60M,
+    PLCKD_PRESCALER_30M,
+    PLCKD_PRESCALER_15M,
+    PLCKD_PRESCALER_7_5M,
+    PLCKD_PRESCALER_3_75M,
+    PLCKD_PRESCALER_1_875M,
+#endif
+};
+
+static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    struct ra_hwtimer *tim;
+    tim = (struct ra_hwtimer *)timer->parent.user_data;
+
+    if (state)
+    {
+        fsp_err_t fsp_err = FSP_SUCCESS;
+
+        fsp_err = R_GPT_Open(tim->g_ctrl, tim->g_cfg);
+
+        if (fsp_err != FSP_SUCCESS)
+        {
+            LOG_E("%s init fail", tim->name);
+        }
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode)
+{
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(opmode != RT_NULL);
+
+    struct ra_hwtimer *tim;
+    tim = (struct ra_hwtimer *)timer->parent.user_data;
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* set timer count */
+    R_GPT_CounterSet(tim->g_ctrl, 0);
+    /* set timer period register */
+    err = R_GPT_PeriodSet(tim->g_ctrl, pr);
+
+    if (err != FSP_SUCCESS)
+    {
+        return -RT_ERROR;
+    }
+
+    /* set timer to one cycle mode */
+    err = R_GPT_Start(tim->g_ctrl);
+
+    return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+    struct ra_hwtimer *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+    tim = (struct ra_hwtimer *)timer->parent.user_data;
+
+    /* stop timer */
+    R_GPT_Stop(tim->g_ctrl);
+
+    /* set timer count */
+    R_GPT_CounterSet(tim->g_ctrl, 0);
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    struct ra_hwtimer *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (struct ra_hwtimer *)timer->parent.user_data;
+
+    timer_info_t info;
+    if (R_GPT_InfoGet(tim->g_ctrl, &info) != FSP_SUCCESS)
+        return -RT_ERROR;
+
+    return info.period_counts;
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct ra_hwtimer *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(arg != RT_NULL);
+
+    tim = (struct ra_hwtimer *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint8_t index = 0;
+        rt_uint32_t freq = *((rt_uint32_t *)arg);
+
+        for (rt_uint8_t i = 0; i < PLCKD_PRESCALER_MAX_SELECT; i++)
+        {
+            if (freq <= PLCKD_FREQ_PRESCALER[i])
+            {
+                index = i;
+            }
+        }
+        tim->g_ctrl->p_reg->GTCR_b.TPCS = index;
+    }
+    break;
+    default:
+    {
+        result = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return result;
+}
+
+static void timer_one_shot_check(void)
+{
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t *p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* If one-shot mode is selected, stop the timer since period has expired. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+        /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
+        p_instance_ctrl->p_reg->GTCNT = 0;
+        p_instance_ctrl->p_reg->GTCCR[0U] = 0;
+        p_instance_ctrl->p_reg->GTCCR[1U] = 0;
+
+        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
+        R_BSP_IrqClearPending(irq);
+    }
+}
+
+#ifdef BSP_USING_TIM0
+void timer0_callback(timer_callback_args_t *p_args)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (TIMER_EVENT_CYCLE_END == p_args->event)
+    {
+        rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER0_INDEX].tmr_device);
+
+        timer_one_shot_check();
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIM1
+void timer1_callback(timer_callback_args_t *p_args)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (TIMER_EVENT_CYCLE_END == p_args->event)
+    {
+        rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER1_INDEX].tmr_device);
+
+        timer_one_shot_check();
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+static const struct rt_hwtimer_ops _ops =
+{
+    .init = timer_init,
+    .start = timer_start,
+    .stop = timer_stop,
+    .count_get = timer_counter_get,
+    .control = timer_ctrl,
+};
+
+static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG;
+
+static int rt_hw_hwtimer_init(void)
+{
+    int result = RT_EOK;
+
+    for (int i = 0; i < sizeof(ra_hwtimer_obj) / sizeof(ra_hwtimer_obj[0]); i++)
+    {
+        ra_hwtimer_obj[i].tmr_device.info = &_info;
+        ra_hwtimer_obj[i].tmr_device.ops  = &_ops;
+        if (rt_device_hwtimer_register(&ra_hwtimer_obj[i].tmr_device, ra_hwtimer_obj[i].name, &ra_hwtimer_obj[i]) == RT_EOK)
+        {
+            LOG_D("%s register success", ra_hwtimer_obj[i].name);
+        }
+        else
+        {
+            LOG_E("%s register failed", ra_hwtimer_obj[i].name);
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
+
+/* This is a hwtimer example */
+#define HWTIMER_DEV_NAME "timer0" /* device name */
+
+static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("this is hwtimer timeout callback fucntion!\n");
+    rt_kprintf("tick is :%d !\n", rt_tick_get());
+
+    return RT_EOK;
+}
+
+int hwtimer_sample(void)
+{
+    rt_err_t ret = RT_EOK;
+    rt_hwtimerval_t timeout_s;
+    rt_device_t hw_dev = RT_NULL;
+    rt_hwtimer_mode_t mode;
+    rt_uint32_t freq = 1875000; /* 1Mhz */
+
+    hw_dev = rt_device_find(HWTIMER_DEV_NAME);
+    if (hw_dev == RT_NULL)
+    {
+        rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
+        return -RT_ERROR;
+    }
+
+    ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
+        return ret;
+    }
+
+    rt_device_set_rx_indicate(hw_dev, timeout_cb);
+
+    rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq);
+
+    mode = HWTIMER_MODE_PERIOD;
+    ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set mode failed! ret is :%d\n", ret);
+        return ret;
+    }
+
+    /* Example Set the timeout period of the timer */
+    timeout_s.sec = 1;  /* secend */
+    timeout_s.usec = 0; /* microsecend */
+    if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
+    {
+        rt_kprintf("set timeout value failed\n");
+        return -RT_ERROR;
+    }
+
+    /* read hwtimer value */
+    rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
+
+    return ret;
+}
+MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
+
+#endif /* BSP_USING_HWTIMER */
diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.h b/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.h
new file mode 100644
index 0000000000..35347d4add
--- /dev/null
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_hwtimer.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-09-04     Rbb666       first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include <rtthread.h>
+#include <drivers/hwtimer.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+struct ra_hwtimer
+{
+    rt_hwtimer_t                    tmr_device;
+    gpt_instance_ctrl_t             *g_ctrl;
+    timer_instance_t const *const   g_timer;
+    timer_cfg_t const *const        g_cfg;
+    char                            *name;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TMR_CONFIG_H__ */
diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c b/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c
index 6eb1a9bdae..2815b216b6 100644
--- a/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -59,10 +59,10 @@ static time_t get_rtc_timestamp(void)
     return timegm(&tm_new);
 }
 
-static rt_err_t ra_get_secs(void *args)
+static rt_err_t ra_get_secs(time_t *sec)
 {
-    *(rt_uint32_t *)args = get_rtc_timestamp();
-    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+    *(rt_uint32_t *)sec = get_rtc_timestamp();
+    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)sec);
 
     return RT_EOK;
 }
@@ -95,25 +95,25 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
     return RT_EOK;
 }
 
-static rt_err_t ra_set_secs(void *args)
+static rt_err_t ra_set_secs(time_t *sec)
 {
 
     rt_err_t result = RT_EOK;
 
-    if (set_rtc_time_stamp(*(rt_uint32_t *)args))
+    if (set_rtc_time_stamp(*(rt_uint32_t *)sec))
     {
         result = -RT_ERROR;
     }
-    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)sec);
 
     return result;
 }
 
 #ifdef RT_USING_ALARM
-static rt_err_t ra_get_alarm(void *arg)
+static rt_err_t ra_get_alarm(struct rt_rtc_wkalarm *alarm)
 {
     rt_err_t result = RT_EOK;
-    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    struct rt_rtc_wkalarm *wkalarm = alarm;
     rtc_alarm_time_t alarm_time_get =
     {
         .sec_match        =  RT_FALSE,
@@ -139,10 +139,10 @@ static rt_err_t ra_get_alarm(void *arg)
     return result;
 }
 
-static rt_err_t ra_set_alarm(void *arg)
+static rt_err_t ra_set_alarm(struct rt_rtc_wkalarm *alarm)
 {
     rt_err_t result = RT_EOK;
-    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    struct rt_rtc_wkalarm *wkalarm = alarm;
     rtc_alarm_time_t alarm_time_set =
     {
         .sec_match        =  RT_TRUE,
diff --git a/bsp/renesas/ra6m3-ek/board/Kconfig b/bsp/renesas/ra6m3-ek/board/Kconfig
index 73260afcde..293f0cf1aa 100644
--- a/bsp/renesas/ra6m3-ek/board/Kconfig
+++ b/bsp/renesas/ra6m3-ek/board/Kconfig
@@ -50,6 +50,38 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                config BSP_USING_HW_I2C
+                    bool "Enable Hardware I2C BUS"
+                    default n
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C0
+                        bool "Enable Hardware I2C0 BUS"
+                        default n
+                endif
+                if !BSP_USING_HW_I2C
+                    menuconfig BSP_USING_I2C1
+                        bool "Enable I2C1 BUS (software simulation)"
+                        default y
+                        if BSP_USING_I2C1
+                            config BSP_I2C1_SCL_PIN
+                                hex "i2c1 scl pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050C
+                            config BSP_I2C1_SDA_PIN
+                                hex "I2C1 sda pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050B
+                        endif
+                endif
+            endif
+
         menuconfig BSP_USING_FS
             bool "Enable File System"
             select RT_USING_DFS
@@ -75,6 +107,19 @@ menu "Hardware Drivers Config"
                     default n
             endif
 
+        menuconfig BSP_USING_TIM
+        bool "Enable timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM0
+                bool "Enable TIM0"
+                default n
+            config BSP_USING_TIM1
+                bool "Enable TIM1"
+                default n
+        endif
+
         config BSP_USING_LCD
             bool "Enable LCD"
             select BSP_USING_GPIO