diff options
| author | Bernard Xiong <[email protected]> | 2020-09-19 22:11:30 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-09-19 22:11:30 +0800 |
| commit | 8302a7224302c0624b9918855a25e12f3a3ede59 (patch) | |
| tree | 0849035b8d568b4fab4068070b7818e528cf88fc | |
| parent | 8afb8b1e294883f50bc17a67cfa4321e61140681 (diff) | |
| parent | ab78ea1de1ce3841a36e4b2b08ce938c1a6fc4f8 (diff) | |
Merge pull request #3913 from Michael0066/master
MIPS:fix the RT_EXCEPTION_MAX value
| -rw-r--r-- | bsp/ls2kdev/drivers/board.c | 10 | ||||
| -rw-r--r-- | bsp/ls2kdev/drivers/ls2k1000.h | 23 | ||||
| -rw-r--r-- | libcpu/mips/common/exception.c | 2 |
3 files changed, 34 insertions, 1 deletions
diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c index 6a66777121..30fb59091a 100644 --- a/bsp/ls2kdev/drivers/board.c +++ b/bsp/ls2kdev/drivers/board.c @@ -16,15 +16,22 @@ #include "exception.h" #include "drv_uart.h" #include "board.h" +#include "ls2k1000.h" + /** * this function will reset CPU * */ void rt_hw_cpu_reset(void) { + WDT_EN = 0x01; + WDT_TIMER = 0x01; + WDT_SET = 0x01; rt_kprintf("reboot system...\n"); while (1); } +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset cpu); + /** * this function will shutdown CPU @@ -32,10 +39,13 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown(void) { + PM1_STS &= 0xffffffff; + PM1_CNT = 0x3c00; rt_kprintf("shutdown...\n"); while (1); } +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, poweroff, shutdown cpu); /** diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h index 38e83875fb..668d484d9c 100644 --- a/bsp/ls2kdev/drivers/ls2k1000.h +++ b/bsp/ls2kdev/drivers/ls2k1000.h @@ -3,6 +3,7 @@ #include <mips.h> #include "interrupt.h" +#include <rthw.h> #define APB_BASE CKSEG1ADDR(0xbfe00000) @@ -24,6 +25,28 @@ #define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420) + +/* + * General PM Configuration Register + */ +#define PMCON_BASE (APB_BASE | (0x7 << 12)) + +/* + * Power Management1 Configuration Registers + */ +#define PM1_BASE (PMCON_BASE + 0x0C) +#define PM1_STS HWREG32(PM1_BASE) +#define PM1_EN HWREG32(PM1_BASE + 0x04) +#define PM1_CNT HWREG32(PM1_BASE + 0x08) + +/* + * Watch Dog Configuration Registers + */ +#define WDT_BASE (PMCON_BASE + 0x30) +#define WDT_EN HWREG32(WDT_BASE) +#define WDT_SET HWREG32(WDT_BASE + 0x04) +#define WDT_TIMER HWREG32(WDT_BASE + 0x08) + void rt_hw_timer_handler(void); void rt_hw_uart_init(void); diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 94be475878..3da8ecead6 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -74,7 +74,7 @@ void rt_hw_interrupt_enable(rt_base_t level) /** * exception handle table */ -#define RT_EXCEPTION_MAX 31 +#define RT_EXCEPTION_MAX 32 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** |