[libcpu][arm][cortex-m4] allows rewrite to interrupt enable/disable api to support independent interrupts management

3 files changed, 23 insertions, 4 deletions

diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 5088e403ed..908c95786d 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -10,6 +10,7 @@
  * 2013-06-18     aozima       add restore MSP feature.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
  */
 
 /**
@@ -32,6 +33,7 @@
  * rt_base_t rt_hw_interrupt_disable();
  */
 .global rt_hw_interrupt_disable
+.weak rt_hw_interrupt_disable
 .type rt_hw_interrupt_disable, %function
 rt_hw_interrupt_disable:
     MRS     r0, PRIMASK
@@ -42,6 +44,7 @@ rt_hw_interrupt_disable:
  * void rt_hw_interrupt_enable(rt_base_t level);
  */
 .global rt_hw_interrupt_enable
+.weak rt_hw_interrupt_enable
 .type rt_hw_interrupt_enable, %function
 rt_hw_interrupt_enable:
     MSR     PRIMASK, r0
@@ -208,6 +211,10 @@ rt_hw_context_switch_to:
     CPSIE   F
     CPSIE   I
 
+    /* clear the BASEPRI register to disable masking priority */
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
     /* ensure PendSV exception taken place before subsequent operation */
     DSB
     ISB
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index 30be2b7202..fc87c82aa5 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -11,6 +11,7 @@
 ; * 2013-06-18     aozima       add restore MSP feature.
 ; * 2013-06-23     aozima       support lazy stack optimized.
 ; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
 ; */
 
 ;/**
@@ -36,7 +37,8 @@ NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV excep
 ;/*
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */
-    EXPORT rt_hw_interrupt_disable
+    PUBWEAK rt_hw_interrupt_disable
+    SECTION .text:CODE:REORDER:NOROOT(2)
 rt_hw_interrupt_disable:
     MRS     r0, PRIMASK
     CPSID   I
@@ -45,7 +47,8 @@ rt_hw_interrupt_disable:
 ;/*
 ; * void rt_hw_interrupt_enable(rt_base_t level);
 ; */
-    EXPORT  rt_hw_interrupt_enable
+    PUBWEAK  rt_hw_interrupt_enable
+    SECTION .text:CODE:REORDER:NOROOT(2)
 rt_hw_interrupt_enable:
     MSR     PRIMASK, r0
     BX      LR
@@ -208,6 +211,10 @@ rt_hw_context_switch_to:
     CPSIE   F
     CPSIE   I
 
+    ; clear the BASEPRI register to disable masking priority
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
     ; ensure PendSV exception taken place before subsequent operation
     DSB
     ISB
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index 018e4251c9..3f6e2e83d6 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -10,6 +10,7 @@
 ; * 2013-06-18     aozima       add restore MSP feature.
 ; * 2013-06-23     aozima       support lazy stack optimized.
 ; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
 ; */
 
 ;/**
@@ -36,7 +37,7 @@ NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV excep
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */
 rt_hw_interrupt_disable    PROC
-    EXPORT  rt_hw_interrupt_disable
+    EXPORT  rt_hw_interrupt_disable [WEAK]
     MRS     r0, PRIMASK
     CPSID   I
     BX      LR
@@ -46,7 +47,7 @@ rt_hw_interrupt_disable    PROC
 ; * void rt_hw_interrupt_enable(rt_base_t level);
 ; */
 rt_hw_interrupt_enable    PROC
-    EXPORT  rt_hw_interrupt_enable
+    EXPORT  rt_hw_interrupt_enable [WEAK]
     MSR     PRIMASK, r0
     BX      LR
     ENDP
@@ -208,6 +209,10 @@ rt_hw_context_switch_to    PROC
     CPSIE   F
     CPSIE   I
 
+    ; clear the BASEPRI register to disable masking priority
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
     ; ensure PendSV exception taken place before subsequent operation
     DSB
     ISB