diff options
| author | rtthread-bot <[email protected]> | 2021-12-08 06:12:14 +0000 |
|---|---|---|
| committer | rtthread-bot <[email protected]> | 2021-12-08 06:12:14 +0000 |
| commit | 9bbb74affc4e399ce48a7e3d6b093ce22823c3aa (patch) | |
| tree | de37bc9e8b300c3ebd55f97a7f02bd1d2d7bddaa | |
| parent | fd9eea2f7ff88862d61687e0376ad8b884693db9 (diff) | |
| parent | 88137fbc910fd3f478e5050448184458461603d8 (diff) | |
Merge remote-tracking branch 'rtt_gitee/gitee_master'
| -rw-r--r-- | bsp/stm32/libraries/HAL_Drivers/drv_can.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c index 89892da09e..7d35ee1096 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c @@ -12,6 +12,8 @@ * 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode). * 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3. * 2021-02-02 YuZhe XU fix bug in filter config + * 2021-8-25 SVCHAO The baud rate is configured according to the different APB1 frequencies. + f4-series only. */ #include "drv_can.h" @@ -34,7 +36,22 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] = {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 150)}, {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 300)} }; -#elif defined (SOC_SERIES_STM32F4)/* APB1 45MHz(max) */ +#elif defined (SOC_SERIES_STM32F4) /* 42MHz or 45MHz */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) /* 42MHz(max) */ +static const struct stm32_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_4TQ | 3)}, + {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_5TQ | 4)}, + {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 6)}, + {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 12)}, + {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 24)}, + {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 30)}, + {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 60)}, + {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)}, + {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)} +}; +#else /* APB1 45MHz(max) */ static const struct stm32_baud_rate_tab can_baud_rate_tab[] = { {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 3)}, @@ -47,6 +64,7 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] = {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)}, {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)} }; +#endif #elif defined (SOC_SERIES_STM32F7)/* APB1 54MHz(max) */ static const struct stm32_baud_rate_tab can_baud_rate_tab[] = { |