Merge pull request #5271 from Lim-LinYuanbo/master

完善驱动

8 files changed, 393 insertions, 183 deletions

diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c
index 637562bf3b..cba0b38768 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c
@@ -8,6 +8,7 @@
  * 2021-08-20     breo.com     first version
  */
 
+#include <stddef.h>
 #include <board.h>
 #include <rtthread.h>
 
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
index fbdb40634e..1e1b51c342 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
@@ -5,51 +5,94 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-1-13      Leo         first version
+ * 2021-11-11     breo.com     first version
  */
 
 #include <board.h>
 #include "drv_pwm.h"
 
 #ifdef RT_USING_PWM
-    #if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
-        !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4)
+    #if !defined(BSP_USING_TIM1_CH1) && !defined(BSP_USING_TIM1_CH2) && \
+        !defined(BSP_USING_TIM1_CH3) && !defined(BSP_USING_TIM1_CH4) && \
+        !defined(BSP_USING_TIM2_CH1) && !defined(BSP_USING_TIM2_CH2) && \
+        !defined(BSP_USING_TIM2_CH3) && !defined(BSP_USING_TIM2_CH4) && \
+        !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
+        !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) && \
+        !defined(BSP_USING_TIM4_CH1) && !defined(BSP_USING_TIM4_CH2) && \
+        !defined(BSP_USING_TIM4_CH3) && !defined(BSP_USING_TIM4_CH4) && \
+        !defined(BSP_USING_TIM5_CH1) && !defined(BSP_USING_TIM5_CH2) && \
+        !defined(BSP_USING_TIM5_CH3) && !defined(BSP_USING_TIM5_CH4) && \
+        !defined(BSP_USING_TIM8_CH1) && !defined(BSP_USING_TIM8_CH2) && \
+        !defined(BSP_USING_TIM8_CH3) && !defined(BSP_USING_TIM8_CH4)
         #error "Please define at least one BSP_USING_TIMx_CHx"
     #endif
 #endif /* RT_USING_PWM */
 
-#define DRV_DEBUG
-#define LOG_TAG             "drv.pwm"
-#include <drv_log.h>
-
 #define MAX_PERIOD 65535
-struct rt_device_pwm pwm_device;
+
+#ifdef BSP_USING_PWM
 
 struct n32_pwm
 {
-    struct rt_device_pwm pwm_device;
     TIM_Module *tim_handle;
-    rt_uint8_t channel;
-    char *name;
+    const char *name;
+    struct rt_device_pwm pwm_device;
+    int8_t tim_en;
+    uint8_t ch_en;
+    uint32_t period;
+    uint32_t psc;
 };
 
 static struct n32_pwm n32_pwm_obj[] =
 {
-#ifdef BSP_USING_TIM3_CH1
-    PWM1_TIM3_CONFIG,
+#if defined(BSP_USING_TIM1_CH1) || defined(BSP_USING_TIM1_CH2) || \
+        defined(BSP_USING_TIM1_CH3) || defined(BSP_USING_TIM1_CH4)
+    {
+        .tim_handle = TIM1,
+        .name = "tim1pwm",
+    },
 #endif
 
-#ifdef BSP_USING_TIM3_CH2
-    PWM2_TIM3_CONFIG,
+#if defined(BSP_USING_TIM2_CH1) || defined(BSP_USING_TIM2_CH2) || \
+        defined(BSP_USING_TIM2_CH3) || defined(BSP_USING_TIM2_CH4)
+    {
+        .tim_handle = TIM2,
+        .name = "tim2pwm",
+    },
 #endif
 
-#ifdef BSP_USING_TIM3_CH3
-    PWM3_TIM3_CONFIG,
+#if defined(BSP_USING_TIM3_CH1) || defined(BSP_USING_TIM3_CH2) || \
+        defined(BSP_USING_TIM3_CH3) || defined(BSP_USING_TIM3_CH4)
+    {
+        .tim_handle = TIM3,
+        .name = "tim3pwm",
+    },
 #endif
 
-#ifdef BSP_USING_TIM3_CH4
-    PWM4_TIM3_CONFIG,
+#if defined(BSP_USING_TIM4_CH1) || defined(BSP_USING_TIM4_CH2) || \
+        defined(BSP_USING_TIM4_CH3) || defined(BSP_USING_TIM4_CH4)
+    {
+        .tim_handle = TIM4,
+        .name = "tim4pwm",
+    },
+#endif
+
+#if defined(BSP_USING_TIM5_CH1) || defined(BSP_USING_TIM5_CH2) || \
+        defined(BSP_USING_TIM5_CH3) || defined(BSP_USING_TIM5_CH4)
+    {
+        .tim_handle = TIM5,
+        .name = "tim5pwm",
+    },
+#endif
+
+#if defined(BSP_USING_TIM8_CH1) || defined(BSP_USING_TIM8_CH2) || \
+        defined(BSP_USING_TIM8_CH3) || defined(BSP_USING_TIM8_CH4)
+    {
+        .tim_handle = TIM8,
+        .name = "tim8pwm",
+    }
 #endif
+
 };
 
 static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
@@ -58,61 +101,81 @@ static struct rt_pwm_ops drv_ops =
     drv_pwm_control
 };
 
-static rt_err_t drv_pwm_enable(TIM_Module *TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+static rt_err_t drv_pwm_enable(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration, rt_bool_t enable)
 {
     /* Get the value of channel */
     rt_uint32_t channel = configuration->channel;
+    TIM_Module *TIMx = pwm_dev->tim_handle;
+
+    if (enable)
+    {
+        pwm_dev->ch_en |= 0x1 << channel;
+    }
+    else
+    {
+        pwm_dev->ch_en &= ~(0x1 << channel);
+    }
 
-    if (!enable)
+    if (enable)
     {
         if (channel == 1)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
         }
         else if (channel == 2)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
         }
         else if (channel == 3)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
         }
         else if (channel == 4)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
         }
     }
     else
     {
         if (channel == 1)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
         }
         else if (channel == 2)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
         }
         else if (channel == 3)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
         }
         else if (channel == 4)
         {
-            TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
         }
     }
 
-    TIM_Enable(TIMx, ENABLE);
+    if (pwm_dev->ch_en)
+    {
+        pwm_dev->tim_en = 0x1;
+        TIM_Enable(TIMx, ENABLE);
+    }
+    else
+    {
+        pwm_dev->tim_en = 0x0;
+        TIM_Enable(TIMx, DISABLE);
+    }
 
     return RT_EOK;
 }
 
-static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
+static rt_err_t drv_pwm_get(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
 {
     RCC_ClocksType  RCC_Clockstruct;
     rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
-    rt_uint32_t channel = configuration->channel;
     rt_uint64_t tim_clock;
+    rt_uint32_t channel = configuration->channel;
+    TIM_Module *TIMx = pwm_dev->tim_handle;
 
     ar   = TIMx->AR;
     div  = TIMx->PSC;
@@ -140,9 +203,13 @@ static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *confi
     return RT_EOK;
 }
 
-static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
+static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
 {
+    TIM_Module *TIMx = pwm_dev->tim_handle;
+    rt_uint32_t channel = configuration->channel;
+
     /* Init timer pin and enable clock */
+    void n32_msp_tim_init(void *Instance);
     n32_msp_tim_init(TIMx);
 
     RCC_ClocksType RCC_Clock;
@@ -167,14 +234,17 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
     period = period / psc;
     psc = psc * (input_clock / 1000000);
 
-    /* TIMe base configuration */
-    TIM_TimeBaseInitType TIM_TIMeBaseStructure;
-    TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
-    TIM_TIMeBaseStructure.Period = period;
-    TIM_TIMeBaseStructure.Prescaler = psc - 1;
-    TIM_TIMeBaseStructure.ClkDiv = 0;
-    TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
-    TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
+    if ((pwm_dev->period != period) || (pwm_dev->psc != psc))
+    {
+        /* TIMe base configuration */
+        TIM_TimeBaseInitType TIM_TIMeBaseStructure;
+        TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
+        TIM_TIMeBaseStructure.Period = period;
+        TIM_TIMeBaseStructure.Prescaler = psc - 1;
+        TIM_TIMeBaseStructure.ClkDiv = 0;
+        TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
+        TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
+    }
 
     rt_uint32_t pulse = (unsigned long long)configuration->pulse;
     /* PWM1 Mode configuration: Channel1 */
@@ -185,26 +255,33 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
     TIM_OCInitStructure.Pulse = pulse;
     TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
 
-    rt_uint32_t channel = configuration->channel;
     if (channel == 1)
     {
         TIM_InitOc1(TIMx, &TIM_OCInitStructure);
         TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
+        if (!(pwm_dev->ch_en & (0x1 << channel)))
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
     }
     else if (channel == 2)
     {
         TIM_InitOc2(TIMx, &TIM_OCInitStructure);
         TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
+        if (!(pwm_dev->ch_en & (0x1 << channel)))
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
     }
     else if (channel == 3)
     {
         TIM_InitOc3(TIMx, &TIM_OCInitStructure);
         TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
+        if (!(pwm_dev->ch_en & (0x1 << channel)))
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
     }
     else if (channel == 4)
     {
         TIM_InitOc4(TIMx, &TIM_OCInitStructure);
         TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
+        if (!(pwm_dev->ch_en & (0x1 << channel)))
+            TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
     }
 
     TIM_ConfigArPreload(TIMx, ENABLE);
@@ -216,18 +293,18 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
 static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
 {
     struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
-    TIM_Module *TIMx = (TIM_Module *)device->parent.user_data;
+    struct n32_pwm *pwm_dev = (struct n32_pwm *)(device->parent.user_data);
 
     switch (cmd)
     {
     case PWM_CMD_ENABLE:
-        return drv_pwm_enable(TIMx, configuration, RT_TRUE);
+        return drv_pwm_enable(pwm_dev, configuration, RT_TRUE);
     case PWM_CMD_DISABLE:
-        return drv_pwm_enable(TIMx, configuration, RT_FALSE);
+        return drv_pwm_enable(pwm_dev, configuration, RT_FALSE);
     case PWM_CMD_SET:
-        return drv_pwm_set(TIMx, configuration);
+        return drv_pwm_set(pwm_dev, configuration);
     case PWM_CMD_GET:
-        return drv_pwm_get(TIMx, configuration);
+        return drv_pwm_get(pwm_dev, configuration);
     default:
         return RT_EINVAL;
     }
@@ -240,13 +317,12 @@ static int rt_hw_pwm_init(void)
 
     for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
     {
-        if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
+        if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device,
+                                   n32_pwm_obj[i].name, &drv_ops, &(n32_pwm_obj[i])) == RT_EOK)
         {
-            LOG_D("%s register success", n32_pwm_obj[i].name);
         }
         else
         {
-            LOG_D("%s register failed", n32_pwm_obj[i].name);
             result = -RT_ERROR;
         }
     }
@@ -254,3 +330,6 @@ static int rt_hw_pwm_init(void)
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pwm_init);
+
+#endif
+
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h
index 489b37166f..dc05465d89 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h
@@ -18,50 +18,6 @@
 extern "C" {
 #endif
 
-#ifdef BSP_USING_TIM3_CH1
-#ifndef PWM1_TIM3_CONFIG
-#define PWM1_TIM3_CONFIG         \
-    {                              \
-        .tim_handle   = TIM3,        \
-        .name         = "tim3pwm1",  \
-        .channel      = 1            \
-    }
-#endif /* PWM1_TIM3_CONFIG */
-#endif /* BSP_USING_TIM3_CH1 */
-
-#ifdef BSP_USING_TIM3_CH2
-#ifndef PWM2_TIM3_CONFIG
-#define PWM2_TIM3_CONFIG         \
-    {                              \
-        .tim_handle   = TIM3,        \
-        .name         = "tim3pwm2",  \
-        .channel      = 2            \
-    }
-#endif /* PWM2_TIM3_CONFIG */
-#endif /* BSP_USING_TIM3_CH2 */
-
-#ifdef BSP_USING_TIM3_CH3
-#ifndef PWM3_TIM3_CONFIG
-#define PWM3_TIM3_CONFIG         \
-    {                              \
-        .tim_handle   = TIM3,        \
-        .name         = "tim3pwm3",  \
-        .channel      = 3            \
-    }
-#endif /* PWM3_TIM3_CONFIG */
-#endif /* BSP_USING_TIM3_CH3 */
-
-#ifdef BSP_USING_TIM3_CH4
-#ifndef PWM4_TIM3_CONFIG
-#define PWM4_TIM3_CONFIG             \
-    {                              \
-        .tim_handle   = TIM3,        \
-        .name         = "tim3pwm4",  \
-        .channel      = 4            \
-    }
-#endif /* PWM4_TIM3_CONFIG */
-#endif /* BSP_USING_TIM3_CH4 */
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_wdt.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_wdt.c
new file mode 100644
index 0000000000..31f921db0a
--- /dev/null
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_wdt.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-01-22     shelton           first version
+ * 2021-11-10     breo.com          porting to n32
+ */
+
+#include <board.h>
+#include <drivers/watchdog.h>
+
+#ifdef RT_USING_WDT
+#ifdef BSP_USING_WDT
+
+#define LSI_VALUE 40000
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.wdt"
+#include <drv_log.h>
+
+struct n32_wdt_obj
+{
+    IWDG_Module *instance;
+    rt_uint32_t Prescaler;
+    rt_uint32_t Reload;
+    rt_uint16_t is_start;
+};
+static struct n32_wdt_obj n32_wdt;
+static struct rt_watchdog_ops ops;
+static rt_watchdog_t watchdog;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    switch (cmd)
+    {
+    /* feed the watchdog */
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        IWDG_ReloadKey();
+        break;
+    /* set watchdog timeout */
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+#if defined(LSI_VALUE)
+        if (LSI_VALUE)
+        {
+            n32_wdt.Reload = (*((rt_uint32_t *)arg)) * LSI_VALUE / 256 ;
+        }
+        else
+        {
+            LOG_E("Please define the value of LSI_VALUE!");
+        }
+        if (n32_wdt.Reload > 0xFFF)
+        {
+            LOG_E("wdg set timeout parameter too large, please less than %ds", 0xFFF * 256 / LSI_VALUE);
+            return -RT_EINVAL;
+        }
+#else
+#error "Please define the value of LSI_VALUE!"
+#endif
+        if (n32_wdt.is_start)
+        {
+            IWDG_WriteConfig(IWDG_WRITE_ENABLE);
+            IWDG_SetPrescalerDiv(n32_wdt.Prescaler);
+            IWDG_CntReload(n32_wdt.Reload);
+            IWDG_WriteConfig(IWDG_WRITE_DISABLE);
+            IWDG_Enable();
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+#if defined(LSI_VALUE)
+        if (LSI_VALUE)
+        {
+            (*((rt_uint32_t *)arg)) = n32_wdt.Reload * 256 / LSI_VALUE;
+        }
+        else
+        {
+            LOG_E("Please define the value of LSI_VALUE!");
+        }
+#else
+#error "Please define the value of LSI_VALUE!"
+#endif
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        IWDG_WriteConfig(IWDG_WRITE_ENABLE);
+        IWDG_SetPrescalerDiv(n32_wdt.Prescaler);
+        IWDG_CntReload(n32_wdt.Reload);
+        IWDG_WriteConfig(IWDG_WRITE_DISABLE);
+        IWDG_Enable();
+        n32_wdt.is_start = 1;
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int rt_hw_wdt_init(void)
+{
+    n32_wdt.instance = IWDG;
+    n32_wdt.Prescaler = IWDG_PRESCALER_DIV256;
+    n32_wdt.Reload = 0x00000FFF;
+    n32_wdt.is_start = 0;
+
+    ops.init = &wdt_init;
+    ops.control = &wdt_control;
+    watchdog.ops = &ops;
+    /* register watchdog device */
+    if (rt_hw_watchdog_register(&watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_wdt_init);
+
+#endif /* BSP_USING_WDT */
+#endif /* RT_USING_WDT */
+
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/.config b/bsp/n32g452xx/n32g452xx-mini-system/.config
index 3ef47e09fc..0ce771a4bc 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/.config
+++ b/bsp/n32g452xx/n32g452xx-mini-system/.config
@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_BIG_ENDIAN is not set
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
@@ -142,7 +143,7 @@ CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
+CONFIG_RT_USING_WDT=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
@@ -154,6 +155,7 @@ CONFIG_RT_USING_PWM=y
 #
 # Using USB
 #
+# CONFIG_RT_USING_USB is not set
 # CONFIG_RT_USING_USB_HOST is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
 
@@ -161,10 +163,11 @@ CONFIG_RT_USING_PWM=y
 # POSIX layer and C standard library
 #
 CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
 CONFIG_RT_LIBC_USING_TIME=y
+# CONFIG_RT_LIBC_USING_FILEIO is not set
 # CONFIG_RT_USING_MODULE is not set
 CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# CONFIG_RT_USING_PTHREADS is not set
 
 #
 # Network
@@ -201,6 +204,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
 # CONFIG_RT_USING_RT_LINK is not set
 
 #
@@ -297,10 +301,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
-# CONFIG_PKG_USING_LORA_PKT_FWD is not set
-# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
-# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
-# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -334,13 +334,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_NUEMWIN is not set
 # CONFIG_PKG_USING_MP3PLAYER is not set
 # CONFIG_PKG_USING_TINYJPEG is not set
-# CONFIG_PKG_USING_UGUI is not set
-
-#
-# U8G2: a monochrome graphic library
-#
-# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
-# CONFIG_PKG_USING_U8G2 is not set
 
 #
 # tools packages
@@ -449,6 +442,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -510,8 +504,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MCP23008 is not set
 # CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
-# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
-# CONFIG_PKG_USING_BL_MCU_SDK is not set
 
 #
 # AI packages
@@ -594,16 +586,12 @@ CONFIG_SOC_N32G452XX=y
 #
 CONFIG_RT_USING_GPIO=y
 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_WDT is not set
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
-CONFIG_BSP_USING_PWM=y
-CONFIG_BSP_USING_TIM3=y
-CONFIG_BSP_USING_TIM3_CH1=y
-CONFIG_BSP_USING_TIM3_CH2=y
-CONFIG_BSP_USING_TIM3_CH3=y
-CONFIG_BSP_USING_TIM3_CH4=y
+# CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_HWTIMER is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_I2C1 is not set
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
index 1d02d7e97e..fd68886a07 100755
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
@@ -26,7 +26,12 @@ menu "On-chip Peripheral Drivers"
 
     config BSP_USING_ON_CHIP_FLASH
         bool "Enable on-chip FLASH"
-        default n 
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
 
     menuconfig BSP_USING_UART
         bool "Enable UART"
@@ -51,10 +56,44 @@ menu "On-chip Peripheral Drivers"
         default n
         select RT_USING_PWM
         if BSP_USING_PWM
-        menuconfig BSP_USING_TIM3
+        menuconfig BSP_USING_TIM1PWM
+            bool "Enable timer1 output PWM"
+            default n
+            if BSP_USING_TIM1PWM
+                config BSP_USING_TIM1_CH1
+                    bool "Enable TIM1 channel1 PWM"
+                    default n
+                config BSP_USING_TIM1_CH2
+                    bool "Enable TIM1 channel2 PWM"
+                    default n
+                config BSP_USING_TIM1_CH3
+                    bool "Enable TIM1 channel3 PWM"
+                    default n
+                config BSP_USING_TIM1_CH4
+                    bool "Enable TIM1 channel4 PWM"
+                    default n
+            endif
+        menuconfig BSP_USING_TIM2PWM
+            bool "Enable timer2 output PWM"
+            default n
+            if BSP_USING_TIM2PWM
+                config BSP_USING_TIM2_CH1
+                    bool "Enable TIM2 channel1 PWM"
+                    default n
+                config BSP_USING_TIM2_CH2
+                    bool "Enable TIM2 channel2 PWM"
+                    default n
+                config BSP_USING_TIM2_CH3
+                    bool "Enable TIM2 channel3 PWM"
+                    default n
+                config BSP_USING_TIM2_CH4
+                    bool "Enable TIM2 channel4 PWM"
+                    default n
+            endif
+        menuconfig BSP_USING_TIM3PWM
             bool "Enable timer3 output PWM"
             default n
-            if BSP_USING_TIM3
+            if BSP_USING_TIM3PWM
                 config BSP_USING_TIM3_CH1
                     bool "Enable TIM3 channel1 PWM"
                     default n
@@ -68,6 +107,57 @@ menu "On-chip Peripheral Drivers"
                     bool "Enable TIM3 channel4 PWM"
                     default n
             endif
+        menuconfig BSP_USING_TIM4PWM
+            bool "Enable timer4 output PWM"
+            default n
+            if BSP_USING_TIM4PWM
+                config BSP_USING_TIM4_CH1
+                    bool "Enable TIM4 channel1 PWM"
+                    default n
+                config BSP_USING_TIM4_CH2
+                    bool "Enable TIM4 channel2 PWM"
+                    default n
+                config BSP_USING_TIM4_CH3
+                    bool "Enable TIM4 channel3 PWM"
+                    default n
+                config BSP_USING_TIM4_CH4
+                    bool "Enable TIM4 channel4 PWM"
+                    default n
+            endif
+        menuconfig BSP_USING_TIM5PWM
+            bool "Enable timer5 output PWM"
+            default n
+            if BSP_USING_TIM5PWM
+                config BSP_USING_TIM5_CH1
+                    bool "Enable TIM5 channel1 PWM"
+                    default n
+                config BSP_USING_TIM5_CH2
+                    bool "Enable TIM5 channel2 PWM"
+                    default n
+                config BSP_USING_TIM5_CH3
+                    bool "Enable TIM5 channel3 PWM"
+                    default n
+                config BSP_USING_TIM5_CH4
+                    bool "Enable TIM5 channel4 PWM"
+                    default n
+            endif
+        menuconfig BSP_USING_TIM8PWM
+            bool "Enable timer8 output PWM"
+            default n
+            if BSP_USING_TIM8PWM
+                config BSP_USING_TIM8_CH1
+                    bool "Enable TIM8 channel1 PWM"
+                    default n
+                config BSP_USING_TIM8_CH2
+                    bool "Enable TIM8 channel2 PWM"
+                    default n
+                config BSP_USING_TIM8_CH3
+                    bool "Enable TIM8 channel3 PWM"
+                    default n
+                config BSP_USING_TIM8_CH4
+                    bool "Enable TIM8 channel4 PWM"
+                    default n
+            endif
         endif
 
     menuconfig BSP_USING_HWTIMER
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
index 178c7d536d..f10dc4df3e 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
@@ -164,49 +164,65 @@ void n32_msp_tim_init(void *Instance)
 
     if (TIMx == TIM1)
     {
-        /* TIM1 clock enable */
         RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
-        /* GPIOA clock enable */
         RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
-
-        /* GPIOA Configuration:TIM1 Channel1 and Channel4 as alternate function push-pull */
         GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11;
         GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
         GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
         GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
     }
 
     if (TIMx == TIM2)
     {
-        /* TIM2 clock enable */
         RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE);
-        /* GPIOA clock enable */
         RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
-
-        /* GPIOA Configuration:TIM2 Channel1 and Channel2 as alternate function push-pull */
-        GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1;
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
         GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
         GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
         GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
     }
 
     if (TIMx == TIM3)
     {
-        /* TIM3 clock enable */
         RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
-        /* GPIOA clock enable */
         RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOB, ENABLE);
-
-        GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
         GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
         GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
         GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
-
         GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1;
         GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStructure);
     }
+
+    if (TIMx == TIM4)
+    {
+        RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE);
+        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9;
+        GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStructure);
+    }
+
+    if (TIMx == TIM5)
+    {
+        RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE);
+        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
+        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
+    }
+
+    if (TIMx == TIM8)
+    {
+        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM8, ENABLE);
+        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9;
+        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStructure);
+    }
 }
 #endif /* BSP_USING_PWM */
 
@@ -474,46 +490,6 @@ static int hwtimer_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
 #endif
 
-#ifdef RT_USING_PWM
-static int pwm_set_test(const char *name, int ch,
-                        rt_uint32_t period, rt_uint32_t pulse)
-{
-    struct rt_device_pwm *pwm_dev = (struct rt_device_pwm *)rt_device_find(name);
-    if (pwm_dev == RT_NULL)
-    {
-        rt_kprintf("pwm sample run failed! can't find %s device!\n", name);
-        return RT_ERROR;
-    }
-    rt_pwm_set(pwm_dev, ch, period, pulse);
-    rt_pwm_enable(pwm_dev, ch);
-    return RT_EOK;
-}
-#define PWM_TEST_NAME_CH_1 "tim3pwm1"
-#define PWM_TEST_NAME_CH_2 "tim3pwm2"
-#define PWM_TEST_NAME_CH_3 "tim3pwm3"
-#define PWM_TEST_NAME_CH_4 "tim3pwm4"
-static int pwm_led_sample(int argc, char *argv[])
-{
-    pwm_set_test(PWM_TEST_NAME_CH_1, 1, 1000, 200);
-    pwm_set_test(PWM_TEST_NAME_CH_2, 2, 1000, 400);
-    pwm_set_test(PWM_TEST_NAME_CH_3, 3, 1000, 600);
-    pwm_set_test(PWM_TEST_NAME_CH_4, 4, 1000, 700);
-    return RT_EOK;
-}
-MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
-static int pwm_led_sample_off(int argc, char *argv[])
-{
-    struct rt_device_pwm *pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_TEST_NAME_CH_1);
-    if (pwm_dev == RT_NULL)
-    {
-        rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_TEST_NAME_CH_1);
-        return RT_ERROR;
-    }
-    rt_pwm_disable(pwm_dev, 1);
-    return RT_EOK;
-}
-MSH_CMD_EXPORT(pwm_led_sample_off, pwm sample off);
-#endif
 
 #endif
 
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
index 7feb290eb2..8fbf2e7e7e 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
+++ b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
@@ -85,6 +85,7 @@
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 #define RT_USING_PWM
+#define RT_USING_WDT
 
 /* Using USB */
 
@@ -143,9 +144,6 @@
 /* multimedia packages */
 
 
-/* U8G2: a monochrome graphic library */
-
-
 /* tools packages */
 
 
@@ -182,11 +180,5 @@
 #define RT_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART1
-#define BSP_USING_PWM
-#define BSP_USING_TIM3
-#define BSP_USING_TIM3_CH1
-#define BSP_USING_TIM3_CH2
-#define BSP_USING_TIM3_CH3
-#define BSP_USING_TIM3_CH4
 
 #endif