diff options
| author | wanghongzhu <[email protected]> | 2020-11-11 09:58:20 +0800 |
|---|---|---|
| committer | wanghongzhu <[email protected]> | 2020-11-11 09:58:20 +0800 |
| commit | 111ecae6ad0483ede349483c04ffee66f2cdd2fe (patch) | |
| tree | 0a68e1f5a0ba7eb012d239552b4c0c0b7637a10f | |
| parent | 5623579f3a1740d53d2f526ffdba7ce6502ee7e9 (diff) | |
fix long call linker error with 'jal', 'j' or conditional branch instruction
| -rw-r--r-- | libcpu/risc-v/common/context_gcc.S | 4 | ||||
| -rw-r--r-- | libcpu/risc-v/k210/interrupt_gcc.S | 4 | ||||
| -rw-r--r-- | libcpu/risc-v/k210/startup_gcc.S | 7 |
3 files changed, 9 insertions, 6 deletions
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 5c9f05c4e8..96afaa4c65 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -47,7 +47,7 @@ rt_hw_context_switch_to: #ifdef RT_USING_SMP mv a0, a1 - jal rt_cpus_lock_status_restore + call rt_cpus_lock_status_restore #endif LOAD a0, 2 * REGBYTES(sp) csrw mstatus, a0 @@ -123,7 +123,7 @@ save_mpie: #ifdef RT_USING_SMP mv a0, a2 - jal rt_cpus_lock_status_restore + call rt_cpus_lock_status_restore #endif /*RT_USING_SMP*/ j rt_hw_context_switch_exit diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S index 0393ea51f8..5cfa2bb170 100644 --- a/libcpu/risc-v/k210/interrupt_gcc.S +++ b/libcpu/risc-v/k210/interrupt_gcc.S @@ -82,7 +82,7 @@ trap_entry: mv sp, s0 mv a0, s0 call rt_scheduler_do_irq_switch - j rt_hw_context_switch_exit + tail rt_hw_context_switch_exit #else @@ -106,4 +106,4 @@ trap_entry: #endif spurious_interrupt: - j rt_hw_context_switch_exit + tail rt_hw_context_switch_exit diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S index f5c0d8fa94..8df41b52c2 100644 --- a/libcpu/risc-v/k210/startup_gcc.S +++ b/libcpu/risc-v/k210/startup_gcc.S @@ -116,18 +116,21 @@ _start: /* other cpu core, jump to cpu entry directly */ bnez a0, secondary_cpu_entry - j primary_cpu_entry + tail primary_cpu_entry secondary_cpu_entry: #ifdef RT_USING_SMP la a0, secondary_boot_flag ld a0, 0(a0) li a1, 0xa55a - beq a0, a1, secondary_cpu_c_start + beq a0, a1, 1f #endif j secondary_cpu_entry #ifdef RT_USING_SMP +1: + tail secondary_cpu_c_start + .data .global secondary_boot_flag .align 3 |