[bsp][gd32103c-eval] Add hwtimer driver

9 files changed, 787 insertions, 148 deletions

diff --git a/bsp/gd32103c-eval/Kconfig b/bsp/gd32103c-eval/Kconfig
index d8bfdde174..07915b7895 100644
--- a/bsp/gd32103c-eval/Kconfig
+++ b/bsp/gd32103c-eval/Kconfig
@@ -66,5 +66,35 @@ menu "On-chip Peripheral Drivers"
                 bool "using adc1"
                 default n
         endif
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable hwtimer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_HWTIMER0
+                bool "using hwtimer0"
+                default n
+            config BSP_USING_HWTIMER1
+                bool "using hwtimer1"
+                default n
+            config BSP_USING_HWTIMER2
+                bool "using hwtimer2"
+                default n
+            config BSP_USING_HWTIMER3
+                bool "using hwtimer3"
+                default n
+            config BSP_USING_HWTIMER4
+                bool "using hwtimer4"
+                default n
+            config BSP_USING_HWTIMER5
+                bool "using hwtimer5"
+                default n
+            config BSP_USING_HWTIMER6
+                bool "using hwtimer6"
+                default n
+            config BSP_USING_HWTIMER7
+                bool "using hwtimer7"
+                default n
+        endif
 
 endmenu
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
index b54bd3601d..1dde2fb596 100644
--- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
+++ b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
@@ -173,13 +173,13 @@ typedef enum IRQn {
     CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
     CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
     EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-    TIMER1_BRK_IRQn             = 24,     /*!< TIMER1 Break Interrupt                               */
-    TIMER1_UP_IRQn              = 25,     /*!< TIMER1 Update Interrupt                              */
-    TIMER1_TRG_COM_IRQn         = 26,     /*!< TIMER1 Trigger and Commutation Interrupt             */
-    TIMER1_CC_IRQn              = 27,     /*!< TIMER1 Capture Compare Interrupt                     */
-    TIMER2_IRQn                 = 28,     /*!< TIMER2 global Interrupt                              */
-    TIMER3_IRQn                 = 29,     /*!< TIMER3 global Interrupt                              */
-    TIMER4_IRQn                 = 30,     /*!< TIMER4 global Interrupt                              */
+    TIMER0_BRK_IRQn             = 24,     /*!< TIMER0 Break Interrupt                               */
+    TIMER0_UP_IRQn              = 25,     /*!< TIMER0 Update Interrupt                              */
+    TIMER0_TRG_COM_IRQn         = 26,     /*!< TIMER0 Trigger and Commutation Interrupt             */
+    TIMER0_CC_IRQn              = 27,     /*!< TIMER0 Capture Compare Interrupt                     */
+    TIMER1_IRQn                 = 28,     /*!< TIMER1 global Interrupt                              */
+    TIMER2_IRQn                 = 29,     /*!< TIMER2 global Interrupt                              */
+    TIMER3_IRQn                 = 30,     /*!< TIMER3 global Interrupt                              */
     I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
     I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
     I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
@@ -202,13 +202,13 @@ typedef enum IRQn {
                                   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
                                   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
                                   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-                                  TIMER1_BRK_IRQn             = 24,     /*!< TIMER1 Break Interrupt                               */
-                                  TIMER1_UP_IRQn              = 25,     /*!< TIMER1 Update Interrupt                              */
-                                  TIMER1_TRG_COM_IRQn         = 26,     /*!< TIMER1 Trigger and Commutation Interrupt             */
-                                  TIMER1_CC_IRQn              = 27,     /*!< TIMER1 Capture Compare Interrupt                     */
-                                  TIMER2_IRQn                 = 28,     /*!< TIMER2 global Interrupt                              */
-                                  TIMER3_IRQn                 = 29,     /*!< TIMER3 global Interrupt                              */
-                                  TIMER4_IRQn                 = 30,     /*!< TIMER4 global Interrupt                              */
+                                  TIMER0_BRK_IRQn             = 24,     /*!< TIMER0 Break Interrupt                               */
+                                  TIMER0_UP_IRQn              = 25,     /*!< TIMER0 Update Interrupt                              */
+                                  TIMER0_TRG_COM_IRQn         = 26,     /*!< TIMER0 Trigger and Commutation Interrupt             */
+                                  TIMER0_CC_IRQn              = 27,     /*!< TIMER0 Capture Compare Interrupt                     */
+                                  TIMER1_IRQn                 = 28,     /*!< TIMER1 global Interrupt                              */
+                                  TIMER2_IRQn                 = 29,     /*!< TIMER2 global Interrupt                              */
+                                  TIMER3_IRQn                 = 30,     /*!< TIMER3 global Interrupt                              */
                                   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
                                   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
                                   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
@@ -221,19 +221,19 @@ typedef enum IRQn {
                                   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
                                   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
                                   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-                                  TIMER8_BRK_IRQn             = 43,     /*!< TIMER8 Break Interrupt                               */
-                                  TIMER8_UP_IRQn              = 44,     /*!< TIMER8 Update Interrupt                              */
-                                  TIMER8_TRG_COM_IRQn         = 45,     /*!< TIMER8 Trigger and Commutation Interrupt             */
-                                  TIMER8_CC_IRQn              = 46,     /*!< TIMER8 Capture Compare Interrupt                     */
+                                  TIMER7_BRK_IRQn             = 43,     /*!< TIMER7 Break Interrupt                               */
+                                  TIMER7_UP_IRQn              = 44,     /*!< TIMER7 Update Interrupt                              */
+                                  TIMER7_TRG_COM_IRQn         = 45,     /*!< TIMER7 Trigger and Commutation Interrupt             */
+                                  TIMER7_CC_IRQn              = 46,     /*!< TIMER7 Capture Compare Interrupt                     */
                                   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
                                   EXMC_IRQn                   = 48,     /*!< EXMC global Interrupt                                */
                                   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-                                  TIMER5_IRQn                 = 50,     /*!< TIMER5 global Interrupt                              */
+                                  TIMER4_IRQn                 = 50,     /*!< TIMER4 global Interrupt                              */
                                   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
                                   UART3_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
                                   UART4_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-                                  TIMER6_IRQn                 = 54,     /*!< TIMER6 global Interrupt                              */
-                                  TIMER7_IRQn                 = 55,     /*!< TIMER7 global Interrupt                              */
+                                  TIMER5_IRQn                 = 54,     /*!< TIMER5 global Interrupt                              */
+                                  TIMER6_IRQn                 = 55,     /*!< TIMER6 global Interrupt                              */
                                   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
                                   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
                                   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
@@ -247,13 +247,13 @@ typedef enum IRQn {
                                           CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
                                           CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
                                           EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-                                          TIMER1_BRK_TIMER9_IRQn      = 24,     /*!< TIMER1 Break Interrupt and TIMER9 global Interrupt   */
-                                          TIMER1_UP_TIMER10_IRQn      = 25,     /*!< TIMER1 Update Interrupt and TIMER10 global Interrupt */
-                                          TIMER1_TRG_COM_TIMER11_IRQn = 26,     /*!< TIMER1 Trigger and Commutation Interrupt and TIMER11 global interrupt */
-                                          TIMER1_CC_IRQn              = 27,     /*!< TIMER1 Capture Compare Interrupt                     */
-                                          TIMER2_IRQn                 = 28,     /*!< TIMER2 global Interrupt                              */
-                                          TIMER3_IRQn                 = 29,     /*!< TIMER3 global Interrupt                              */
-                                          TIMER4_IRQn                 = 30,     /*!< TIMER4 global Interrupt                              */
+                                          TIMER0_BRK_TIMER8_IRQn      = 24,     /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt   */
+                                          TIMER0_UP_TIMER9_IRQn       = 25,     /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */
+                                          TIMER0_TRG_COM_TIMER10_IRQn = 26,     /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */
+                                          TIMER0_CC_IRQn              = 27,     /*!< TIMER0 Capture Compare Interrupt                     */
+                                          TIMER1_IRQn                 = 28,     /*!< TIMER1 global Interrupt                              */
+                                          TIMER2_IRQn                 = 29,     /*!< TIMER2 global Interrupt                              */
+                                          TIMER3_IRQn                 = 30,     /*!< TIMER3 global Interrupt                              */
                                           I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
                                           I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
                                           I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
@@ -266,19 +266,19 @@ typedef enum IRQn {
                                           EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
                                           RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
                                           USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-                                          TIMER8_BRK_TIMER12_IRQn     = 43,     /*!< TIMER8 Break Interrupt and TIMER12 global Interrupt  */
-                                          TIMER8_UP_TIMER13_IRQn      = 44,     /*!< TIMER8 Update Interrupt and TIMER13 global Interrupt */
-                                          TIMER8_TRG_COM_TIMER14_IRQn = 45,     /*!< TIMER8 Trigger and Commutation Interrupt and TIMER14 global interrupt */
-                                          TIMER8_CC_IRQn              = 46,     /*!< TIMER8 Capture Compare Interrupt                     */
+                                          TIMER7_BRK_TIMER11_IRQn     = 43,     /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt  */
+                                          TIMER7_UP_TIMER12_IRQn      = 44,     /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */
+                                          TIMER7_TRG_COM_TIMER13_IRQn = 45,     /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */
+                                          TIMER7_CC_IRQn              = 46,     /*!< TIMER7 Capture Compare Interrupt                     */
                                           ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
                                           EXMC_IRQn                   = 48,     /*!< EXMC global Interrupt                                */
                                           SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-                                          TIMER5_IRQn                 = 50,     /*!< TIMER5 global Interrupt                              */
+                                          TIMER4_IRQn                 = 50,     /*!< TIMER4 global Interrupt                              */
                                           SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
                                           UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
                                           UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-                                          TIMER6_IRQn                 = 54,     /*!< TIMER6 global Interrupt                              */
-                                          TIMER7_IRQn                 = 55,     /*!< TIMER7 global Interrupt                              */
+                                          TIMER5_IRQn                 = 54,     /*!< TIMER5 global Interrupt                              */
+                                          TIMER6_IRQn                 = 55,     /*!< TIMER6 global Interrupt                              */
                                           DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
                                           DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
                                           DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
@@ -292,13 +292,13 @@ typedef enum IRQn {
                                                   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
                                                   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
                                                   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-                                                  TIMER1_BRK_TIMER9_IRQn      = 24,     /*!< TIMER1 Break Interrupt and TIMER9 global Interrupt   */
-                                                  TIMER1_UP_TIMER10_IRQn      = 25,     /*!< TIMER1 Update Interrupt and TIMER10 global Interrupt */
-                                                  TIMER1_TRG_COM_TIMER11_IRQn = 26,     /*!< TIMER1 Trigger and Commutation Interrupt and TIMER11 global interrupt */
-                                                  TIMER1_CC_IRQn              = 27,     /*!< TIMER1 Capture Compare Interrupt                     */
-                                                  TIMER2_IRQn                 = 28,     /*!< TIMER2 global Interrupt                              */
-                                                  TIMER3_IRQn                 = 29,     /*!< TIMER3 global Interrupt                              */
-                                                  TIMER4_IRQn                 = 30,     /*!< TIMER4 global Interrupt                              */
+                                                  TIMER0_BRK_TIMER8_IRQn      = 24,     /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt   */
+                                                  TIMER0_UP_TIMER9_IRQn       = 25,     /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */
+                                                  TIMER0_TRG_COM_TIMER10_IRQn = 26,     /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */
+                                                  TIMER0_CC_IRQn              = 27,     /*!< TIMER0 Capture Compare Interrupt                     */
+                                                  TIMER1_IRQn                 = 28,     /*!< TIMER1 global Interrupt                              */
+                                                  TIMER2_IRQn                 = 29,     /*!< TIMER2 global Interrupt                              */
+                                                  TIMER3_IRQn                 = 30,     /*!< TIMER3 global Interrupt                              */
                                                   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
                                                   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
                                                   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
@@ -311,18 +311,18 @@ typedef enum IRQn {
                                                   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
                                                   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
                                                   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
-                                                  TIMER8_BRK_TIMER12_IRQn     = 43,     /*!< TIMER8 Break Interrupt and TIMER12 global Interrupt  */
-                                                  TIMER8_UP_TIMER13_IRQn      = 44,     /*!< TIMER8 Update Interrupt and TIMER13 global Interrupt */
-                                                  TIMER8_TRG_COM_TIMER14_IRQn = 45,     /*!< TIMER8 Trigger and Commutation Interrupt and TIMER14 global interrupt */
-                                                  TIMER8_CC_IRQn              = 46,     /*!< TIMER8 Capture Compare Interrupt                     */
+                                                  TIMER7_BRK_TIMER11_IRQn     = 43,     /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt  */
+                                                  TIMER7_UP_TIMER12_IRQn      = 44,     /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */
+                                                  TIMER7_TRG_COM_TIMER13_IRQn = 45,     /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */
+                                                  TIMER7_CC_IRQn              = 46,     /*!< TIMER7 Capture Compare Interrupt                     */
                                                   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
                                                   EXMC_IRQn                   = 48,     /*!< EXMC global Interrupt                                */
-                                                  TIMER5_IRQn                 = 50,     /*!< TIMER5 global Interrupt                              */
+                                                  TIMER4_IRQn                 = 50,     /*!< TIMER4 global Interrupt                              */
                                                   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
                                                   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
                                                   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-                                                  TIMER6_IRQn                 = 54,     /*!< TIMER6 global Interrupt                              */
-                                                  TIMER7_IRQn                 = 55,     /*!< TIMER7 global Interrupt                              */
+                                                  TIMER5_IRQn                 = 54,     /*!< TIMER5 global Interrupt                              */
+                                                  TIMER6_IRQn                 = 55,     /*!< TIMER6 global Interrupt                              */
                                                   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
                                                   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
                                                   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
@@ -1090,15 +1090,15 @@ typedef struct {
 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
 
-#define TIMER2_BASE           (APB1PERIPH_BASE + 0x0000)
-#define TIMER3_BASE           (APB1PERIPH_BASE + 0x0400)
-#define TIMER4_BASE           (APB1PERIPH_BASE + 0x0800)
-#define TIMER5_BASE           (APB1PERIPH_BASE + 0x0C00)
-#define TIMER6_BASE           (APB1PERIPH_BASE + 0x1000)
-#define TIMER7_BASE           (APB1PERIPH_BASE + 0x1400)
-#define TIMER12_BASE          (APB1PERIPH_BASE + 0x1800)
-#define TIMER13_BASE          (APB1PERIPH_BASE + 0x1C00)
-#define TIMER14_BASE          (APB1PERIPH_BASE + 0x2000)
+#define TIMER1_BASE           (APB1PERIPH_BASE + 0x0000)
+#define TIMER2_BASE           (APB1PERIPH_BASE + 0x0400)
+#define TIMER3_BASE           (APB1PERIPH_BASE + 0x0800)
+#define TIMER4_BASE           (APB1PERIPH_BASE + 0x0C00)
+#define TIMER5_BASE           (APB1PERIPH_BASE + 0x1000)
+#define TIMER6_BASE           (APB1PERIPH_BASE + 0x1400)
+#define TIMER11_BASE          (APB1PERIPH_BASE + 0x1800)
+#define TIMER12_BASE          (APB1PERIPH_BASE + 0x1C00)
+#define TIMER13_BASE          (APB1PERIPH_BASE + 0x2000)
 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
@@ -1126,17 +1126,17 @@ typedef struct {
 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
 #define ADC0_BASE             (APB2PERIPH_BASE + 0x2400)
 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2800)
-#define TIMER1_BASE           (APB2PERIPH_BASE + 0x2C00)
+#define TIMER0_BASE           (APB2PERIPH_BASE + 0x2C00)
 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define TIMER8_BASE           (APB2PERIPH_BASE + 0x3400)
+#define TIMER7_BASE           (APB2PERIPH_BASE + 0x3400)
 #define USART0_BASE           (APB2PERIPH_BASE + 0x3800)
 #define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIMER15_BASE          (APB2PERIPH_BASE + 0x4000)
-#define TIMER16_BASE          (APB2PERIPH_BASE + 0x4400)
-#define TIMER17_BASE          (APB2PERIPH_BASE + 0x4800)
-#define TIMER9_BASE           (APB2PERIPH_BASE + 0x4C00)
-#define TIMER10_BASE          (APB2PERIPH_BASE + 0x5000)
-#define TIMER11_BASE          (APB2PERIPH_BASE + 0x5400)
+#define TIMER14_BASE          (APB2PERIPH_BASE + 0x4000)
+#define TIMER15_BASE          (APB2PERIPH_BASE + 0x4400)
+#define TIMER16_BASE          (APB2PERIPH_BASE + 0x4800)
+#define TIMER8_BASE           (APB2PERIPH_BASE + 0x4C00)
+#define TIMER9_BASE           (APB2PERIPH_BASE + 0x5000)
+#define TIMER10_BASE          (APB2PERIPH_BASE + 0x5400)
 
 #define SDIO_BASE             (PERIPH_BASE + 0x18000)
 
@@ -1183,15 +1183,15 @@ typedef struct {
   * @{
   */
 
+#define TIMER1                ((TIMER_TypeDef *) TIMER1_BASE)
 #define TIMER2                ((TIMER_TypeDef *) TIMER2_BASE)
 #define TIMER3                ((TIMER_TypeDef *) TIMER3_BASE)
 #define TIMER4                ((TIMER_TypeDef *) TIMER4_BASE)
 #define TIMER5                ((TIMER_TypeDef *) TIMER5_BASE)
 #define TIMER6                ((TIMER_TypeDef *) TIMER6_BASE)
-#define TIMER7                ((TIMER_TypeDef *) TIMER7_BASE)
+#define TIMER11               ((TIMER_TypeDef *) TIMER11_BASE)
 #define TIMER12               ((TIMER_TypeDef *) TIMER12_BASE)
 #define TIMER13               ((TIMER_TypeDef *) TIMER13_BASE)
-#define TIMER14               ((TIMER_TypeDef *) TIMER14_BASE)
 #define RTC                   ((RTC_TypeDef *) RTC_BASE)
 #define WWDG                  ((WWDG_TypeDef *) WWDG_BASE)
 #define IWDG                  ((IWDG_TypeDef *) IWDG_BASE)
@@ -1220,18 +1220,18 @@ typedef struct {
 #define GPIOG                 ((GPIO_TypeDef *) GPIOG_BASE)
 #define ADC0                  ((ADC_TypeDef *) ADC0_BASE)
 #define ADC1                  ((ADC_TypeDef *) ADC1_BASE)
-#define TIMER1                ((TIMER_TypeDef *) TIMER1_BASE)
+#define TIMER0                ((TIMER_TypeDef *) TIMER0_BASE)
 #define SPI1                  ((SPI_TypeDef *) SPI1_BASE)
-#define TIMER8                ((TIMER_TypeDef *) TIMER8_BASE)
+#define TIMER7                ((TIMER_TypeDef *) TIMER7_BASE)
 #define USART0                ((USART_TypeDef *) USART0_BASE)
 #define USART1                ((USART_TypeDef *) USART1_BASE)
 #define ADC3                  ((ADC_TypeDef *) ADC3_BASE)
+#define TIMER14               ((TIMER_TypeDef *) TIMER14_BASE)
 #define TIMER15               ((TIMER_TypeDef *) TIMER15_BASE)
 #define TIMER16               ((TIMER_TypeDef *) TIMER16_BASE)
-#define TIMER17               ((TIMER_TypeDef *) TIMER17_BASE)
+#define TIMER8                ((TIMER_TypeDef *) TIMER8_BASE)
 #define TIMER9                ((TIMER_TypeDef *) TIMER9_BASE)
 #define TIMER10               ((TIMER_TypeDef *) TIMER10_BASE)
-#define TIMER11               ((TIMER_TypeDef *) TIMER11_BASE)
 #define SDIO                  ((SDIO_TypeDef *) SDIO_BASE)
 #define DMA1                  ((DMA_TypeDef *) DMA1_BASE)
 #define DMA2                  ((DMA_TypeDef *) DMA2_BASE)
@@ -7050,26 +7050,26 @@ typedef struct {
 #define  RCC_APB2RCR_PGRST                          ((uint32_t)0x00000100)         /*!< GPIOF clock reset */
 #define  RCC_APB2RCR_ADC0RST                        ((uint32_t)0x00000200)         /*!< ADC0 clock reset */
 #define  RCC_APB2RCR_ADC1RST                        ((uint32_t)0x00000400)         /*!< ADC1 clock reset */
-#define  RCC_APB2RCR_TIMER1RST                      ((uint32_t)0x00000800)         /*!< TIMER1 clock reset */
+#define  RCC_APB2RCR_TIMER0RST                      ((uint32_t)0x00000800)         /*!< TIMER0 clock reset */
 #define  RCC_APB2RCR_SPI1RST                        ((uint32_t)0x00001000)         /*!< SPI1 clock reset */
-#define  RCC_APB2RCR_TIMER8RST                      ((uint32_t)0x00002000)         /*!< TIMER8 clock reset */
+#define  RCC_APB2RCR_TIMER7RST                      ((uint32_t)0x00002000)         /*!< TIMER7 clock reset */
 #define  RCC_APB2RCR_USART0RST                      ((uint32_t)0x00004000)         /*!< USART1 clock reset */
 #define  RCC_APB2RCR_ADC3RST                        ((uint32_t)0x00008000)         /*!< ADC3 clock reset */
-#define  RCC_APB2RCR_TIMER9RST                      ((uint32_t)0x00080000)         /*!< TIMER9 clock reset */
-#define  RCC_APB2RCR_TIMER10RST                     ((uint32_t)0x00100000)         /*!< TIMER10 clock reset */
-#define  RCC_APB2RCR_TIMER11RST                     ((uint32_t)0x00200000)         /*!< TIMER11 clock reset */
+#define  RCC_APB2RCR_TIMER8RST                      ((uint32_t)0x00080000)         /*!< TIMER8 clock reset */
+#define  RCC_APB2RCR_TIMER9RST                      ((uint32_t)0x00100000)         /*!< TIMER9 clock reset */
+#define  RCC_APB2RCR_TIMER10RST                     ((uint32_t)0x00200000)         /*!< TIMER10 clock reset */
 
 /*****************  Bit definition for RCC_APB1RCR register  *****************/
 
-#define  RCC_APB1RCR_TIMER2RST                      ((uint32_t)0x00000001)        /*!< TIMER2 clock reset */
-#define  RCC_APB1RCR_TIMER3RST                      ((uint32_t)0x00000002)        /*!< TIMER3 clock reset */
-#define  RCC_APB1RCR_TIMER4RST                      ((uint32_t)0x00000004)        /*!< TIMER4 clock reset */
-#define  RCC_APB1RCR_TIMER5RST                      ((uint32_t)0x00000008)        /*!< TIMER8 clock reset */
-#define  RCC_APB1RCR_TIMER6RST                      ((uint32_t)0x00000010)        /*!< TIMER6 clock reset */
-#define  RCC_APB1RCR_TIMER7RST                      ((uint32_t)0x00000020)        /*!< TIMER7 clock reset */
-#define  RCC_APB1RCR_TIMER12RST                     ((uint32_t)0x00000040)        /*!< TIMER12 clock reset */
-#define  RCC_APB1RCR_TIMER13RST                     ((uint32_t)0x00000080)        /*!< TIMER13 clock reset */
-#define  RCC_APB1RCR_TIMER14RST                     ((uint32_t)0x00000100)        /*!< TIMER14 clock reset */
+#define  RCC_APB1RCR_TIMER1RST                      ((uint32_t)0x00000001)        /*!< TIMER1 clock reset */
+#define  RCC_APB1RCR_TIMER2RST                      ((uint32_t)0x00000002)        /*!< TIMER2 clock reset */
+#define  RCC_APB1RCR_TIMER3RST                      ((uint32_t)0x00000004)        /*!< TIMER3 clock reset */
+#define  RCC_APB1RCR_TIMER4RST                      ((uint32_t)0x00000008)        /*!< TIMER7 clock reset */
+#define  RCC_APB1RCR_TIMER5RST                      ((uint32_t)0x00000010)        /*!< TIMER5 clock reset */
+#define  RCC_APB1RCR_TIMER6RST                      ((uint32_t)0x00000020)        /*!< TIMER6 clock reset */
+#define  RCC_APB1RCR_TIMER11RST                     ((uint32_t)0x00000040)        /*!< TIMER11 clock reset */
+#define  RCC_APB1RCR_TIMER12RST                     ((uint32_t)0x00000080)        /*!< TIMER12 clock reset */
+#define  RCC_APB1RCR_TIMER13RST                     ((uint32_t)0x00000100)        /*!< TIMER13 clock reset */
 #define  RCC_APB1RCR_WWDGRST                        ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
 #define  RCC_APB1RCR_SPI2RST                        ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
 #define  RCC_APB1RCR_SPI3RST                        ((uint32_t)0x00008000)        /*!< SPI3 clock reset */
@@ -7115,26 +7115,26 @@ typedef struct {
 #define  RCC_APB2CCR_PGEN                           ((uint32_t)0x00000100)         /*!< GPIOF clock enable */
 #define  RCC_APB2CCR_ADC0EN                         ((uint32_t)0x00000200)         /*!< ADC0 clock enable */
 #define  RCC_APB2CCR_ADC1EN                         ((uint32_t)0x00000400)         /*!< ADC1 clock enable */
-#define  RCC_APB2CCR_TIMER1EN                       ((uint32_t)0x00000800)         /*!< TIMER1 clock enable */
+#define  RCC_APB2CCR_TIMER0EN                       ((uint32_t)0x00000800)         /*!< TIMER0 clock enable */
 #define  RCC_APB2CCR_SPI1EN                         ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
-#define  RCC_APB2CCR_TIMER8EN                       ((uint32_t)0x00002000)         /*!< TIMER8 clock enable */
+#define  RCC_APB2CCR_TIMER7EN                       ((uint32_t)0x00002000)         /*!< TIMER7 clock enable */
 #define  RCC_APB2CCR_USART1EN                       ((uint32_t)0x00004000)         /*!< USART1 clock enable */
 #define  RCC_APB2CCR_ADC3EN                         ((uint32_t)0x00008000)         /*!< ADC3 clock enable */
-#define  RCC_APB2CCR_TIMER9EN                       ((uint32_t)0x00080000)         /*!< TIMER9 clock enable */
-#define  RCC_APB2CCR_TIMER10EN                      ((uint32_t)0x00100000)         /*!< TIMER10 clock enable */
-#define  RCC_APB2CCR_TIMER11EN                      ((uint32_t)0x00200000)         /*!< TIMER11 clock enable */
+#define  RCC_APB2CCR_TIMER8EN                       ((uint32_t)0x00080000)         /*!< TIMER8 clock enable */
+#define  RCC_APB2CCR_TIMER9EN                       ((uint32_t)0x00100000)         /*!< TIMER9 clock enable */
+#define  RCC_APB2CCR_TIMER10EN                      ((uint32_t)0x00200000)         /*!< TIMER10 clock enable */
 
 /*****************  Bit definition for RCC_APB1CCR register  ******************/
 
-#define  RCC_APB1CCR_TIMER2EN                       ((uint32_t)0x00000001)        /*!< TIMER2 clock enable */
-#define  RCC_APB1CCR_TIMER3EN                       ((uint32_t)0x00000002)        /*!< TIMER3 clock enable */
-#define  RCC_APB1CCR_TIMER4EN                       ((uint32_t)0x00000004)        /*!< TIMER4 clock enable */
-#define  RCC_APB1CCR_TIMER5EN                       ((uint32_t)0x00000008)        /*!< TIMER8 clock enable */
-#define  RCC_APB1CCR_TIMER6EN                       ((uint32_t)0x00000010)        /*!< TIMER6 clock enable */
-#define  RCC_APB1CCR_TIMER7EN                       ((uint32_t)0x00000020)        /*!< TIMER7 clock enable */
-#define  RCC_APB1CCR_TIMER12EN                      ((uint32_t)0x00000040)        /*!< TIMER12 clock enable */
-#define  RCC_APB1CCR_TIMER13EN                      ((uint32_t)0x00000080)        /*!< TIMER13 clock enable */
-#define  RCC_APB1CCR_TIMER14EN                      ((uint32_t)0x00000100)        /*!< TIMER14 clock enable */
+#define  RCC_APB1CCR_TIMER1EN                       ((uint32_t)0x00000001)        /*!< TIMER1 clock enable */
+#define  RCC_APB1CCR_TIMER2EN                       ((uint32_t)0x00000002)        /*!< TIMER2 clock enable */
+#define  RCC_APB1CCR_TIMER3EN                       ((uint32_t)0x00000004)        /*!< TIMER3 clock enable */
+#define  RCC_APB1CCR_TIMER4EN                       ((uint32_t)0x00000008)        /*!< TIMER7 clock enable */
+#define  RCC_APB1CCR_TIMER5EN                       ((uint32_t)0x00000010)        /*!< TIMER5 clock enable */
+#define  RCC_APB1CCR_TIMER6EN                       ((uint32_t)0x00000020)        /*!< TIMER6 clock enable */
+#define  RCC_APB1CCR_TIMER11EN                      ((uint32_t)0x00000040)        /*!< TIMER11 clock enable */
+#define  RCC_APB1CCR_TIMER12EN                      ((uint32_t)0x00000080)        /*!< TIMER12 clock enable */
+#define  RCC_APB1CCR_TIMER13EN                      ((uint32_t)0x00000100)        /*!< TIMER13 clock enable */
 #define  RCC_APB1CCR_WWDGEN                         ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
 #define  RCC_APB1CCR_SPI2EN                         ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
 #define  RCC_APB1CCR_SPI3EN                         ((uint32_t)0x00008000)        /*!< SPI3 clock enable*/
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
index 207b365572..9772751542 100644
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
+++ b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
@@ -455,14 +455,14 @@ typedef struct {
 #define  RCC_APB2PERIPH_GPIOG             RCC_APB2CCR_PGEN
 #define  RCC_APB2PERIPH_ADC0              RCC_APB2CCR_ADC0EN
 #define  RCC_APB2PERIPH_ADC1              RCC_APB2CCR_ADC1EN
-#define  RCC_APB2PERIPH_TIMER1            RCC_APB2CCR_TIMER1EN
+#define  RCC_APB2PERIPH_TIMER0            RCC_APB2CCR_TIMER0EN
 #define  RCC_APB2PERIPH_SPI1              RCC_APB2CCR_SPI1EN
-#define  RCC_APB2PERIPH_TIMER8            RCC_APB2CCR_TIMER8EN
+#define  RCC_APB2PERIPH_TIMER7            RCC_APB2CCR_TIMER7EN
 #define  RCC_APB2PERIPH_USART1            RCC_APB2CCR_USART1EN
 #define  RCC_APB2PERIPH_ADC2              RCC_APB2CCR_ADC2EN
-#define  RCC_APB2PERIPH_TIMER9            RCC_APB2CCR_TIMER9EN
+#define  RCC_APB2PERIPH_TIMER8            RCC_APB2CCR_TIMER8EN
+#define  RCC_APB2PERIPH_TIMER9           RCC_APB2CCR_TIMER9EN
 #define  RCC_APB2PERIPH_TIMER10           RCC_APB2CCR_TIMER10EN
-#define  RCC_APB2PERIPH_TIMER11           RCC_APB2CCR_TIMER11EN
 
 /**
   * @}
@@ -481,14 +481,14 @@ typedef struct {
 #define  RCC_APB2PERIPH_GPIOGRST          RCC_APB2RCR_PGRST
 #define  RCC_APB2PERIPH_ADC0RST           RCC_APB2RCR_ADC0RST
 #define  RCC_APB2PERIPH_ADC1RST           RCC_APB2RCR_ADC1RST
-#define  RCC_APB2PERIPH_TIMER1RST         RCC_APB2RCR_TIMER1RST
+#define  RCC_APB2PERIPH_TIMER0RST         RCC_APB2RCR_TIMER0RST
 #define  RCC_APB2PERIPH_SPI1RST           RCC_APB2RCR_SPI1RST
-#define  RCC_APB2PERIPH_TIMER8RST         RCC_APB2RCR_TIMER8RST
+#define  RCC_APB2PERIPH_TIMER7RST         RCC_APB2RCR_TIMER7RST
 #define  RCC_APB2PERIPH_USART0RST         RCC_APB2RCR_USART0RST
 #define  RCC_APB2PERIPH_ADC2RST           RCC_APB2RCR_ADC2RST
+#define  RCC_APB2PERIPH_TIMER8RST         RCC_APB2RCR_TIMER8RST
 #define  RCC_APB2PERIPH_TIMER9RST         RCC_APB2RCR_TIMER9RST
 #define  RCC_APB2PERIPH_TIMER10RST        RCC_APB2RCR_TIMER10RST
-#define  RCC_APB2PERIPH_TIMER11RST        RCC_APB2RCR_TIMER11RST
 
 /**
   * @}
@@ -497,15 +497,15 @@ typedef struct {
 /** @defgroup RCC_APB1_peripheral
   * @{
   */
+#define  RCC_APB1PERIPH_TIMER1            RCC_APB1CCR_TIMER1EN
 #define  RCC_APB1PERIPH_TIMER2            RCC_APB1CCR_TIMER2EN
 #define  RCC_APB1PERIPH_TIMER3            RCC_APB1CCR_TIMER3EN
 #define  RCC_APB1PERIPH_TIMER4            RCC_APB1CCR_TIMER4EN
 #define  RCC_APB1PERIPH_TIMER5            RCC_APB1CCR_TIMER5EN
 #define  RCC_APB1PERIPH_TIMER6            RCC_APB1CCR_TIMER6EN
-#define  RCC_APB1PERIPH_TIMER7            RCC_APB1CCR_TIMER7EN
+#define  RCC_APB1PERIPH_TIMER11           RCC_APB1CCR_TIMER11EN
 #define  RCC_APB1PERIPH_TIMER12           RCC_APB1CCR_TIMER12EN
 #define  RCC_APB1PERIPH_TIMER13           RCC_APB1CCR_TIMER13EN
-#define  RCC_APB1PERIPH_TIMER14           RCC_APB1CCR_TIMER14EN
 #define  RCC_APB1PERIPH_WWDG              RCC_APB1CCR_WWDGEN
 #define  RCC_APB1PERIPH_SPI2              RCC_APB1CCR_SPI2EN
 #define  RCC_APB1PERIPH_SPI3              RCC_APB1CCR_SPI3EN
@@ -529,15 +529,15 @@ typedef struct {
 /** @defgroup RCC_APB1_Peripherals_RST
   * @{
   */
+#define  RCC_APB1PERIPH_TIMER1RST         RCC_APB1RCR_TIMER1RST
 #define  RCC_APB1PERIPH_TIMER2RST         RCC_APB1RCR_TIMER2RST
 #define  RCC_APB1PERIPH_TIMER3RST         RCC_APB1RCR_TIMER3RST
 #define  RCC_APB1PERIPH_TIMER4RST         RCC_APB1RCR_TIMER4RST
 #define  RCC_APB1PERIPH_TIMER5RST         RCC_APB1RCR_TIMER5RST
 #define  RCC_APB1PERIPH_TIMER6RST         RCC_APB1RCR_TIMER6RST
-#define  RCC_APB1PERIPH_TIMER7RST         RCC_APB1RCR_TIMER7RST
+#define  RCC_APB1PERIPH_TIMER11RST        RCC_APB1RCR_TIMER11RST
 #define  RCC_APB1PERIPH_TIMER12RST        RCC_APB1RCR_TIMER12RST
 #define  RCC_APB1PERIPH_TIMER13RST        RCC_APB1RCR_TIMER13RST
-#define  RCC_APB1PERIPH_TIMER14RST        RCC_APB1RCR_TIMER14RST
 #define  RCC_APB1PERIPH_WWDGRST           RCC_APB1RCR_WWDGRST
 #define  RCC_APB1PERIPH_SPI2RST           RCC_APB1RCR_SPI2RST
 #define  RCC_APB1PERIPH_SPI3RST           RCC_APB1RCR_SPI3RST
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
index b24274fa49..d5fd7fdf74 100644
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
+++ b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
@@ -45,14 +45,17 @@ static void TI4_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_
 
 /**
   * @brief  Deinitialize the TIMER .
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @retval None
   */
 void TIMER_DeInit(TIMER_TypeDef *TIMERx)
 {
-    if (TIMERx == TIMER1) {
-        RCC->APB2RCR |= RCC_APB2PERIPH_TIMER1RST;
-        RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER1;
+    if (TIMERx == TIMER0) {
+        RCC->APB2RCR |= RCC_APB2PERIPH_TIMER0RST;
+        RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER0;
+    } else if (TIMERx == TIMER1) {
+        RCC->APB1RCR |= RCC_APB1PERIPH_TIMER1RST;
+        RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER1;
     } else if (TIMERx == TIMER2) {
         RCC->APB1RCR |= RCC_APB1PERIPH_TIMER2RST;
         RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER2;
@@ -69,8 +72,8 @@ void TIMER_DeInit(TIMER_TypeDef *TIMERx)
         RCC->APB1RCR |= RCC_APB1PERIPH_TIMER6RST;
         RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER6;
     } else if (TIMERx == TIMER7) {
-        RCC->APB1RCR |= RCC_APB1PERIPH_TIMER7RST;
-        RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER7;
+        RCC->APB2RCR |= RCC_APB2PERIPH_TIMER7RST;
+        RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER7;
     } else if (TIMERx == TIMER8) {
         RCC->APB2RCR |= RCC_APB2PERIPH_TIMER8RST;
         RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER8;
@@ -81,23 +84,20 @@ void TIMER_DeInit(TIMER_TypeDef *TIMERx)
         RCC->APB2RCR |= RCC_APB2PERIPH_TIMER10RST;
         RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER10;
     } else if (TIMERx == TIMER11) {
-        RCC->APB2RCR |= RCC_APB2PERIPH_TIMER11RST;
-        RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER11;
+        RCC->APB1RCR |= RCC_APB1PERIPH_TIMER11RST;
+        RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER11;
     } else if (TIMERx == TIMER12) {
         RCC->APB1RCR |= RCC_APB1PERIPH_TIMER12RST;
         RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER12;
     } else if (TIMERx == TIMER13) {
         RCC->APB1RCR |= RCC_APB1PERIPH_TIMER13RST;
         RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER13;
-    } else if (TIMERx == TIMER14) {
-        RCC->APB1RCR |= RCC_APB1PERIPH_TIMER14RST;
-        RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER14;
     }
 }
 
 /**
   * @brief  Initialize the specified Timer
-  * @param  TIMERx:  x ={ 1 -14 } .
+  * @param  TIMERx:  x ={ 0 -13 } .
   * @param  TIMER_Init: pointer to a TIMER_BaseInitPara structure.
   * @retval None
   */
@@ -107,15 +107,15 @@ void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init)
 
     tmpctlr1 = TIMERx->CTLR1;
 
-    if ((TIMERx == TIMER1) || (TIMERx == TIMER8) || (TIMERx == TIMER2) || (TIMERx == TIMER3) ||
-            (TIMERx == TIMER4) || (TIMERx == TIMER5) || (TIMERx == TIMER9) || (TIMERx == TIMER10)
-            || (TIMERx == TIMER11) || (TIMERx == TIMER12) || (TIMERx == TIMER13) || (TIMERx == TIMER14)) {
+    if ((TIMERx == TIMER0) || (TIMERx == TIMER7) || (TIMERx == TIMER1) || (TIMERx == TIMER2) ||
+            (TIMERx == TIMER3) || (TIMERx == TIMER4) || (TIMERx == TIMER8) || (TIMERx == TIMER9)
+            || (TIMERx == TIMER10) || (TIMERx == TIMER11) || (TIMERx == TIMER12) || (TIMERx == TIMER13)) {
         /* Configure the Counter Mode */
         tmpctlr1 &= (uint16_t)(~((uint16_t)(TIMER_CTLR1_DIR | TIMER_CTLR1_CAM)));
         tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_CounterMode;
     }
 
-    if ((TIMERx != TIMER6) && (TIMERx != TIMER7)) {
+    if ((TIMERx != TIMER5) && (TIMERx != TIMER6)) {
         /* Configure the clock division */
         tmpctlr1 &= (uint16_t)(~((uint16_t)TIMER_CTLR1_CDIV));
         tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_ClockDivision;
@@ -129,8 +129,8 @@ void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init)
     /* Configure the Prescaler value */
     TIMERx->PSC = TIMER_Init->TIMER_Prescaler;
 
-    if ((TIMERx == TIMER1)  ||
-            (TIMERx == TIMER8)) {
+    if ((TIMERx == TIMER0)  ||
+            (TIMERx == TIMER7)) {
         /* Configure the Repetition Counter value */
         TIMERx->CREP = TIMER_Init->TIMER_RepetitionCounter;
     }
@@ -156,7 +156,7 @@ void TIMER_BaseStructInit(TIMER_BaseInitPara *TIMER_Init)
 
 /**
   * @brief  Configure the TIMER Prescaler.
-  * @param  TIMERx:  x ={ 1-14 }
+  * @param  TIMERx:  x ={ 0-13 }
   * @param  Prescaler:  Prescaler value
   * @param  TIMER_PSCReloadMode:  Prescaler Reload mode
   *   This value will be :
@@ -203,7 +203,7 @@ void TIMER_CounterMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_CounterMode)
 
 /**
   * @brief  Configure the TIMER Counter Register value
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  Counter: the Counter register new value.
   * @retval None
   */
@@ -214,7 +214,7 @@ void TIMER_SetCounter(TIMER_TypeDef *TIMERx, uint32_t Counter)
 
 /**
   * @brief  Configure the Autoreload value
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  AutoReloadValue:
   * @retval None
   */
@@ -225,7 +225,7 @@ void TIMER_SetAutoreload(TIMER_TypeDef *TIMERx, uint32_t AutoReloadValue)
 
 /**
   * @brief  Get the Counter value.
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @retval Counter Register value.
   */
 uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx)
@@ -235,7 +235,7 @@ uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx)
 
 /**
   * @brief  Get the Prescaler value.
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @retval Prescaler Register value
   */
 uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx)
@@ -245,7 +245,7 @@ uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx)
 
 /**
   * @brief  Configure the TIMERx Update event.
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  NewValue: new value of the TIMERx UPDIS bit
   *   This value will be :
   *     @arg ENABLE  : Update Enbale
@@ -263,7 +263,7 @@ void TIMER_UpdateDisableConfig(TIMER_TypeDef *TIMERx, TypeState NewValue)
 
 /**
   * @brief  Configure the TIMER Update Request source.
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_UpdateSrc: Configures the Update source.
   *   This value will be :
   *     @arg TIMER_UPDATE_SRC_GLOBAL    : Update generate by setting of UPG bit or the counter
@@ -282,7 +282,7 @@ void TIMER_UpdateRequestConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_UpdateSrc)
 
 /**
   * @brief  Configure the CARL Preload function
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  NewValue: the state of the Preload function on CARL.
   *   This value will be :
   *     @arg ENABLE
@@ -339,7 +339,7 @@ void TIMER_SetClockDivision(TIMER_TypeDef *TIMERx, uint16_t TIMER_CDIV)
 
 /**
   * @brief  ENABLE or DISABLE the TIMER.
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  NewValue: ENABLE or DISABLE.
   * @retval None
   */
@@ -443,7 +443,7 @@ void TIMER_OC1_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
     /* Set the Output State */
     tmpche |= TIMER_OCInit->TIMER_OutputState;
 
-    if ((TIMERx == TIMER1) || (TIMERx == TIMER8)) {
+    if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
         /* Reset the Output complementary Polarity */
         tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1NP));
 
@@ -518,7 +518,7 @@ void TIMER_OC2_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
     /* Set the Output State */
     tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 4);
 
-    if ((TIMERx == TIMER1) || (TIMERx == TIMER8)) {
+    if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
         /* Reset the Output complementary Polarity */
         tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2NP));
 
@@ -593,7 +593,7 @@ void TIMER_OC3_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
     /* Set the Output State */
     tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 8);
 
-    if ((TIMERx == TIMER1) || (TIMERx == TIMER8)) {
+    if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
         /* Reset the Output complementary Polarity */
         tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3NP));
 
@@ -667,7 +667,7 @@ void TIMER_OC4_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
     /* Set the Output State */
     tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 12);
 
-    if ((TIMERx == TIMER1) || (TIMERx == TIMER8)) {
+    if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
         /* Reset the Ouput Compare IDLE State */
         tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO4));
 
@@ -1646,7 +1646,7 @@ void TIMER_Set_IC4_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC)
 
 /**
   * @brief  Configure interrupts Enables
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_INT:  the interrupts sources to Configure.
   *   This value will be :
   *     @arg TIMER_INT_UPDATE  : update Interrupt
@@ -1671,7 +1671,7 @@ void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT, TypeState NewVal
 
 /**
   * @brief  Generate the software event
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_EventSrc:
   *   This value will be :
   *     @arg TIMER_EVENT_SRC_UPDATE  : update Event
@@ -1691,7 +1691,7 @@ void TIMER_GenerateEvent(TIMER_TypeDef *TIMERx, uint16_t TIMER_EventSrc)
 
 /**
   * @brief  Get current flag status
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_FLAG:
   *   This value will be :
   *     @arg TIMER_FLAG_UPDATE  : update Flag
@@ -1719,7 +1719,7 @@ TypeState TIMER_GetBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG)
 
 /**
   * @brief  Clear the flags
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_FLAG: the flag bit to clear.
   *   This value will be :
   *     @arg TIMER_FLAG_UPDATE  : update Flag
@@ -1743,7 +1743,7 @@ void TIMER_ClearBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG)
 
 /**
   * @brief  Get interrupt state
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_INT:
   *   This value will be :
   *     @arg TIMER_INT_UPDATE: update Interrupt
@@ -1772,7 +1772,7 @@ TypeState TIMER_GetIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT)
 
 /**
   * @brief  Clear the interrupt pending bits
-  * @param  TIMERx:  x ={ 1-14 } .
+  * @param  TIMERx:  x ={ 0-13 } .
   * @param  TIMER_INT:
   *   This value will be :
   *     @arg TIMER_INT_UPDATE: update Interrupt
diff --git a/bsp/gd32103c-eval/README.md b/bsp/gd32103c-eval/README.md
index 20a0d2c55c..1f3c3d3425 100644
--- a/bsp/gd32103c-eval/README.md
+++ b/bsp/gd32103c-eval/README.md
@@ -47,6 +47,7 @@ msh />
 | UART      | 支持     |          UART0~4           |
 | GPIO      | 支持     |          GPIOA~G           |
 | ADC       | 支持     |          ADC0~1            |
+| HWTIMER   | 支持     |          TIMER0~7          |
 | IIC       | 未支持   |          I2C0~1            |
 | SPI       | 未支持   |          SPI0~2            |
 | ETH       | 未支持   |                            |
diff --git a/bsp/gd32103c-eval/drivers/SConscript b/bsp/gd32103c-eval/drivers/SConscript
index 374218f0ab..35734e9d10 100644
--- a/bsp/gd32103c-eval/drivers/SConscript
+++ b/bsp/gd32103c-eval/drivers/SConscript
@@ -21,6 +21,9 @@ if GetDepend('RT_USING_PIN'):
 if GetDepend('RT_USING_ADC'):
     src += ['drv_adc.c']
 
+if GetDepend('RT_USING_HWTIMER'):
+    src += ['drv_hwtimer.c']
+
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/gd32103c-eval/drivers/drv_comm.h b/bsp/gd32103c-eval/drivers/drv_comm.h
new file mode 100644
index 0000000000..5aef53cce2
--- /dev/null
+++ b/bsp/gd32103c-eval/drivers/drv_comm.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-01-28     iysheng           first version
+ */
+
+#ifndef __DRV_COMM_H__
+#define __DRV_COMM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x)    (sizeof(x) / sizeof(x[0]))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_HWTIMER_H__ */
+
diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.c b/bsp/gd32103c-eval/drivers/drv_hwtimer.c
new file mode 100644
index 0000000000..8b5f5010e6
--- /dev/null
+++ b/bsp/gd32103c-eval/drivers/drv_hwtimer.c
@@ -0,0 +1,540 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-01-28     iysheng           first version
+ */
+
+#include <board.h>
+#include <drivers/drv_comm.h>
+#include <drivers/drv_hwtimer.h>
+
+#ifdef BSP_USING_HWTIMER
+
+enum timer_index_E {
+#ifdef BSP_USING_HWTIMER0
+    TIM0_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER2
+    TIM2_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER3
+    TIM3_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER4
+    TIM4_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER5
+    TIM5_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER6
+    TIM6_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER7
+    TIM7_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER8
+    TIM8_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER9
+    TIM9_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER10
+    TIM10_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER11
+    TIM11_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER12
+    TIM12_INDEX,
+#endif
+#ifdef BSP_USING_HWTIMER13
+    TIM13_INDEX,
+#endif
+};
+
+/*
+ * static void __set_timerx_freq
+ * Set freq with timerx
+ *
+ * @param timerx the pointer of TIMER_TypeDef
+ * @param freq of the timer clock
+ * @retval None
+ */
+static void __set_timerx_freq(TIMER_TypeDef *timerx, uint32_t freq)
+{
+    RCC_ClocksPara RCC_Clocks = {0};
+    uint16_t prescaler;
+    uint32_t temp;
+
+    RCC_GetClocksFreq(&RCC_Clocks);
+    if (timerx == TIMER0 || timerx == TIMER7 || timerx == TIMER8 \
+        || timerx == TIMER9 || timerx == TIMER10)
+    {
+        temp = RCC->GCFGR & RCC_GCFGR_APB2PS;
+        temp >>= 11;
+        /* whether should frequency doubling */
+        temp = (temp < 4) ? 0 : 1;
+
+        prescaler = (RCC_Clocks.APB2_Frequency << temp) / freq - 1;
+    }
+    else
+    {
+        temp = RCC->GCFGR & RCC_GCFGR_APB1PS;
+        temp >>= 8;
+        /* whether should frequency doubling */
+        temp = (temp < 4) ? 0 : 1;
+
+        prescaler = (RCC_Clocks.APB1_Frequency << temp) / freq - 1;
+    }
+
+    TIMER_PrescalerConfig(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
+}
+
+static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
+{
+    TIMER_TypeDef * timer_base = timer->parent.user_data;
+    TIMER_BaseInitPara TIMER_Init;
+
+    RT_ASSERT(timer_base);
+
+    if (state)
+    {
+        TIMER_InternalClockConfig(timer_base);
+        TIMER_BaseStructInit(&TIMER_Init);
+        TIMER_Init.TIMER_Period =  timer->info->maxcnt;
+        TIMER_BaseInit(timer_base, &TIMER_Init);
+        __set_timerx_freq(timer_base, timer->info->maxfreq);
+    }
+}
+
+static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \
+    rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+{
+    TIMER_TypeDef * timer_base = timer->parent.user_data;
+
+    if (mode == HWTIMER_MODE_ONESHOT)
+    {
+        TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_SINGLE);
+    }
+    else if (mode == HWTIMER_MODE_PERIOD)
+    {
+        TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_REPETITIVE);
+    }
+
+    TIMER_SetCounter(timer_base, 0);
+    TIMER_SetAutoreload(timer_base, cnt - 1);
+    TIMER_Enable(timer_base, ENABLE);
+
+    return 0;
+}
+
+static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer)
+{
+    TIMER_TypeDef * timer_base = timer->parent.user_data;
+
+    TIMER_Enable(timer_base, DISABLE);
+}
+
+static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer)
+{
+    TIMER_TypeDef * timer_base = timer->parent.user_data;
+    rt_uint32_t count;
+
+    count = TIMER_GetCounter(timer_base);
+
+    return count;
+}
+
+static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_t cmd, \
+    void *args)
+{
+    int ret = RT_EOK;
+    rt_int32_t freq;
+    rt_hwtimer_mode_t mode;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+        freq = *(rt_uint32_t *)args;
+        __set_timerx_freq(timer->parent.user_data, freq);
+        break;
+    default:
+        rt_kprintf("invalid cmd:%x\n", cmd);
+        ret = -EINVAL;
+        break;
+    }
+
+    return ret;
+}
+
+static const struct rt_hwtimer_ops g_gd32_hwtimer_ops = {
+    gd32_hwtimer_init,
+    gd32_hwtimer_start,
+    gd32_hwtimer_stop,
+    gd32_hwtimer_count_get,
+    gd32_hwtimer_control,
+};
+
+static gd32_hwtimer_device g_gd32_hwtimer[] = {
+#ifdef BSP_USING_HWTIMER0
+    {
+        "timer0",
+        {
+             TIMER0,
+             TIMER0_UP_IRQn,
+             RCU_TIMER0,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER1
+    {
+        "timer1",
+        {
+             TIMER1,
+             TIMER1_IRQn,
+             RCU_TIMER1,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER2
+    {
+        "timer2",
+        {
+             TIMER2,
+             TIMER2_IRQn,
+             RCU_TIMER2,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER3
+    {
+        "timer3",
+        {
+             TIMER3,
+             TIMER3_IRQn,
+             RCU_TIMER3,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER4
+    {
+        "timer4",
+        {
+             TIMER4,
+             TIMER4_IRQn,
+             RCU_TIMER4,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER5
+    {
+        "timer5",
+        {
+             TIMER5,
+             TIMER5_IRQn,
+             RCU_TIMER5,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER6
+    {
+        "timer6",
+        {
+             TIMER6,
+             TIMER6_IRQn,
+             RCU_TIMER6,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER7
+    {
+        "timer7",
+        {
+             TIMER7,
+             TIMER7_UP_IRQn,
+             RCU_TIMER7,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER8
+    {
+        "timer8",
+        {
+             TIMER8,
+             TIMER8_IRQn,
+             RCU_TIMER8,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER9
+    {
+        "timer9",
+        {
+             TIMER9,
+             TIMER9_IRQn,
+             RCU_TIMER9,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER10
+    {
+        "timer10",
+        {
+             TIMER10,
+             TIMER10_IRQn,
+             RCU_TIMER10,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER11
+    {
+        "timer11",
+        {
+             TIMER11,
+             TIMER11_IRQn,
+             RCU_TIMER11,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER12
+    {
+        "timer12",
+        {
+             TIMER12,
+             TIMER12_IRQn,
+             RCU_TIMER12,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+#ifdef BSP_USING_HWTIMER13
+    {
+        "timer13",
+        {
+             TIMER13,
+             TIMER13_IRQn,
+             RCU_TIMER13,
+        },
+        {0},
+        {
+            1000000,
+            1000,
+            0xffff,
+            0, /* count up mode  */
+        }
+    },
+#endif
+};
+
+#ifdef BSP_USING_HWTIMER0
+void TIMER0_UP_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER1
+void TIMER1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER2
+void TIMER2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER3
+void TIMER3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER4
+void TIMER4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER5
+void TIMER5_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER6
+void TIMER6_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_HWTIMER7
+void TIMER7_UP_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev);
+    TIMER_ClearIntBitState(g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
+        TIMER_INT_UPDATE);
+    rt_interrupt_leave();
+}
+#endif
+
+static int rt_hwtimer_init(void)
+{
+    int ret = 0, i = 0;
+
+    for (; i < ARRAY_SIZE(g_gd32_hwtimer); i++)
+    {
+        g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops;
+        g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info;
+
+        rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu);
+        NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0);
+        NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn);
+        TIMER_INTConfig(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UPDATE, ENABLE);
+        ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \
+            g_gd32_hwtimer[i].dev_name, g_gd32_hwtimer[i].hw_data.reg_base);
+        if (RT_EOK != ret)
+        {
+            rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \
+                ret);
+            break;
+        }
+    }
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hwtimer_init);
+#endif
diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.h b/bsp/gd32103c-eval/drivers/drv_hwtimer.h
new file mode 100644
index 0000000000..1b1a7e7da9
--- /dev/null
+++ b/bsp/gd32103c-eval/drivers/drv_hwtimer.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-01-15     iysheng           first release
+ */
+
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <drivers/hwtimer.h>
+
+typedef struct {
+    TIMER_TypeDef *reg_base;
+    IRQn_Type irqn;
+    rcu_periph_enum rcu;
+} gd32_hwtimer_data;
+
+typedef struct {
+    char dev_name[RT_NAME_MAX];
+    const gd32_hwtimer_data hw_data;
+    rt_hwtimer_t hwtimer_dev;
+    const struct rt_hwtimer_info hwtimer_info;
+} gd32_hwtimer_device;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_HWTIMER_H__ */
+