diff options
| author | Grissiom <[email protected]> | 2013-05-26 17:10:49 +0800 |
|---|---|---|
| committer | Grissiom <[email protected]> | 2013-05-26 17:22:36 +0800 |
| commit | 3d0647efb3980238c2a1c511f24b45f430f1d2e4 (patch) | |
| tree | 002de04fcef5ef2cb1ad4955e1f4007d767f031f | |
| parent | b39d038cf00edf416753ae8a6d668aaa0a189871 (diff) | |
rm48x50: optimize context_switch_interrupt_do
Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
| -rw-r--r-- | libcpu/arm/rm48x50/context_ccs.asm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/arm/rm48x50/context_ccs.asm b/libcpu/arm/rm48x50/context_ccs.asm index dad36f8f40..e72f9f0f68 100644 --- a/libcpu/arm/rm48x50/context_ccs.asm +++ b/libcpu/arm/rm48x50/context_ccs.asm @@ -127,9 +127,9 @@ rt_hw_context_switch_interrupt_do STR r1, [r0] LDMFD sp!, {r0-r12,lr} ; reload saved registers - STMFD sp!, {r0-r3} ; save r0-r3 - MOV r1, sp - ADD sp, sp, #16 ; restore sp + STMFD sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC + ; mode so there is no need to update SP. + SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3. SUB r2, lr, #4 ; save old task's pc to r2 MRS r3, spsr ; get cpsr of interrupt thread |