Merge remote-tracking branch 'upstream/master'

8 files changed, 512 insertions, 9 deletions

diff --git a/bsp/stm32f10x/drivers/gpio.c b/bsp/stm32f10x/drivers/gpio.c
new file mode 100644
index 0000000000..747b55b4dc
--- /dev/null
+++ b/bsp/stm32f10x/drivers/gpio.c
@@ -0,0 +1,479 @@
+/*
+ * File      : gpio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-03-24     Bright      the first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef RT_USING_PIN
+
+#define STM32F10X_PIN_NUMBERS 100 //[ 64, 100, 144 ]
+
+#define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index}
+#define __STM32_PIN_DEFAULT {-1, 0, 0, 0}
+
+/* STM32 GPIO driver */
+struct pin_index
+{
+    int index;
+    uint32_t rcc;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+#if (STM32F10X_PIN_NUMBERS == 64)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(2, APB2, C, 13),
+    __STM32_PIN(3, APB2, C, 14),
+    __STM32_PIN(4, APB2, C, 15),
+    __STM32_PIN(5, APB2, D, 0),
+    __STM32_PIN(6, APB2, D, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(8, APB2, C, 0),
+    __STM32_PIN(9, APB2, C, 1),
+    __STM32_PIN(10, APB2, C, 2),
+    __STM32_PIN(11, APB2, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(14, APB2, A, 0),
+    __STM32_PIN(15, APB2, A, 1),
+    __STM32_PIN(16, APB2, A, 2),
+    __STM32_PIN(17, APB2, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(20, APB2, A, 4),
+    __STM32_PIN(21, APB2, A, 5),
+    __STM32_PIN(22, APB2, A, 6),
+    __STM32_PIN(23, APB2, A, 7),
+    __STM32_PIN(24, APB2, C, 4),
+    __STM32_PIN(25, APB2, C, 5),
+    __STM32_PIN(26, APB2, B, 0),
+    __STM32_PIN(27, APB2, B, 1),
+    __STM32_PIN(28, APB2, B, 2),
+    __STM32_PIN(29, APB2, B, 10),
+    __STM32_PIN(30, APB2, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(33, APB2, B, 12),
+    __STM32_PIN(34, APB2, B, 13),
+    __STM32_PIN(35, APB2, B, 14),
+    __STM32_PIN(36, APB2, B, 15),
+    __STM32_PIN(37, APB2, C, 6),
+    __STM32_PIN(38, APB2, C, 7),
+    __STM32_PIN(39, APB2, C, 8),
+    __STM32_PIN(40, APB2, C, 9),
+    __STM32_PIN(41, APB2, A, 8),
+    __STM32_PIN(42, APB2, A, 9),
+    __STM32_PIN(43, APB2, A, 10),
+    __STM32_PIN(44, APB2, A, 11),
+    __STM32_PIN(45, APB2, A, 12),
+    __STM32_PIN(46, APB2, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(49, APB2, A, 14),
+    __STM32_PIN(50, APB2, A, 15),
+    __STM32_PIN(51, APB2, C, 10),
+    __STM32_PIN(52, APB2, C, 11),
+    __STM32_PIN(53, APB2, C, 12),
+    __STM32_PIN(54, APB2, D, 2),
+    __STM32_PIN(55, APB2, B, 3),
+    __STM32_PIN(56, APB2, B, 4),
+    __STM32_PIN(57, APB2, B, 5),
+    __STM32_PIN(58, APB2, B, 6),
+    __STM32_PIN(59, APB2, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(61, APB2, B, 8),
+    __STM32_PIN(62, APB2, B, 9),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+#if (STM32F10X_PIN_NUMBERS == 100)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(1, APB2, E, 2),
+    __STM32_PIN(2, APB2, E, 3),
+    __STM32_PIN(3, APB2, E, 4),
+    __STM32_PIN(4, APB2, E, 5),
+    __STM32_PIN(5, APB2, E, 6),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(7, APB2, C, 13),
+    __STM32_PIN(8, APB2, C, 14),
+    __STM32_PIN(9, APB2, C, 15),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(15, APB2, C, 0),
+    __STM32_PIN(16, APB2, C, 1),
+    __STM32_PIN(17, APB2, C, 2),
+    __STM32_PIN(18, APB2, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(23, APB2, A, 0),
+    __STM32_PIN(24, APB2, A, 1),
+    __STM32_PIN(25, APB2, A, 2),
+    __STM32_PIN(26, APB2, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(29, APB2, A, 4),
+    __STM32_PIN(30, APB2, A, 5),
+    __STM32_PIN(31, APB2, A, 6),
+    __STM32_PIN(32, APB2, A, 7),
+    __STM32_PIN(33, APB2, C, 4),
+    __STM32_PIN(34, APB2, C, 5),
+    __STM32_PIN(35, APB2, B, 0),
+    __STM32_PIN(36, APB2, B, 1),
+    __STM32_PIN(37, APB2, B, 2),
+    __STM32_PIN(38, APB2, E, 7),
+    __STM32_PIN(39, APB2, E, 8),
+    __STM32_PIN(40, APB2, E, 9),
+    __STM32_PIN(41, APB2, E, 10),
+    __STM32_PIN(42, APB2, E, 11),
+    __STM32_PIN(43, APB2, E, 12),
+    __STM32_PIN(44, APB2, E, 13),
+    __STM32_PIN(45, APB2, E, 14),
+    __STM32_PIN(46, APB2, E, 15),
+    __STM32_PIN(47, APB2, B, 10),
+    __STM32_PIN(48, APB2, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(51, APB2, B, 12),
+    __STM32_PIN(52, APB2, B, 13),
+    __STM32_PIN(53, APB2, B, 14),
+    __STM32_PIN(54, APB2, B, 15),
+    __STM32_PIN(55, APB2, D, 8),
+    __STM32_PIN(56, APB2, D, 9),
+    __STM32_PIN(57, APB2, D, 10),
+    __STM32_PIN(58, APB2, D, 11),
+    __STM32_PIN(59, APB2, D, 12),
+    __STM32_PIN(60, APB2, D, 13),
+    __STM32_PIN(61, APB2, D, 14),
+    __STM32_PIN(62, APB2, D, 15),
+    __STM32_PIN(63, APB2, C, 6),
+    __STM32_PIN(64, APB2, C, 7),
+    __STM32_PIN(65, APB2, C, 8),
+    __STM32_PIN(66, APB2, C, 9),
+    __STM32_PIN(67, APB2, A, 8),
+    __STM32_PIN(68, APB2, A, 9),
+    __STM32_PIN(69, APB2, A, 10),
+    __STM32_PIN(70, APB2, A, 11),
+    __STM32_PIN(71, APB2, A, 12),
+    __STM32_PIN(72, APB2, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(76, APB2, A, 14),
+    __STM32_PIN(77, APB2, A, 15),
+    __STM32_PIN(78, APB2, C, 10),
+    __STM32_PIN(79, APB2, C, 11),
+    __STM32_PIN(80, APB2, C, 12),
+    __STM32_PIN(81, APB2, D, 0),
+    __STM32_PIN(82, APB2, D, 1),
+    __STM32_PIN(83, APB2, D, 2),
+    __STM32_PIN(84, APB2, D, 3),
+    __STM32_PIN(85, APB2, D, 4),
+    __STM32_PIN(86, APB2, D, 5),
+    __STM32_PIN(87, APB2, D, 6),
+    __STM32_PIN(88, APB2, D, 7),
+    __STM32_PIN(89, APB2, B, 3),
+    __STM32_PIN(90, APB2, B, 4),
+    __STM32_PIN(91, APB2, B, 5),
+    __STM32_PIN(92, APB2, B, 6),
+    __STM32_PIN(93, APB2, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(95, APB2, B, 8),
+    __STM32_PIN(96, APB2, B, 9),
+    __STM32_PIN(97, APB2, E, 0),
+    __STM32_PIN(98, APB2, E, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+#if (STM32F10X_PIN_NUMBERS == 144)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(1, APB2, E, 2),
+    __STM32_PIN(2, APB2, E, 3),
+    __STM32_PIN(3, APB2, E, 4),
+    __STM32_PIN(4, APB2, E, 5),
+    __STM32_PIN(5, APB2, E, 6),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(7, APB2, C, 13),
+    __STM32_PIN(8, APB2, C, 14),
+    __STM32_PIN(9, APB2, C, 15),
+    
+    __STM32_PIN(10, APB2, F, 0),
+    __STM32_PIN(11, APB2, F, 1),
+    __STM32_PIN(12, APB2, F, 2),
+    __STM32_PIN(13, APB2, F, 3),
+    __STM32_PIN(14, APB2, F, 4),
+    __STM32_PIN(15, APB2, F, 5),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(18, APB2, F, 6),
+    __STM32_PIN(19, APB2, F, 7),
+    __STM32_PIN(20, APB2, F, 8),
+    __STM32_PIN(21, APB2, F, 9),
+    __STM32_PIN(22, APB2, F, 10),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(26, APB2, C, 0),
+    __STM32_PIN(27, APB2, C, 1),
+    __STM32_PIN(28, APB2, C, 2),
+    __STM32_PIN(29, APB2, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(34, APB2, A, 0),
+    __STM32_PIN(35, APB2, A, 1),
+    __STM32_PIN(36, APB2, A, 2),
+    __STM32_PIN(37, APB2, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(40, APB2, A, 4),
+    __STM32_PIN(41, APB2, A, 5),
+    __STM32_PIN(42, APB2, A, 6),
+    __STM32_PIN(43, APB2, A, 7),
+    __STM32_PIN(44, APB2, C, 4),
+    __STM32_PIN(45, APB2, C, 5),
+    __STM32_PIN(46, APB2, B, 0),
+    __STM32_PIN(47, APB2, B, 1),
+    __STM32_PIN(48, APB2, B, 2),
+    __STM32_PIN(49, APB2, F, 11),
+    __STM32_PIN(50, APB2, F, 12),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(53, APB2, F, 13),
+    __STM32_PIN(54, APB2, F, 14),
+    __STM32_PIN(55, APB2, F, 15),
+    __STM32_PIN(56, APB2, G, 0),
+    __STM32_PIN(57, APB2, G, 1),
+    __STM32_PIN(58, APB2, E, 7),
+    __STM32_PIN(59, APB2, E, 8),
+    __STM32_PIN(60, APB2, E, 9),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(63, APB2, E, 10),
+    __STM32_PIN(64, APB2, E, 11),
+    __STM32_PIN(65, APB2, E, 12),
+    __STM32_PIN(66, APB2, E, 13),
+    __STM32_PIN(67, APB2, E, 14),
+    __STM32_PIN(68, APB2, E, 15),
+    __STM32_PIN(69, APB2, B, 10),
+    __STM32_PIN(70, APB2, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(73, APB2, B, 12),
+    __STM32_PIN(74, APB2, B, 13),
+    __STM32_PIN(75, APB2, B, 14),
+    __STM32_PIN(76, APB2, B, 15),
+    __STM32_PIN(77, APB2, D, 8),
+    __STM32_PIN(78, APB2, D, 9),
+    __STM32_PIN(79, APB2, D, 10),
+    __STM32_PIN(80, APB2, D, 11),
+    __STM32_PIN(81, APB2, D, 12),
+    __STM32_PIN(82, APB2, D, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(85, APB2, D, 14),
+    __STM32_PIN(86, APB2, D, 15),
+    __STM32_PIN(87, APB2, G, 2),
+    __STM32_PIN(88, APB2, G, 3),
+    __STM32_PIN(89, APB2, G, 4),
+    __STM32_PIN(90, APB2, G, 5),
+    __STM32_PIN(91, APB2, G, 6),
+    __STM32_PIN(92, APB2, G, 7),
+    __STM32_PIN(93, APB2, G, 8),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(96, APB2, C, 6),
+    __STM32_PIN(97, APB2, C, 7),
+    __STM32_PIN(98, APB2, C, 8),
+    __STM32_PIN(99, APB2, C, 9),
+    __STM32_PIN(100, APB2, A, 8),
+    __STM32_PIN(101, APB2, A, 9),
+    __STM32_PIN(102, APB2, A, 10),
+    __STM32_PIN(103, APB2, A, 11),
+    __STM32_PIN(104, APB2, A, 12),
+    __STM32_PIN(105, APB2, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(109, APB2, A, 14),
+    __STM32_PIN(110, APB2, A, 15),
+    __STM32_PIN(111, APB2, C, 10),
+    __STM32_PIN(112, APB2, C, 11),
+    __STM32_PIN(113, APB2, C, 12),
+    __STM32_PIN(114, APB2, D, 0),
+    __STM32_PIN(115, APB2, D, 1),
+    __STM32_PIN(116, APB2, D, 2),
+    __STM32_PIN(117, APB2, D, 3),
+    __STM32_PIN(118, APB2, D, 4),
+    __STM32_PIN(119, APB2, D, 5),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(122, APB2, D, 6),
+    __STM32_PIN(123, APB2, D, 7),
+    __STM32_PIN(124, APB2, G, 9),
+    __STM32_PIN(125, APB2, G, 10),
+    __STM32_PIN(126, APB2, G, 11),
+    __STM32_PIN(127, APB2, G, 12),
+    __STM32_PIN(128, APB2, G, 13),
+    __STM32_PIN(129, APB2, G, 14),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(132, APB2, G, 15),
+    __STM32_PIN(133, APB2, B, 3),
+    __STM32_PIN(134, APB2, B, 4),
+    __STM32_PIN(135, APB2, B, 5),
+    __STM32_PIN(136, APB2, B, 6),
+    __STM32_PIN(137, APB2, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(139, APB2, B, 8),
+    __STM32_PIN(140, APB2, B, 9),
+    __STM32_PIN(141, APB2, E, 0),
+    __STM32_PIN(142, APB2, E, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+};
+
+
+#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    if (value == PIN_LOW)
+    {
+        GPIO_ResetBits(index->gpio, index->pin);
+    }
+    else
+    {
+        GPIO_SetBits(index->gpio, index->pin);
+    }
+}
+
+int stm32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
+    {
+        value = PIN_LOW;
+    }
+    else
+    {
+        value = PIN_HIGH;
+    }
+
+    return value;
+}
+
+void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef  GPIO_InitStructure;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* GPIO Periph clock enable */
+    RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStructure.GPIO_Pin     = index->pin;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IN_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPU;
+    }
+    else
+    {
+        /* input setting:default. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPD;
+    }
+    GPIO_Init(index->gpio, &GPIO_InitStructure);
+}
+
+const static struct rt_pin_ops _stm32_pin_ops =
+{
+    stm32_pin_mode,
+    stm32_pin_write,
+    stm32_pin_read,
+};
+
+int stm32_hw_pin_init(void)
+{
+    int result;
+    
+    result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(stm32_hw_pin_init);
+
+#endif
diff --git a/bsp/stm32f10x/drivers/gpio.h b/bsp/stm32f10x/drivers/gpio.h
new file mode 100644
index 0000000000..a4947b100d
--- /dev/null
+++ b/bsp/stm32f10x/drivers/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * File      : gpio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-01-05     Bernard      the first version
+ */
+#ifndef GPIO_H__
+#define GPIO_H__
+
+int stm32_hw_pin_init(void);
+
+#endif
diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h
index bf2a25ae1e..3b0a009072 100644
--- a/components/drivers/include/drivers/serial.h
+++ b/components/drivers/include/drivers/serial.h
@@ -65,11 +65,6 @@
 #define RT_SERIAL_RB_BUFSZ              64
 #endif
 
-#define RT_DEVICE_CTRL_CONFIG           0x03    /* configure device */
-#define RT_DEVICE_CTRL_SET_INT          0x10    /* enable receive irq */
-#define RT_DEVICE_CTRL_CLR_INT          0x11    /* disable receive irq */
-#define RT_DEVICE_CTRL_GET_INT          0x12
-
 #define RT_SERIAL_EVENT_RX_IND          0x01    /* Rx indication */
 #define RT_SERIAL_EVENT_TX_DONE         0x02    /* Tx complete   */
 #define RT_SERIAL_EVENT_RX_DMADONE      0x03    /* Rx DMA transfer done */
diff --git a/components/drivers/misc/pin.c b/components/drivers/misc/pin.c
index d83c3d2f03..f3577a11d5 100644
--- a/components/drivers/misc/pin.c
+++ b/components/drivers/misc/pin.c
@@ -93,7 +93,7 @@ int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void
     _hw_pin.parent.user_data    = user_data;
 
     /* register a character device */
-    rt_device_register(&_hw_pin.parent, "pin", RT_DEVICE_FLAG_RDWR);
+    rt_device_register(&_hw_pin.parent, name, RT_DEVICE_FLAG_RDWR);
 
     return 0;
 }
diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c
index bcdd4db519..8744aa4657 100644
--- a/components/drivers/serial/serial.c
+++ b/components/drivers/serial/serial.c
@@ -279,7 +279,7 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag)
                 serial->config.bufsz);
             RT_ASSERT(rx_fifo != RT_NULL);
             rx_fifo->buffer = (rt_uint8_t*) (rx_fifo + 1);
-            rt_memset(rx_fifo->buffer, 0, RT_SERIAL_RB_BUFSZ);
+            rt_memset(rx_fifo->buffer, 0, serial->config.bufsz);
             rx_fifo->put_index = 0;
             rx_fifo->get_index = 0;
 
diff --git a/components/drivers/src/SConscript b/components/drivers/src/SConscript
index a9bb775427..d70b3fb771 100644
--- a/components/drivers/src/SConscript
+++ b/components/drivers/src/SConscript
@@ -3,6 +3,11 @@ from building import *
 cwd = GetCurrentDir()
 src	= Glob('*.c')
 CPPPATH = [cwd + '/../include']
+
+if GetDepend('RT_USING_HEAP'):
+    SrcRemove(src, 'dataqueue.c')
+    SrcRemove(src, 'pipe.c')
+
 group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_DEVICE_IPC'], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/components/drivers/src/completion.c b/components/drivers/src/completion.c
index f49e44c48f..48afc2ee34 100644
--- a/components/drivers/src/completion.c
+++ b/components/drivers/src/completion.c
@@ -95,10 +95,10 @@ rt_err_t rt_completion_wait(struct rt_completion *completion,
             result = thread->error;
 
             level = rt_hw_interrupt_disable();
-            /* clean completed flag */
-            completion->flag = RT_UNCOMPLETED;
         }
     }
+    /* clean completed flag */
+    completion->flag = RT_UNCOMPLETED;
 
 __exit:
     rt_hw_interrupt_enable(level);
diff --git a/include/rtdef.h b/include/rtdef.h
index 78a5642058..4c3581b91a 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -776,6 +776,11 @@ enum rt_device_class_type
 #define RT_DEVICE_FLAG_SUSPENDED        0x020           /**< device is suspended */
 #define RT_DEVICE_FLAG_STREAM           0x040           /**< stream mode */
 
+#define RT_DEVICE_CTRL_CONFIG           0x03    	/* configure device */
+#define RT_DEVICE_CTRL_SET_INT          0x10    	/* enable receive irq */
+#define RT_DEVICE_CTRL_CLR_INT          0x11    	/* disable receive irq */
+#define RT_DEVICE_CTRL_GET_INT          0x12
+
 #define RT_DEVICE_FLAG_INT_RX           0x100           /**< INT mode on Rx */
 #define RT_DEVICE_FLAG_DMA_RX           0x200           /**< DMA mode on Rx */
 #define RT_DEVICE_FLAG_INT_TX           0x400           /**< INT mode on Tx */