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| author | chinesebear <[email protected]> | 2016-04-19 22:08:23 +0800 |
|---|---|---|
| committer | chinesebear <[email protected]> | 2016-04-19 22:08:23 +0800 |
| commit | 86216ceeccb95a86a8e08b2230c4f0dcf6fb69de (patch) | |
| tree | ab5b0e125ac7fa84f8254efe4cdbb2db54a02c49 | |
| parent | c8c4d2edcf3fa8a7c3fab5b317faed223468904e (diff) | |
start exception by chinesebear
| -rw-r--r-- | libcpu/mips/loongson_1c/context_gcc.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S index ce004dc716..1ac2747747 100644 --- a/libcpu/mips/loongson_1c/context_gcc.S +++ b/libcpu/mips/loongson_1c/context_gcc.S @@ -36,7 +36,14 @@ rt_hw_interrupt_disable: */ .globl rt_hw_interrupt_enable rt_hw_interrupt_enable: + ori a0, 0x00000800 mtc0 a0, CP0_STATUS + ehb + mfc0 v0, CP0_CAUSE + ehb + or v1, v0, 0x800000 //EBASE + 0x200 + mtc0 v1, CP0_CAUSE + ehb jr ra nop |