[libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释

34 files changed, 9 insertions, 1 deletions

diff --git a/bsp/wch/risc-v/Libraries/Kconfig b/bsp/wch/risc-v/Libraries/Kconfig
index 298f56a9aa..6dad90ac06 100644
--- a/bsp/wch/risc-v/Libraries/Kconfig
+++ b/bsp/wch/risc-v/Libraries/Kconfig
@@ -14,6 +14,7 @@ config SOC_RISCV_SERIES_CH32V2
 config SOC_RISCV_SERIES_CH32V3
     bool
     select ARCH_RISCV
+    select ARCH_RISCV_FPU
     select SOC_RISCV_FAMILY_CH32
 
 config SOC_FAMILY_CH56X
diff --git a/bsp/wch/risc-v/ch32v208v-r0/.config b/bsp/wch/risc-v/ch32v208w-r0/.config
index 30fd17be0e..30fd17be0e 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/.config
+++ b/bsp/wch/risc-v/ch32v208w-r0/.config
diff --git a/bsp/wch/risc-v/ch32v208v-r0/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/Kconfig
index c80a8958fd..c80a8958fd 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/Kconfig
+++ b/bsp/wch/risc-v/ch32v208w-r0/Kconfig
diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConscript b/bsp/wch/risc-v/ch32v208w-r0/SConscript
index 20f7689c53..20f7689c53 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/SConscript
+++ b/bsp/wch/risc-v/ch32v208w-r0/SConscript
diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConstruct b/bsp/wch/risc-v/ch32v208w-r0/SConstruct
index 1c21f19f0a..1c21f19f0a 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/SConstruct
+++ b/bsp/wch/risc-v/ch32v208w-r0/SConstruct
diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript b/bsp/wch/risc-v/ch32v208w-r0/applications/SConscript
index 9bb9abae89..9bb9abae89 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript
+++ b/bsp/wch/risc-v/ch32v208w-r0/applications/SConscript
diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/main.c b/bsp/wch/risc-v/ch32v208w-r0/applications/main.c
index 3246340a93..3246340a93 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/applications/main.c
+++ b/bsp/wch/risc-v/ch32v208w-r0/applications/main.c
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig
index 613551495b..613551495b 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/SConscript b/bsp/wch/risc-v/ch32v208w-r0/board/SConscript
index bc8e7636f1..bc8e7636f1 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/board/SConscript
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/SConscript
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.c b/bsp/wch/risc-v/ch32v208w-r0/board/board.c
index 197c3c66ad..197c3c66ad 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/board/board.c
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/board.c
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.h b/bsp/wch/risc-v/ch32v208w-r0/board/board.h
index 9086e24c4e..9086e24c4e 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/board/board.h
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/board.h
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
index b0051ab14d..b0051ab14d 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds
+++ b/bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/ch32v208.png b/bsp/wch/risc-v/ch32v208w-r0/figures/ch32v208.png
index 752edca1d6..752edca1d6 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/ch32v208.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/ch32v208.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/config.png b/bsp/wch/risc-v/ch32v208w-r0/figures/config.png
index f74e8705f8..f74e8705f8 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/config.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/config.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/dist.png b/bsp/wch/risc-v/ch32v208w-r0/figures/dist.png
index d190d816fb..d190d816fb 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/dist.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/dist.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/end.png b/bsp/wch/risc-v/ch32v208w-r0/figures/end.png
index ff49a943b4..ff49a943b4 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/end.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/end.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/import.png b/bsp/wch/risc-v/ch32v208w-r0/figures/import.png
index eaf0f2213d..eaf0f2213d 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/import.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/import.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/prefix.png b/bsp/wch/risc-v/ch32v208w-r0/figures/prefix.png
index 9542d60a29..9542d60a29 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/prefix.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/prefix.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/scons.png b/bsp/wch/risc-v/ch32v208w-r0/figures/scons.png
index 683dc33ab1..683dc33ab1 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/scons.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/scons.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/sconscompile.jpg b/bsp/wch/risc-v/ch32v208w-r0/figures/sconscompile.jpg
index 2460567f48..2460567f48 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/sconscompile.jpg
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/sconscompile.jpg
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/set.png b/bsp/wch/risc-v/ch32v208w-r0/figures/set.png
index 573a45c34e..573a45c34e 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/set.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/set.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/success.png b/bsp/wch/risc-v/ch32v208w-r0/figures/success.png
index c5d399d150..c5d399d150 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/success.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/success.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/tool.png b/bsp/wch/risc-v/ch32v208w-r0/figures/tool.png
index 94c5aec257..94c5aec257 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/tool.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/tool.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/toolchain.png b/bsp/wch/risc-v/ch32v208w-r0/figures/toolchain.png
index 610e67cc91..610e67cc91 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/toolchain.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/toolchain.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/toolset.png b/bsp/wch/risc-v/ch32v208w-r0/figures/toolset.png
index 3fd87da63f..3fd87da63f 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/toolset.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/toolset.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/vscode-terminal.png b/bsp/wch/risc-v/ch32v208w-r0/figures/vscode-terminal.png
index a227260d84..a227260d84 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/vscode-terminal.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/vscode-terminal.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/windows.png b/bsp/wch/risc-v/ch32v208w-r0/figures/windows.png
index 5deed9009e..5deed9009e 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/figures/windows.png
+++ b/bsp/wch/risc-v/ch32v208w-r0/figures/windows.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/README_zh.md b/bsp/wch/risc-v/ch32v208w-r0/readme.md
index 18eb07552b..18eb07552b 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/README_zh.md
+++ b/bsp/wch/risc-v/ch32v208w-r0/readme.md
diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h
index 394d127847..394d127847 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h
+++ b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.h
diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.py
index 93507a7f8d..93507a7f8d 100644
--- a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py
+++ b/bsp/wch/risc-v/ch32v208w-r0/rtconfig.py
diff --git a/libcpu/risc-v/ch32/context_gcc.S b/libcpu/risc-v/ch32/context_gcc.S
index 3d6af17934..5e6567a79f 100644
--- a/libcpu/risc-v/ch32/context_gcc.S
+++ b/libcpu/risc-v/ch32/context_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include "cpuport.h"
diff --git a/libcpu/risc-v/ch32/cpuport.c b/libcpu/risc-v/ch32/cpuport.c
index e42bab949e..c1c609c58d 100644
--- a/libcpu/risc-v/ch32/cpuport.c
+++ b/libcpu/risc-v/ch32/cpuport.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include <rthw.h>
diff --git a/libcpu/risc-v/ch32/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S
index 96c61ddd33..4d16a5b054 100644
--- a/libcpu/risc-v/ch32/interrupt_gcc.S
+++ b/libcpu/risc-v/ch32/interrupt_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
  
 #include "cpuport.h"
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index e458268e11..dbb5f8f4b5 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -8,6 +8,7 @@
  * 2018/10/28     Bernard      The unify RISC-V porting implementation
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
+ * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
  */
 
 #define __ASSEMBLY__
@@ -212,8 +213,11 @@ rt_hw_context_switch_exit:
     csrw mepc, a0
 
     LOAD x1,   1 * REGBYTES(sp)
-
+    #ifdef ARCH_RISCV_FPU
     li    t0, 0x00007800
+    #else
+    li    t0, 0x00001800
+    #endif
     csrw  mstatus, t0
     LOAD a0,   2 * REGBYTES(sp)
     csrs mstatus, a0