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authorwuyangyong <[email protected]>2011-06-15 15:21:44 +0000
committerwuyangyong <[email protected]>2011-06-15 15:21:44 +0000
commita8f412bca66a157036e35f602e56d1f70f34a6c3 (patch)
tree7a606672fc3b6d125205e71c77765e07b3686011
parentaa31ef7377a4650bf02061b844f2971bfd08cf7a (diff)
update stm32f10x
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1517 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat
-rw-r--r--bsp/stm32f10x/Libraries/SConscript28
-rw-r--r--bsp/stm32f10x/SConscript8
-rw-r--r--bsp/stm32f10x/SConstruct2
-rw-r--r--bsp/stm32f10x/project.Uv237
-rw-r--r--bsp/stm32f10x/serial.c418
-rw-r--r--bsp/stm32f10x/serial.h70
-rw-r--r--bsp/stm32f10x/stm32f10x_it.c42
-rw-r--r--bsp/stm32f10x/system_stm32f10x.c1033
8 files changed, 542 insertions, 1096 deletions
diff --git a/bsp/stm32f10x/Libraries/SConscript b/bsp/stm32f10x/Libraries/SConscript
index 7b86f60d1f..5b1415c1d1 100644
--- a/bsp/stm32f10x/Libraries/SConscript
+++ b/bsp/stm32f10x/Libraries/SConscript
@@ -5,6 +5,7 @@ from building import *
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/CM3/CoreSupport/core_cm3.c
+CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
@@ -30,11 +31,30 @@ STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
STM32F10x_StdPeriph_Driver/src/misc.c
""")
-path = [RTT_ROOT + '/bsp/stm3210/Libraries/STM32F10x_StdPeriph_Driver/inc',
- RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/CoreSupport',
- RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
+# starupt scripts for each STM32 kind
+startup_scripts = {}
+startup_scripts['STM32F10X_CL'] = 'startup_stm32f10x_cl.s'
+startup_scripts['STM32F10X_HD'] = 'startup_stm32f10x_hd.s'
+startup_scripts['STM32F10X_HD_VL'] = 'startup_stm32f10x_hd_vl.s'
+startup_scripts['STM32F10X_LD'] = 'startup_stm32f10x_ld.s'
+startup_scripts['STM32F10X_LD_VL'] = 'startup_stm32f10x_ld_vl.s'
+startup_scripts['STM32F10X_MD'] = 'startup_stm32f10x_md.s'
+startup_scripts['STM32F10X_MD_VL'] = 'startup_stm32f10x_md_vl.s'
+startup_scripts['STM32F10X_XL'] = 'startup_stm32f10x_xl.s'
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
+
+path = [RTT_ROOT + '/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc',
+ RTT_ROOT + '/bsp/stm32f10x/Libraries/CMSIS/CM3/CoreSupport',
+ RTT_ROOT + '/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
-group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path)
+group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
diff --git a/bsp/stm32f10x/SConscript b/bsp/stm32f10x/SConscript
index 415bc95572..cb67d7eece 100644
--- a/bsp/stm32f10x/SConscript
+++ b/bsp/stm32f10x/SConscript
@@ -2,8 +2,8 @@ import rtconfig
Import('RTT_ROOT')
from building import *
-src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c', 'system_stm32f10x.c']
-src_drv = ['rtc.c', 'usart.c', 'led.c']
+src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c']
+src_drv = ['rtc.c', 'usart.c', 'serial.c', 'led.c']
if GetDepend('RT_USING_DFS'):
if rtconfig.STM32_TYPE == 'STM32F10X_HD':
@@ -18,8 +18,8 @@ if GetDepend('RT_USING_LWIP'):
src_drv += ['enc28j60.c']
src = src_bsp + src_drv
-CPPPATH = [RTT_ROOT + '/bsp/stm3210']
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
+CPPPATH = [RTT_ROOT + '/bsp/stm32f10x']
+CPPDEFINES = []
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
diff --git a/bsp/stm32f10x/SConstruct b/bsp/stm32f10x/SConstruct
index 51d464b6be..a3183352d2 100644
--- a/bsp/stm32f10x/SConstruct
+++ b/bsp/stm32f10x/SConstruct
@@ -26,7 +26,7 @@ Export('rtconfig')
objs = PrepareBuilding(env, RTT_ROOT)
# STM32 firemare library building script
-objs = objs + SConscript(RTT_ROOT + '/bsp/stm3210/Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
+objs = objs + SConscript(RTT_ROOT + '/bsp/stm32f10x/Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
# build program
env.Program(TARGET, objs)
diff --git a/bsp/stm32f10x/project.Uv2 b/bsp/stm32f10x/project.Uv2
index 9e142dccb2..67b94b2083 100644
--- a/bsp/stm32f10x/project.Uv2
+++ b/bsp/stm32f10x/project.Uv2
@@ -15,9 +15,9 @@ File 1,1,<.\application.c><application.c>
File 1,1,<.\startup.c><startup.c>
File 1,1,<.\board.c><board.c>
File 1,1,<.\stm32f10x_it.c><stm32f10x_it.c>
-File 1,1,<.\system_stm32f10x.c><system_stm32f10x.c>
File 1,1,<.\rtc.c><rtc.c>
File 1,1,<.\usart.c><usart.c>
+File 1,1,<.\serial.c><serial.c>
File 1,1,<.\led.c><led.c>
File 1,1,<.\sdcard.c><sdcard.c>
File 1,1,<.\enc28j60.c><enc28j60.c>
@@ -36,14 +36,8 @@ File 2,1,<..\..\src\scheduler.c><scheduler.c>
File 2,1,<..\..\src\slab.c><slab.c>
File 2,1,<..\..\src\thread.c><thread.c>
File 2,1,<..\..\src\timer.c><timer.c>
-File 3,1,<..\..\libcpu\arm\stm32\cpu.c><cpu.c>
-File 3,1,<..\..\libcpu\arm\stm32\fault.c><fault.c>
-File 3,1,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c>
-File 3,1,<..\..\libcpu\arm\stm32\serial.c><serial.c>
-File 3,1,<..\..\libcpu\arm\stm32\stack.c><stack.c>
+File 3,1,<..\..\libcpu\arm\stm32\cpuport.c><cpuport.c>
File 3,2,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S>
-File 3,2,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S>
-File 3,2,<..\..\libcpu\arm\stm32\start_rvds.S><start_rvds.S>
File 3,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
File 3,1,<..\..\libcpu\arm\common\div0.c><div0.c>
File 3,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
@@ -97,30 +91,12 @@ File 6,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip.c><ip.c>
File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c><asn1_dec.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c><asn1_enc.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\mib2.c><mib2.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c><mib_structs.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c><msg_in.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c><msg_out.c>
File 6,1,<..\..\components\net\lwip\src\netif\etharp.c><etharp.c>
File 6,1,<..\..\components\net\lwip\src\netif\ethernetif.c><ethernetif.c>
File 6,1,<..\..\components\net\lwip\src\netif\loopif.c><loopif.c>
File 6,1,<..\..\components\net\lwip\src\netif\slipif.c><slipif.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\auth.c><auth.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\chap.c><chap.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\chpms.c><chpms.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\fsm.c><fsm.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ipcp.c><ipcp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\lcp.c><lcp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\magic.c><magic.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\md5.c><md5.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\pap.c><pap.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ppp.c><ppp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ppp_oe.c><ppp_oe.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\randm.c><randm.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\vj.c><vj.c>
File 7,1,<Libraries\CMSIS\CM3\CoreSupport\core_cm3.c><core_cm3.c>
+File 7,1,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c><system_stm32f10x.c>
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c>
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
@@ -144,6 +120,7 @@ File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dm
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c>
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c><stm32f10x_cec.c>
File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c>
+File 7,2,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s><startup_stm32f10x_hd.s>
Options 1,0,0 // Target 'RT-Thread STM32'
@@ -178,7 +155,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
GenHex=0
Debug=1
Browse=0
- LstDir (.\obj\)
+ LstDir (.\)
HexSel=1
MG32K=0
TGMORE=0
@@ -204,7 +181,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
ADSCMISC ()
ADSCDEFN (STM32F10X_HD, USE_STDPERIPH_DRIVER)
ADSCUDEF ()
- ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\CoreSupport;..\..\components\dfs;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\arch\include;..\..\components\dfs\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\net\lwip\src\netif\ppp;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x)
+ ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\CoreSupport;..\..\components\dfs;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\arch\include;..\..\components\dfs\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
@@ -229,7 +206,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
- OPTDBG 49150,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
+ OPTDBG 49149,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
FLASH1 { 1,0,0,0,1,0,0,0,6,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (Segger\JL2CM3.dll)
FLASH3 ("" ())
diff --git a/bsp/stm32f10x/serial.c b/bsp/stm32f10x/serial.c
new file mode 100644
index 0000000000..13bf961e20
--- /dev/null
+++ b/bsp/stm32f10x/serial.c
@@ -0,0 +1,418 @@
+/*
+ * File : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-02-05 Bernard first version
+ * 2009-10-25 Bernard fix rt_serial_read bug when there is no data
+ * in the buffer.
+ * 2010-03-29 Bernard cleanup code.
+ */
+
+#include "serial.h"
+#include <stm32f10x_dma.h>
+#include <stm32f10x_usart.h>
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+ rt_uint32_t address, rt_uint32_t size);
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
+
+ if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+ {
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_memset(uart->int_rx->rx_buffer, 0,
+ sizeof(uart->int_rx->rx_buffer));
+ uart->int_rx->read_index = 0;
+ uart->int_rx->save_index = 0;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
+ uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+
+ /* init data node memory pool */
+ rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
+ uart->dma_tx->data_node_mem_pool,
+ sizeof(uart->dma_tx->data_node_mem_pool),
+ sizeof(struct stm32_serial_data_node));
+ }
+
+ /* Enable USART */
+ USART_Cmd(uart->uart_device, ENABLE);
+
+ dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
+
+ ptr = buffer;
+ err_code = RT_EOK;
+ uart = (struct stm32_serial_device*)dev->user_data;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* interrupt mode Rx */
+ while (size)
+ {
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ if (uart->int_rx->read_index != uart->int_rx->save_index)
+ {
+ /* read a character */
+ *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+ size--;
+
+ /* move to next position */
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+ else
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ *ptr = uart->uart_device->DR & 0xff;
+ ptr ++;
+ }
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+ rt_uint32_t address, rt_uint32_t size)
+{
+ RT_ASSERT(dma_channel != RT_NULL);
+
+ /* disable DMA */
+ DMA_Cmd(dma_channel, DISABLE);
+
+ /* set buffer address */
+ dma_channel->CMAR = address;
+ /* set size */
+ dma_channel->CNDTR = size;
+
+ /* enable DMA */
+ DMA_Cmd(dma_channel, ENABLE);
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct stm32_serial_device* uart;
+
+ err_code = RT_EOK;
+ ptr = (rt_uint8_t*)buffer;
+ uart = (struct stm32_serial_device*)dev->user_data;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /* interrupt mode Tx, does not support */
+ RT_ASSERT(0);
+ }
+ else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ /* DMA mode Tx */
+
+ /* allocate a data node */
+ struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
+ rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
+ if (data_node == RT_NULL)
+ {
+ /* set error code */
+ err_code = -RT_ENOMEM;
+ }
+ else
+ {
+ rt_uint32_t level;
+
+ /* fill data node */
+ data_node->data_ptr = ptr;
+ data_node->data_size = size;
+
+ /* insert to data link */
+ data_node->next = RT_NULL;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ data_node->prev = uart->dma_tx->list_tail;
+ if (uart->dma_tx->list_tail != RT_NULL)
+ uart->dma_tx->list_tail->next = data_node;
+ uart->dma_tx->list_tail = data_node;
+
+ if (uart->dma_tx->list_head == RT_NULL)
+ {
+ /* start DMA to transmit data */
+ uart->dma_tx->list_head = data_node;
+
+ /* Enable DMA Channel */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+ uart->dma_tx->list_head->data_size);
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ if (dev->flag & RT_DEVICE_FLAG_STREAM)
+ {
+ /* stream mode */
+ while (size)
+ {
+ if (*ptr == '\n')
+ {
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = '\r';
+ }
+
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = (*ptr & 0x1FF);
+
+ ++ptr; --size;
+ }
+ }
+ else
+ {
+ /* write data directly */
+ while (size)
+ {
+ while (!(uart->uart_device->SR & USART_FLAG_TXE));
+ uart->uart_device->DR = (*ptr & 0x1FF);
+
+ ++ptr; --size;
+ }
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ struct stm32_serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ uart = (struct stm32_serial_device*)dev->user_data;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_SUSPEND:
+ /* suspend device */
+ dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, DISABLE);
+ break;
+
+ case RT_DEVICE_CTRL_RESUME:
+ /* resume device */
+ dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+ USART_Cmd(uart->uart_device, ENABLE);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/*
+ * serial register for STM32
+ * support STM32F103VB and STM32F103ZE
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
+{
+ RT_ASSERT(device != RT_NULL);
+
+ if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+ (flag & RT_DEVICE_FLAG_INT_TX))
+ {
+ RT_ASSERT(0);
+ }
+
+ device->type = RT_Device_Class_Char;
+ device->rx_indicate = RT_NULL;
+ device->tx_complete = RT_NULL;
+ device->init = rt_serial_init;
+ device->open = rt_serial_open;
+ device->close = rt_serial_close;
+ device->read = rt_serial_read;
+ device->write = rt_serial_write;
+ device->control = rt_serial_control;
+ device->user_data = serial;
+
+ /* register a character device */
+ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+ if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+ {
+ /* interrupt mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+ /* save on rx buffer */
+ while (uart->uart_device->SR & USART_FLAG_RXNE)
+ {
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ /* save character */
+ uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
+ uart->int_rx->save_index ++;
+ if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->save_index = 0;
+
+ /* if the next position is read index, discard this 'read char' */
+ if (uart->int_rx->save_index == uart->int_rx->read_index)
+ {
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ {
+ rt_size_t rx_length;
+
+ /* get rx length */
+ rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+ UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+ uart->int_rx->save_index - uart->int_rx->read_index;
+
+ device->rx_indicate(device, rx_length);
+ }
+ }
+
+ if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+ {
+ /* clear interrupt */
+ USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+ }
+}
+
+/*
+ * ISR for DMA mode Tx
+ */
+void rt_hw_serial_dma_tx_isr(rt_device_t device)
+{
+ rt_uint32_t level;
+ struct stm32_serial_data_node* data_node;
+ struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+ /* DMA mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+
+ /* get the first data node */
+ data_node = uart->dma_tx->list_head;
+ RT_ASSERT(data_node != RT_NULL);
+
+ /* invoke call to notify tx complete */
+ if (device->tx_complete != RT_NULL)
+ device->tx_complete(device, data_node->data_ptr);
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ /* remove list head */
+ uart->dma_tx->list_head = data_node->next;
+ if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
+ uart->dma_tx->list_tail = RT_NULL;
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+
+ /* release data node memory */
+ rt_mp_free(data_node);
+
+ if (uart->dma_tx->list_head != RT_NULL)
+ {
+ /* transmit next data node */
+ rt_serial_enable_dma(uart->dma_tx->dma_channel,
+ (rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+ uart->dma_tx->list_head->data_size);
+ }
+ else
+ {
+ /* no data to be transmitted, disable DMA */
+ DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+ }
+}
+
+/*@}*/
diff --git a/bsp/stm32f10x/serial.h b/bsp/stm32f10x/serial.h
new file mode 100644
index 0000000000..6dc175367c
--- /dev/null
+++ b/bsp/stm32f10x/serial.h
@@ -0,0 +1,70 @@
+/*
+ * File : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-01-05 Bernard first version
+ * 2010-03-29 Bernard remove interrupt tx and DMA rx mode.
+ */
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/* STM32F10x library definitions */
+#include <stm32f10x.h>
+
+#define UART_RX_BUFFER_SIZE 64
+#define UART_TX_DMA_NODE_SIZE 4
+
+/* data node for Tx Mode */
+struct stm32_serial_data_node
+{
+ rt_uint8_t *data_ptr;
+ rt_size_t data_size;
+ struct stm32_serial_data_node *next, *prev;
+};
+struct stm32_serial_dma_tx
+{
+ /* DMA Channel */
+ DMA_Channel_TypeDef* dma_channel;
+
+ /* data list head and tail */
+ struct stm32_serial_data_node *list_head, *list_tail;
+
+ /* data node memory pool */
+ struct rt_mempool data_node_mp;
+ rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
+ (sizeof(struct stm32_serial_data_node) + sizeof(void*))];
+};
+
+struct stm32_serial_int_rx
+{
+ rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
+ rt_uint32_t read_index, save_index;
+};
+
+struct stm32_serial_device
+{
+ USART_TypeDef* uart_device;
+
+ /* rx structure */
+ struct stm32_serial_int_rx* int_rx;
+
+ /* tx structure */
+ struct stm32_serial_dma_tx* dma_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_dma_tx_isr(rt_device_t device);
+
+#endif
diff --git a/bsp/stm32f10x/stm32f10x_it.c b/bsp/stm32f10x/stm32f10x_it.c
index 558afa9c1a..41d62d9c6b 100644
--- a/bsp/stm32f10x/stm32f10x_it.c
+++ b/bsp/stm32f10x/stm32f10x_it.c
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file Project/Template/stm32f10x_it.c
+ * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
* @author MCD Application Team
- * @version V3.1.0
- * @date 06/19/2009
+ * @version V3.5.0
+ * @date 08-April-2011
* @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
+ * This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
- * @copy
+ * @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -17,8 +17,9 @@
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
- * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
- */
+ * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
@@ -50,19 +51,6 @@ void NMI_Handler(void)
}
/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
@@ -119,6 +107,12 @@ void DebugMon_Handler(void)
{
}
+void SysTick_Handler(void)
+{
+ extern void rt_hw_timer_handler(void);
+ rt_hw_timer_handler();
+}
+
/******************************************************************************/
/* STM32F10x Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
@@ -168,7 +162,7 @@ void USART1_IRQHandler(void)
#ifdef RT_USING_UART1
extern struct rt_device uart1_device;
extern void rt_hw_serial_isr(struct rt_device *device);
-
+
/* enter interrupt */
rt_interrupt_enter();
@@ -260,10 +254,10 @@ void SDIO_IRQHandler(void)
void ETH_IRQHandler(void)
{
extern void rt_hw_stm32_eth_isr(void);
-
+
/* enter interrupt */
rt_interrupt_enter();
-
+
rt_hw_stm32_eth_isr();
/* leave interrupt */
@@ -324,7 +318,7 @@ void EXTI9_5_IRQHandler(void)
/**
* @}
- */
+ */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f10x/system_stm32f10x.c b/bsp/stm32f10x/system_stm32f10x.c
deleted file mode 100644
index 50af0dc3f6..0000000000
--- a/bsp/stm32f10x/system_stm32f10x.c
+++ /dev/null
@@ -1,1033 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.c
- * @author MCD Application Team
- * @version V3.4.0
- * @date 10/15/2010
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- ******************************************************************************
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/** @addtogroup STM32F10x_System_Private_Includes
- * @{
- */
-
-#include "stm32f10x.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For Low, Medium and High density Value line devices an external 8MHz
- crystal is used to drive the System clock.
- - For Low, Medium and High density devices an external 8MHz crystal is
- used to drive the System clock.
- - For Connectivity line devices an external 25MHz crystal is used to drive
- the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
- */
-
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
- #define SYSCLK_FREQ_24MHz 24000000
-#else
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
- STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x100. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
- uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
- uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
- static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
- static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
- static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
- static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
- static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
- RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * @note None
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef STM32F10X_CL
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#ifndef STM32F10X_CL
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18;
-
- if (pllmull != 0x0D)
- {
- pllmull += 2;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
- }
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-
- if (prediv1source == 0)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F10X_CL */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f10x_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
-
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
-
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
-
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x44444B44;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4] = 0x00001011;
- FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
- if (HSE_VALUE <= 24000000)
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
- }
- else
- {
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
- }
-#endif /* STM32F10X_CL */
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 0 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL7);
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 2 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL9);
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 11:37:10 +0000