[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 (#6780)

【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件

100 files changed, 25076 insertions, 675 deletions

diff --git a/bsp/wch/risc-v/Libraries/Kconfig b/bsp/wch/risc-v/Libraries/Kconfig
index 70931c692b..298f56a9aa 100644
--- a/bsp/wch/risc-v/Libraries/Kconfig
+++ b/bsp/wch/risc-v/Libraries/Kconfig
@@ -5,6 +5,11 @@ config SOC_RISCV_SERIES_CH32V1
     bool
     select ARCH_RISCV
     select SOC_RISCV_FAMILY_CH32
+    
+config SOC_RISCV_SERIES_CH32V2
+    bool
+    select ARCH_RISCV
+    select SOC_RISCV_FAMILY_CH32
 	
 config SOC_RISCV_SERIES_CH32V3
     bool
diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c
index d4a925c6ae..4495a0c2b1 100644
--- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c
@@ -431,12 +431,21 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
     pin_irq_hdr(bit2bitno(GPIO_Pin));
 }
 
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void EXTI0_IRQHandler(void) __attribute__((interrupt()));
+void EXTI1_IRQHandler(void) __attribute__((interrupt()));
+void EXTI2_IRQHandler(void) __attribute__((interrupt()));
+void EXTI3_IRQHandler(void) __attribute__((interrupt()));
+void EXTI4_IRQHandler(void) __attribute__((interrupt()));
+void EXTI9_5_IRQHandler(void) __attribute__((interrupt()));
+#else
 void EXTI0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 void EXTI1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 void EXTI2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 void EXTI3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 void EXTI4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 void EXTI9_5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 
 void EXTI0_IRQHandler(void)
 {
diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.c
index e409acc637..dd79dda1a3 100644
--- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.c
+++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.c
@@ -369,7 +369,11 @@ static const struct rt_uart_ops ch32_uart_ops =
 };
 
 #ifdef BSP_USING_UART1
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART1_IRQHandler(void) __attribute__((interrupt()));
+#else
 void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void USART1_IRQHandler(void)
 {
     GET_INT_SP();
@@ -381,7 +385,11 @@ void USART1_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART2
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART2_IRQHandler(void) __attribute__((interrupt()));
+#else
 void USART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void USART2_IRQHandler(void)
 {
     GET_INT_SP();
@@ -393,7 +401,11 @@ void USART2_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART3
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART3_IRQHandler(void) __attribute__((interrupt()));
+#else
 void USART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void USART3_IRQHandler(void)
 {
     GET_INT_SP();
@@ -405,7 +417,11 @@ void USART3_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART4
-void UART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART4_IRQHandler(void) __attribute__((interrupt()));
+#else
+void USART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void UART4_IRQHandler(void)
 {
     GET_INT_SP();
@@ -417,7 +433,11 @@ void UART4_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART5
-void UART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART5_IRQHandler(void) __attribute__((interrupt()));
+#else
+void USART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void UART5_IRQHandler(void)
 {
     GET_INT_SP();
@@ -429,7 +449,11 @@ void UART5_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART6
-void UART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART6_IRQHandler(void) __attribute__((interrupt()));
+#else
+void USART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void UART6_IRQHandler(void)
 {
     GET_INT_SP();
@@ -441,7 +465,11 @@ void UART6_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART7
-void UART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART7_IRQHandler(void) __attribute__((interrupt()));
+#else
+void USART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void UART7_IRQHandler(void)
 {
     GET_INT_SP();
@@ -453,7 +481,11 @@ void UART7_IRQHandler(void)
 #endif
 
 #ifdef BSP_USING_UART8
-void UART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#if defined (SOC_RISCV_SERIES_CH32V2)
+void USART8_IRQHandler(void) __attribute__((interrupt()));
+#else
+void USART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+#endif
 void UART8_IRQHandler(void)
 {
     GET_INT_SP();
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/.ignore_format.yml b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/.ignore_format.yml
new file mode 100644
index 0000000000..4114abf9b5
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/.ignore_format.yml
@@ -0,0 +1,7 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- bmsis
+- ch32v208_hal
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/SConscript b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/SConscript
new file mode 100644
index 0000000000..ca95be14e2
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/SConscript
@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/SConscript b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/SConscript
new file mode 100644
index 0000000000..08fcbe8b8c
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/SConscript
@@ -0,0 +1,79 @@
+#-*- encoding: utf-8 -*-
+
+import os
+from building import * 
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#---------------------------------------------------------------------------------
+# Package configuration
+#---------------------------------------------------------------------------------
+PKGNAME = "bmsis"
+VERSION = "v1.0.0"
+DEPENDS = [""]
+#DEPENDS = ["PKG_USING_RW007"]
+
+#---------------------------------------------------------------------------------
+# Compile the configuration 
+#
+# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
+# 
+# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
+# LOCAL_CCFLAGS: Local compilation parameter 
+# LOCAL_ASFLAGS: Local assembly parameters
+# 
+# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH 
+#          is empty # no pass!!!
+# CCFLAGS: Global compilation parameter 
+# ASFLAGS: Global assembly parameters
+#
+# CPPDEFINES: Global macro definition
+# LOCAL_CPPDEFINES: Local macro definition 
+# 
+# LIBS: Specify the static library that need to be linked
+# LIBPATH: Specify the search directory for the library file (.lib/.a)
+#
+# LINKFLAGS: Link options
+#---------------------------------------------------------------------------------
+SOURCES          = Glob("./source/*.c")
+SOURCES          += Glob("./source/startup_ch32v20x_D8W.S")
+
+LOCAL_CPPPATH    = [] 
+LOCAL_CCFLAGS    = "" 
+LOCAL_ASFLAGS    = ""
+
+CPPPATH          = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')] 
+CCFLAGS          = "" 
+ASFLAGS          = ""
+
+CPPDEFINES       = []
+LOCAL_CPPDEFINES = []
+
+LIBS             = [] 
+LIBPATH          = [] 
+
+LINKFLAGS        = "" 
+
+SOURCES_IGNORE   = []
+CPPPATH_IGNORE   = []
+
+#---------------------------------------------------------------------------------
+# Main target
+#---------------------------------------------------------------------------------
+objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS, 
+                   CPPPATH          = CPPPATH, 
+                   CCFLAGS          = CCFLAGS, 
+                   ASFLAGS          = ASFLAGS, 
+                   LOCAL_CPPPATH    = LOCAL_CPPPATH, 
+                   LOCAL_CCFLAGS    = LOCAL_CCFLAGS, 
+                   LOCAL_ASFLAGS    = LOCAL_ASFLAGS, 
+                   CPPDEFINES       = CPPDEFINES, 
+                   LOCAL_CPPDEFINES = LOCAL_CPPDEFINES, 
+                   LIBS             = LIBS, 
+                   LIBPATH          = LIBPATH,
+                   LINKFLAGS        = LINKFLAGS)  
+
+Return("objs") 
+#---------------------------------------------------------------------------------
+# End
+#---------------------------------------------------------------------------------
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_conf.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_conf.h
new file mode 100644
index 0000000000..6142fd8c6a
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_conf.h
@@ -0,0 +1,40 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_it.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_it.h
new file mode 100644
index 0000000000..c750e9be44
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_it.h
@@ -0,0 +1,21 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+#define GET_INT_SP()   asm("csrrw sp,mscratch,sp")
+#define FREE_INT_SP()  asm("csrrw sp,mscratch,sp")
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/core_riscv.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/core_riscv.h
new file mode 100644
index 0000000000..6591159043
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/core_riscv.h
@@ -0,0 +1,327 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : core_riscv.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : RISC-V Core Peripheral Access Layer Header File for CH32V20x
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions     */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint64_t vuc64;  /* Read Only */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint64_t uc64;  /* Read Only */
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int64_t vsc64;  /* Read Only */
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int64_t sc64;  /* Read Only */
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint64_t  vu64;
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint64_t  u64;
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int64_t  vs64;
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int64_t  s64;
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t VTFIDR[4];
+  uint8_t RESERVED0[12];
+  __IO uint32_t VTFADDR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+    __IO u32 CTLR;
+    __IO u32 SR;
+    __IO u64 CNT;
+    __IO u64 CMP;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
+#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+/* risc-v specific functions */
+RV_STATIC_INLINE void __enable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); }
+RV_STATIC_INLINE void __disable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); }
+RV_STATIC_INLINE void __NOP() { __asm volatile ("nop"); }
+
+
+
+/* ##########################   NVIC functions  #################################### */
+
+/*******************************************************************************
+* Function Name  : NVIC_EnableIRQ
+* Description    : Enable Interrupt
+* Input          : IRQn: Interrupt Numbers
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_DisableIRQ
+* Description    : Disable Interrupt
+* Input          : IRQn: Interrupt Numbers
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetStatusIRQ
+* Description    : Get Interrupt Enable State
+* Input          : IRQn: Interrupt Numbers
+* Return         : 1: Interrupt Enable
+*                  0: Interrupt Disable
+*******************************************************************************/
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetPendingIRQ
+* Description    : Get Interrupt Pending State
+* Input          : IRQn: Interrupt Numbers
+* Return         : 1: Interrupt Pending Enable
+*                  0: Interrupt Pending Disable
+*******************************************************************************/
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SetPendingIRQ
+* Description    : Set Interrupt Pending
+* Input          : IRQn: Interrupt Numbers
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_ClearPendingIRQ
+* Description    : Clear Interrupt Pending
+* Input          : IRQn: Interrupt Numbers
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetActive
+* Description    : Get Interrupt Active State
+* Input          : IRQn: Interrupt Numbers
+* Return         : 1: Interrupt Active
+*                  0: Interrupt No Active
+*******************************************************************************/
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SetPriority
+* Description    : Set Interrupt Priority
+* Input          : IRQn: Interrupt Numbers
+*                  priority: bit7:pre-emption priority
+*                            bit6-bit4: subpriority
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*******************************************************************************
+* Function Name  : __WFI
+* Description    : Wait for Interrupt
+* Input          : None
+* Return         : None
+*******************************************************************************/
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);	// wfi
+  asm volatile ("wfi");
+}
+
+/*******************************************************************************
+* Function Name  : __WFE
+* Description    : Wait for Events
+* Input          : None
+* Return         : None
+*******************************************************************************/
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  uint32_t t;
+
+  t = NVIC->SCTLR;
+  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
+  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  asm volatile ("wfi");
+  asm volatile ("wfi");
+}
+
+/*******************************************************************************
+* Function Name  : SetVTFIRQ
+* Description    : Set VTF Interrupt
+* Input          : addr��VTF interrupt service function base address.
+*                  IRQn��Interrupt Numbers
+*                  num��VTF Interrupt Numbers
+*                  NewState: DISABLE or ENABLE
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+  if(num > 3)  return ;
+
+  if (NewState != DISABLE)
+  {
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)|0x1);
+  }
+  else{
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)&(~0x1));
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SystemReset
+* Description    : Initiate a system reset request
+* Input          : None
+* Return         : None
+*******************************************************************************/
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+extern uint32_t __get_SP(void);
+
+
+#endif
+
+
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/debug.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/debug.h
new file mode 100644
index 0000000000..efce13c64a
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/debug.h
@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "stdio.h"
+#include "ch32v20x.h"
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG   DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+
+void Delay_Init(void);
+void Delay_Us (uint32_t n);
+void Delay_Ms (uint32_t n);
+void USART_Printf_Init(uint32_t baudrate);
+
+#endif 
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/system_ch32v20x.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/system_ch32v20x.h
new file mode 100644
index 0000000000..1020832b3f
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/system_ch32v20x.h
@@ -0,0 +1,30 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/ch32v20x_it.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/ch32v20x_it.c
new file mode 100644
index 0000000000..768cf57af6
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/ch32v20x_it.c
@@ -0,0 +1,49 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_it.h"
+#include "board.h"
+#include <rtthread.h>
+void NMI_Handler(void) __attribute__((interrupt()));
+void HardFault_Handler(void) __attribute__((interrupt()));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    rt_kprintf(" NMI Handler\r\n");
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    rt_kprintf(" hardfult\r\n");
+    rt_interrupt_leave();
+    FREE_INT_SP();
+
+}
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/core_riscv.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/core_riscv.c
new file mode 100644
index 0000000000..0a176917be
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/core_riscv.c
@@ -0,0 +1,397 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : core_riscv.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : RISC-V Core Peripheral Access Layer Source File
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/**
+ * @brief  Return the Floating-Point Accrued Exceptions
+ */
+uint32_t __get_FFLAGS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Floating-Point Accrued Exceptions
+ */
+void __set_FFLAGS(uint32_t value)
+{
+  __ASM volatile ("csrw fflags, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Floating-Point Dynamic Rounding Mode
+ */
+uint32_t __get_FRM(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "frm" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Floating-Point Dynamic Rounding Mode
+ */
+void __set_FRM(uint32_t value)
+{
+  __ASM volatile ("csrw frm, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Floating-Point Control and Status Register
+ */
+uint32_t __get_FCSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Floating-Point Control and Status Register
+ */
+void __set_FCSR(uint32_t value)
+{
+  __ASM volatile ("csrw fcsr, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Status Register
+ */
+uint32_t __get_MSTATUS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Status Register
+ */
+void __set_MSTATUS(uint32_t value)
+{
+  __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine ISA Register
+ */
+uint32_t __get_MISA(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine ISA Register
+ */
+void __set_MISA(uint32_t value)
+{
+  __ASM volatile ("csrw misa, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Interrupt Enable Register
+ */
+uint32_t __get_MIE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mie" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine ISA Register
+ */
+void __set_MIE(uint32_t value)
+{
+  __ASM volatile ("csrw mie, %0" : : "r" (value) );
+}
+
+
+/**
+ * @brief  Return the Machine Trap-Vector Base-Address Register
+ */
+uint32_t __get_MTVEC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Trap-Vector Base-Address Register
+ */
+void __set_MTVEC(uint32_t value)
+{
+  __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Seratch Register
+ */
+uint32_t __get_MSCRATCH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Seratch Register
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+  __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Exception Program Register
+ */
+uint32_t __get_MEPC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Exception Program Register
+ */
+void __set_MEPC(uint32_t value)
+{
+  __ASM volatile ("csrw mepc, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Cause Register
+ */
+uint32_t __get_MCAUSE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Cause Register
+ */
+void __set_MCAUSE(uint32_t value)
+{
+  __ASM volatile ("csrw mcause, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Trap Value Register
+ */
+uint32_t __get_MTVAL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Trap Value Register
+ */
+void __set_MTVAL(uint32_t value)
+{
+  __ASM volatile ("csrw mtval, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Machine Interrupt Pending Register
+ */
+uint32_t __get_MIP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mip" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set the Machine Interrupt Pending Register
+ */
+void __set_MIP(uint32_t value)
+{
+  __ASM volatile ("csrw mip, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return Lower 32 bits of Cycle counter
+ */
+uint32_t __get_MCYCLE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set Lower 32 bits of Cycle counter
+ */
+void __set_MCYCLE(uint32_t value)
+{
+  __ASM volatile ("csrw mcycle, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return Upper 32 bits of Cycle counter
+ */
+uint32_t __get_MCYCLEH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set Upper 32 bits of Cycle counter
+ */
+void __set_MCYCLEH(uint32_t value)
+{
+  __ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return Lower 32 bits of Instructions-retired counter
+ */
+uint32_t __get_MINSTRET(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set Lower 32 bits of Instructions-retired counter
+ */
+void __set_MINSTRET(uint32_t value)
+{
+  __ASM volatile ("csrw minstret, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return Upper 32 bits of Instructions-retired counter
+ */
+uint32_t __get_MINSTRETH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Set Upper 32 bits of Instructions-retired counter
+ */
+void __set_MINSTRETH(uint32_t value)
+{
+  __ASM volatile ("csrw minstreth, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return Vendor ID Register
+ */
+uint32_t __get_MVENDORID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Return Machine Architecture ID Register
+ */
+uint32_t __get_MARCHID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Return Machine Implementation ID Register
+ */
+uint32_t __get_MIMPID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Return Hart ID Register
+ */
+uint32_t __get_MHARTID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
+  return (result);
+}
+
+/**
+ * @brief  Return SP Register
+ */
+uint32_t __get_SP(void)
+{
+  uint32_t result;
+
+  asm volatile (
+   "mv %0," "sp"
+   : "=r"(result)
+   :
+ );
+  return (result);
+}
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/debug.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/debug.c
new file mode 100644
index 0000000000..b9ef9b40e6
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/debug.c
@@ -0,0 +1,193 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "debug.h"
+
+static uint8_t  p_us = 0;
+static uint16_t p_ms = 0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+    p_us = SystemCoreClock / 8000000;
+    p_ms = (uint16_t)p_us * 1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_us;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_ms;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+
+#if(DEBUG == DEBUG_UART1)
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART2)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART3)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+
+    USART_InitStructure.USART_BaudRate = baudrate;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if(DEBUG == DEBUG_UART1)
+    USART_Init(USART1, &USART_InitStructure);
+    USART_Cmd(USART1, ENABLE);
+
+#elif(DEBUG == DEBUG_UART2)
+    USART_Init(USART2, &USART_InitStructure);
+    USART_Cmd(USART2, ENABLE);
+
+#elif(DEBUG == DEBUG_UART3)
+    USART_Init(USART3, &USART_InitStructure);
+    USART_Cmd(USART3, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      _write
+ *
+ * @brief   Support Printf Function
+ *
+ * @param   *buf - UART send Data.
+ *          size - Data length
+ *
+ * @return  size: Data length
+ */
+__attribute__((used)) int _write(int fd, char *buf, int size)
+{
+    int i;
+
+    for(i = 0; i < size; i++)
+    {
+#if(DEBUG == DEBUG_UART1)
+        while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+        USART_SendData(USART1, *buf++);
+#elif(DEBUG == DEBUG_UART2)
+        while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+        USART_SendData(USART2, *buf++);
+#elif(DEBUG == DEBUG_UART3)
+        while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
+        USART_SendData(USART3, *buf++);
+#endif
+    }
+
+    return size;
+}
+
+/*********************************************************************
+ * @fn      _sbrk
+ *
+ * @brief   Change the spatial position of data segment.
+ *
+ * @return  size: Data length
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/startup_ch32v20x_D8W.S b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/startup_ch32v20x_D8W.S
new file mode 100644
index 0000000000..565d522bc1
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/startup_ch32v20x_D8W.S
@@ -0,0 +1,285 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8W.s
+;* Author             : WCH
+;* Version            : V1.0.0
+;* Date               : 2021/06/06
+;* Description        : CH32V208x
+;*                    vector table for eclipse toolchain.
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* SPDX-License-Identifier: Apache-2.0
+;*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00100073
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   BB_IRQHandler              /* BLE BB */
+    .word   LLE_IRQHandler             /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   BB_IRQHandler              /* BLE BB */
+    .weak   LLE_IRQHandler             /* BLE LLE */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:  1:  j 1b
+HardFault_Handler:  1:  j 1b
+Ecall_M_Mode_Handler:  1:  j 1b
+Ecall_U_Mode_Handler:  1:  j 1b
+Break_Point_Handler:  1:  j 1b
+SysTick_Handler:  1:  j 1b
+SW_handler:  1:  j 1b
+WWDG_IRQHandler:  1:  j 1b
+PVD_IRQHandler:  1:  j 1b
+TAMPER_IRQHandler:  1:  j 1b
+RTC_IRQHandler:  1:  j 1b
+FLASH_IRQHandler:  1:  j 1b
+RCC_IRQHandler:  1:  j 1b
+EXTI0_IRQHandler:  1:  j 1b
+EXTI1_IRQHandler:  1:  j 1b
+EXTI2_IRQHandler:  1:  j 1b
+EXTI3_IRQHandler:  1:  j 1b
+EXTI4_IRQHandler:  1:  j 1b
+DMA1_Channel1_IRQHandler:  1:  j 1b
+DMA1_Channel2_IRQHandler:  1:  j 1b
+DMA1_Channel3_IRQHandler:  1:  j 1b
+DMA1_Channel4_IRQHandler:  1:  j 1b
+DMA1_Channel5_IRQHandler:  1:  j 1b
+DMA1_Channel6_IRQHandler:  1:  j 1b
+DMA1_Channel7_IRQHandler:  1:  j 1b
+ADC1_2_IRQHandler:  1:  j 1b
+USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
+USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
+CAN1_RX1_IRQHandler:  1:  j 1b
+CAN1_SCE_IRQHandler:  1:  j 1b
+EXTI9_5_IRQHandler:  1:  j 1b
+TIM1_BRK_IRQHandler:  1:  j 1b
+TIM1_UP_IRQHandler:  1:  j 1b
+TIM1_TRG_COM_IRQHandler:  1:  j 1b
+TIM1_CC_IRQHandler:  1:  j 1b
+TIM2_IRQHandler:  1:  j 1b
+TIM3_IRQHandler:  1:  j 1b
+TIM4_IRQHandler:  1:  j 1b
+I2C1_EV_IRQHandler:  1:  j 1b
+I2C1_ER_IRQHandler:  1:  j 1b
+I2C2_EV_IRQHandler:  1:  j 1b
+I2C2_ER_IRQHandler:  1:  j 1b
+SPI1_IRQHandler:  1:  j 1b
+SPI2_IRQHandler:  1:  j 1b
+USART1_IRQHandler:  1:  j 1b
+USART2_IRQHandler:  1:  j 1b
+USART3_IRQHandler:  1:  j 1b
+EXTI15_10_IRQHandler:  1:  j 1b
+RTCAlarm_IRQHandler:  1:  j 1b
+USBWakeUp_IRQHandler:  1:  j 1b
+USBHD_IRQHandler:  1:  j 1b
+USBHDWakeUp_IRQHandler:  1:  j 1b
+ETH_IRQHandler:  1:  j 1b
+ETHWakeUp_IRQHandler:  1:  j 1b
+BB_IRQHandler:  1:  j 1b
+LLE_IRQHandler:  1:  j 1b
+TIM5_IRQHandler:  1:  j 1b
+UART4_IRQHandler:  1:  j 1b
+DMA1_Channel8_IRQHandler:  1:  j 1b
+OSC32KCal_IRQHandler:  1:  j 1b
+OSCWakeUp_IRQHandler:  1:  j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+	/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+    li t0, 0x1f
+    csrw 0xbc0, t0
+
+    /* Enable nested and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+
+    /* Enable interrupt */
+   	li t0, 0x1800           
+   	csrs mstatus, t0
+
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, entry
+	csrw mepc, t0
+	mret
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/system_ch32v20x.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/system_ch32v20x.c
new file mode 100644
index 0000000000..0e8eabc378
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/source/system_ch32v20x.c
@@ -0,0 +1,962 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+//#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/SConscript b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/SConscript
new file mode 100644
index 0000000000..841b6e7ca9
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/SConscript
@@ -0,0 +1,78 @@
+#-*- encoding: utf-8 -*-
+
+import os
+from building import * 
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#---------------------------------------------------------------------------------
+# Package configuration
+#---------------------------------------------------------------------------------
+PKGNAME = "ch32v208_hal"
+VERSION = "v1.0.0"
+DEPENDS = [""]
+
+#---------------------------------------------------------------------------------
+# Compile the configuration 
+#
+# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
+# 
+# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
+# LOCAL_CCFLAGS: Local compilation parameter 
+# LOCAL_ASFLAGS: Local assembly parameters
+# 
+# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH 
+#          is empty # no pass!!!
+# CCFLAGS: Global compilation parameter 
+# ASFLAGS: Global assembly parameters
+#
+# CPPDEFINES: Global macro definition
+# LOCAL_CPPDEFINES: Local macro definition 
+# 
+# LIBS: Specify the static library that need to be linked
+# LIBPATH: Specify the search directory for the library file (.lib/.a)
+#
+# LINKFLAGS: Link options
+#---------------------------------------------------------------------------------
+CWD              = GetCurrentDir()
+SOURCES          = Glob("./source/*.c")
+
+LOCAL_CPPPATH    = [] 
+LOCAL_CCFLAGS    = "" 
+LOCAL_ASFLAGS    = ""
+
+CPPPATH          = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')] 
+CCFLAGS          = "" 
+ASFLAGS          = ""
+
+CPPDEFINES       = []
+LOCAL_CPPDEFINES = []
+
+LIBS             = [] 
+LIBPATH          = []
+
+LINKFLAGS        = "" 
+
+SOURCES_IGNORE   = []
+CPPPATH_IGNORE   = []
+
+#---------------------------------------------------------------------------------
+# Main target
+#---------------------------------------------------------------------------------
+objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS, 
+                   CPPPATH          = CPPPATH, 
+                   CCFLAGS          = CCFLAGS, 
+                   ASFLAGS          = ASFLAGS, 
+                   LOCAL_CPPPATH    = LOCAL_CPPPATH, 
+                   LOCAL_CCFLAGS    = LOCAL_CCFLAGS, 
+                   LOCAL_ASFLAGS    = LOCAL_ASFLAGS, 
+                   CPPDEFINES       = CPPDEFINES, 
+                   LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
+                   LIBS             = LIBS, 
+                   LIBPATH          = LIBPATH, 
+                   LINKFLAGS        = LINKFLAGS)  
+
+Return("objs") 
+#---------------------------------------------------------------------------------
+# End
+#---------------------------------------------------------------------------------
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x.h
new file mode 100644
index 0000000000..6e6045c0f7
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x.h
@@ -0,0 +1,4817 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer Header File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_H
+#define __CH32V20x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
+//#define CH32V20x_D6              /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 */
+//#define CH32V20x_D8              /* CH32V203RBT6 */
+#define CH32V20x_D8W               /* CH32V208 */
+
+#endif
+
+#define __MPU_PRESENT             0                   /* Other CH32 devices does not provide an MPU */
+#define __Vendor_SysTickConfig    0                   /* Set to 1 if different SysTick Config is used */
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+  #define HSE_VALUE    ((uint32_t)32000000) /* Value of the External oscillator in Hz */
+#else
+  #define HSE_VALUE    ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+#endif
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT    ((uint16_t)0x1000) /* Time out for HSE start up */
+
+#define HSI_VALUE              ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
+/* Interrupt Number Definition, according to the selected device */
+typedef enum IRQn
+{
+    /******  RISC-V Processor Exceptions Numbers *******************************************************/
+    NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt                             */
+    EXC_IRQn = 3,            /* 3 Exception Interrupt                                */
+    Ecall_M_Mode_IRQn = 5,   /* 5 Ecall M Mode Interrupt                             */
+    Ecall_U_Mode_IRQn = 8,   /* 8 Ecall U Mode Interrupt                             */
+    Break_Point_IRQn = 9,    /* 9 Break Point Interrupt                              */
+    SysTicK_IRQn = 12,       /* 12 System timer Interrupt                            */
+    Software_IRQn = 14,      /* 14 software Interrupt                                */
+
+    /******  RISC-V specific Interrupt Numbers *********************************************************/
+    WWDG_IRQn = 16,            /* Window WatchDog Interrupt                            */
+    PVD_IRQn = 17,             /* PVD through EXTI Line detection Interrupt            */
+    TAMPER_IRQn = 18,          /* Tamper Interrupt                                     */
+    RTC_IRQn = 19,             /* RTC global Interrupt                                 */
+    FLASH_IRQn = 20,           /* FLASH global Interrupt                               */
+    RCC_IRQn = 21,             /* RCC global Interrupt                                 */
+    EXTI0_IRQn = 22,           /* EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn = 23,           /* EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn = 24,           /* EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn = 25,           /* EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn = 26,           /* EXTI Line4 Interrupt                                 */
+    DMA1_Channel1_IRQn = 27,   /* DMA1 Channel 1 global Interrupt                      */
+    DMA1_Channel2_IRQn = 28,   /* DMA1 Channel 2 global Interrupt                      */
+    DMA1_Channel3_IRQn = 29,   /* DMA1 Channel 3 global Interrupt                      */
+    DMA1_Channel4_IRQn = 30,   /* DMA1 Channel 4 global Interrupt                      */
+    DMA1_Channel5_IRQn = 31,   /* DMA1 Channel 5 global Interrupt                      */
+    DMA1_Channel6_IRQn = 32,   /* DMA1 Channel 6 global Interrupt                      */
+    DMA1_Channel7_IRQn = 33,   /* DMA1 Channel 7 global Interrupt                      */
+    ADC_IRQn = 34,             /* ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn = 35,  /* USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn = 37,        /* CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn = 38,        /* CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn = 39,         /* External Line[9:5] Interrupts                        */
+    TIM1_BRK_IRQn = 40,        /* TIM1 Break Interrupt                                 */
+    TIM1_UP_IRQn = 41,         /* TIM1 Update Interrupt                                */
+    TIM1_TRG_COM_IRQn = 42,    /* TIM1 Trigger and Commutation Interrupt               */
+    TIM1_CC_IRQn = 43,         /* TIM1 Capture Compare Interrupt                       */
+    TIM2_IRQn = 44,            /* TIM2 global Interrupt                                */
+    TIM3_IRQn = 45,            /* TIM3 global Interrupt                                */
+    TIM4_IRQn = 46,            /* TIM4 global Interrupt                                */
+    I2C1_EV_IRQn = 47,         /* I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn = 48,         /* I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn = 49,         /* I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn = 50,         /* I2C2 Error Interrupt                                 */
+    SPI1_IRQn = 51,            /* SPI1 global Interrupt                                */
+    SPI2_IRQn = 52,            /* SPI2 global Interrupt                                */
+    USART1_IRQn = 53,          /* USART1 global Interrupt                              */
+    USART2_IRQn = 54,          /* USART2 global Interrupt                              */
+    USART3_IRQn = 55,          /* USART3 global Interrupt                              */
+    EXTI15_10_IRQn = 56,       /* External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn = 57,        /* RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn = 58,       /* USB Device WakeUp from suspend through EXTI Line Interrupt 	*/
+    USBHD_IRQn = 59,           /* USBHD global Interrupt                               */
+    USBHDWakeUp_IRQn = 60,     /* USB Host/Device WakeUp Interrupt                     */
+
+#ifdef CH32V20x_D6
+    UART4_IRQn = 61,         /* UART4 global Interrupt                               */
+    DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt                      */
+
+#elif defined(CH32V20x_D8)
+    ETH_IRQn = 61,           /* ETH global Interrupt               	                 */
+    ETHWakeUp_IRQn = 62,     /* ETH WakeUp Interrupt                       			 */
+    TIM5_IRQn = 65,          /* TIM5 global Interrupt                                */
+    UART4_IRQn = 66,         /* UART4 global Interrupt                               */
+    DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt                      */
+    OSC32KCal_IRQn = 68,     /* OSC32K global Interrupt                              */
+    OSCWakeUp_IRQn = 69,     /* OSC32K WakeUp Interrupt                              */
+
+#elif defined(CH32V20x_D8W)
+    ETH_IRQn = 61,           /* ETH global Interrupt               	                 */
+    ETHWakeUp_IRQn = 62,     /* ETH WakeUp Interrupt                       			 */
+    BB_IRQn = 63,            /* BLE BB global Interrupt                              */
+    LLE_IRQn = 64,           /* BLE LLE global Interrupt                             */
+    TIM5_IRQn = 65,          /* TIM5 global Interrupt                                */
+    UART4_IRQn = 66,         /* UART4 global Interrupt                               */
+    DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt                      */
+    OSC32KCal_IRQn = 68,     /* OSC32K global Interrupt                              */
+    OSCWakeUp_IRQn = 69,     /* OSC32K WakeUp Interrupt                              */
+#endif
+
+} IRQn_Type;
+
+#define HardFault_IRQn    EXC_IRQn
+#define ADC1_2_IRQn       ADC_IRQn
+
+#include <stdint.h>
+#include "core_riscv.h"
+#include "system_ch32v20x.h"
+
+/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSI_Value             HSI_VALUE
+#define HSE_Value             HSE_VALUE
+#define HSEStartUp_TimeOut    HSE_STARTUP_TIMEOUT
+
+/* Analog to Digital Converter */
+typedef struct
+{
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR1;
+    __IO uint32_t CTLR2;
+    __IO uint32_t SAMPTR1;
+    __IO uint32_t SAMPTR2;
+    __IO uint32_t IOFR1;
+    __IO uint32_t IOFR2;
+    __IO uint32_t IOFR3;
+    __IO uint32_t IOFR4;
+    __IO uint32_t WDHTR;
+    __IO uint32_t WDLTR;
+    __IO uint32_t RSQR1;
+    __IO uint32_t RSQR2;
+    __IO uint32_t RSQR3;
+    __IO uint32_t ISQR;
+    __IO uint32_t IDATAR1;
+    __IO uint32_t IDATAR2;
+    __IO uint32_t IDATAR3;
+    __IO uint32_t IDATAR4;
+    __IO uint32_t RDATAR;
+} ADC_TypeDef;
+
+/* Backup Registers */
+typedef struct
+{
+    uint32_t      RESERVED0;
+    __IO uint16_t DATAR1;
+    uint16_t      RESERVED1;
+    __IO uint16_t DATAR2;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR3;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR4;
+    uint16_t      RESERVED4;
+    __IO uint16_t DATAR5;
+    uint16_t      RESERVED5;
+    __IO uint16_t DATAR6;
+    uint16_t      RESERVED6;
+    __IO uint16_t DATAR7;
+    uint16_t      RESERVED7;
+    __IO uint16_t DATAR8;
+    uint16_t      RESERVED8;
+    __IO uint16_t DATAR9;
+    uint16_t      RESERVED9;
+    __IO uint16_t DATAR10;
+    uint16_t      RESERVED10;
+    __IO uint16_t OCTLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t TPCTLR;
+    uint16_t      RESERVED12;
+    __IO uint16_t TPCSR;
+    uint16_t      RESERVED13[5];
+    __IO uint16_t DATAR11;
+    uint16_t      RESERVED14;
+    __IO uint16_t DATAR12;
+    uint16_t      RESERVED15;
+    __IO uint16_t DATAR13;
+    uint16_t      RESERVED16;
+    __IO uint16_t DATAR14;
+    uint16_t      RESERVED17;
+    __IO uint16_t DATAR15;
+    uint16_t      RESERVED18;
+    __IO uint16_t DATAR16;
+    uint16_t      RESERVED19;
+    __IO uint16_t DATAR17;
+    uint16_t      RESERVED20;
+    __IO uint16_t DATAR18;
+    uint16_t      RESERVED21;
+    __IO uint16_t DATAR19;
+    uint16_t      RESERVED22;
+    __IO uint16_t DATAR20;
+    uint16_t      RESERVED23;
+    __IO uint16_t DATAR21;
+    uint16_t      RESERVED24;
+    __IO uint16_t DATAR22;
+    uint16_t      RESERVED25;
+    __IO uint16_t DATAR23;
+    uint16_t      RESERVED26;
+    __IO uint16_t DATAR24;
+    uint16_t      RESERVED27;
+    __IO uint16_t DATAR25;
+    uint16_t      RESERVED28;
+    __IO uint16_t DATAR26;
+    uint16_t      RESERVED29;
+    __IO uint16_t DATAR27;
+    uint16_t      RESERVED30;
+    __IO uint16_t DATAR28;
+    uint16_t      RESERVED31;
+    __IO uint16_t DATAR29;
+    uint16_t      RESERVED32;
+    __IO uint16_t DATAR30;
+    uint16_t      RESERVED33;
+    __IO uint16_t DATAR31;
+    uint16_t      RESERVED34;
+    __IO uint16_t DATAR32;
+    uint16_t      RESERVED35;
+    __IO uint16_t DATAR33;
+    uint16_t      RESERVED36;
+    __IO uint16_t DATAR34;
+    uint16_t      RESERVED37;
+    __IO uint16_t DATAR35;
+    uint16_t      RESERVED38;
+    __IO uint16_t DATAR36;
+    uint16_t      RESERVED39;
+    __IO uint16_t DATAR37;
+    uint16_t      RESERVED40;
+    __IO uint16_t DATAR38;
+    uint16_t      RESERVED41;
+    __IO uint16_t DATAR39;
+    uint16_t      RESERVED42;
+    __IO uint16_t DATAR40;
+    uint16_t      RESERVED43;
+    __IO uint16_t DATAR41;
+    uint16_t      RESERVED44;
+    __IO uint16_t DATAR42;
+    uint16_t      RESERVED45;
+} BKP_TypeDef;
+
+/* Controller Area Network TxMailBox */
+typedef struct
+{
+    __IO uint32_t TXMIR;
+    __IO uint32_t TXMDTR;
+    __IO uint32_t TXMDLR;
+    __IO uint32_t TXMDHR;
+} CAN_TxMailBox_TypeDef;
+
+/* Controller Area Network FIFOMailBox */
+typedef struct
+{
+    __IO uint32_t RXMIR;
+    __IO uint32_t RXMDTR;
+    __IO uint32_t RXMDLR;
+    __IO uint32_t RXMDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/* Controller Area Network FilterRegister */
+typedef struct
+{
+    __IO uint32_t FR1;
+    __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/* Controller Area Network */
+typedef struct
+{
+    __IO uint32_t              CTLR;
+    __IO uint32_t              STATR;
+    __IO uint32_t              TSTATR;
+    __IO uint32_t              RFIFO0;
+    __IO uint32_t              RFIFO1;
+    __IO uint32_t              INTENR;
+    __IO uint32_t              ERRSR;
+    __IO uint32_t              BTIMR;
+    uint32_t                   RESERVED0[88];
+    CAN_TxMailBox_TypeDef      sTxMailBox[3];
+    CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];
+    uint32_t                   RESERVED1[12];
+    __IO uint32_t              FCTLR;
+    __IO uint32_t              FMCFGR;
+    uint32_t                   RESERVED2;
+    __IO uint32_t              FSCFGR;
+    uint32_t                   RESERVED3;
+    __IO uint32_t              FAFIFOR;
+    uint32_t                   RESERVED4;
+    __IO uint32_t              FWR;
+    uint32_t                   RESERVED5[8];
+    CAN_FilterRegister_TypeDef sFilterRegister[28];
+} CAN_TypeDef;
+
+/* CRC Calculation Unit */
+typedef struct
+{
+    __IO uint32_t DATAR;
+    __IO uint8_t  IDATAR;
+    uint8_t       RESERVED0;
+    uint16_t      RESERVED1;
+    __IO uint32_t CTLR;
+} CRC_TypeDef;
+
+/* DMA Channel Controller */
+typedef struct
+{
+    __IO uint32_t CFGR;
+    __IO uint32_t CNTR;
+    __IO uint32_t PADDR;
+    __IO uint32_t MADDR;
+} DMA_Channel_TypeDef;
+
+/* DMA Controller */
+typedef struct
+{
+    __IO uint32_t INTFR;
+    __IO uint32_t INTFCR;
+} DMA_TypeDef;
+
+/* External Interrupt/Event Controller */
+typedef struct
+{
+    __IO uint32_t INTENR;
+    __IO uint32_t EVENR;
+    __IO uint32_t RTENR;
+    __IO uint32_t FTENR;
+    __IO uint32_t SWIEVR;
+    __IO uint32_t INTFR;
+} EXTI_TypeDef;
+
+/* FLASH Registers */
+typedef struct
+{
+    __IO uint32_t ACTLR;
+    __IO uint32_t KEYR;
+    __IO uint32_t OBKEYR;
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR;
+    __IO uint32_t ADDR;
+    __IO uint32_t RESERVED;
+    __IO uint32_t OBR;
+    __IO uint32_t WPR;
+    __IO uint32_t MODEKEYR;
+} FLASH_TypeDef;
+
+/* Option Bytes Registers */
+typedef struct
+{
+    __IO uint16_t RDPR;
+    __IO uint16_t USER;
+    __IO uint16_t Data0;
+    __IO uint16_t Data1;
+    __IO uint16_t WRPR0;
+    __IO uint16_t WRPR1;
+    __IO uint16_t WRPR2;
+    __IO uint16_t WRPR3;
+} OB_TypeDef;
+
+/* General Purpose I/O */
+typedef struct
+{
+    __IO uint32_t CFGLR;
+    __IO uint32_t CFGHR;
+    __IO uint32_t INDR;
+    __IO uint32_t OUTDR;
+    __IO uint32_t BSHR;
+    __IO uint32_t BCR;
+    __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/* Alternate Function I/O */
+typedef struct
+{
+    __IO uint32_t ECR;
+    __IO uint32_t PCFR1;
+    __IO uint32_t EXTICR[4];
+    uint32_t      RESERVED0;
+    __IO uint32_t PCFR2;
+} AFIO_TypeDef;
+
+/* Inter Integrated Circuit Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t OADDR1;
+    uint16_t      RESERVED2;
+    __IO uint16_t OADDR2;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED4;
+    __IO uint16_t STAR1;
+    uint16_t      RESERVED5;
+    __IO uint16_t STAR2;
+    uint16_t      RESERVED6;
+    __IO uint16_t CKCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t RTR;
+    uint16_t      RESERVED8;
+} I2C_TypeDef;
+
+/* Independent WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t PSCR;
+    __IO uint32_t RLDR;
+    __IO uint32_t STATR;
+} IWDG_TypeDef;
+
+/* Power Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/* Reset and Clock Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR0;
+    __IO uint32_t INTR;
+    __IO uint32_t APB2PRSTR;
+    __IO uint32_t APB1PRSTR;
+    __IO uint32_t AHBPCENR;
+    __IO uint32_t APB2PCENR;
+    __IO uint32_t APB1PCENR;
+    __IO uint32_t BDCTLR;
+    __IO uint32_t RSTSCKR;
+
+    __IO uint32_t AHBRSTR;
+    __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/* Real-Time Clock */
+typedef struct
+{
+    __IO uint16_t CTLRH;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLRL;
+    uint16_t      RESERVED1;
+    __IO uint16_t PSCRH;
+    uint16_t      RESERVED2;
+    __IO uint16_t PSCRL;
+    uint16_t      RESERVED3;
+    __IO uint16_t DIVH;
+    uint16_t      RESERVED4;
+    __IO uint16_t DIVL;
+    uint16_t      RESERVED5;
+    __IO uint16_t CNTH;
+    uint16_t      RESERVED6;
+    __IO uint16_t CNTL;
+    uint16_t      RESERVED7;
+    __IO uint16_t ALRMH;
+    uint16_t      RESERVED8;
+    __IO uint16_t ALRML;
+    uint16_t      RESERVED9;
+} RTC_TypeDef;
+
+/* Serial Peripheral Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t STATR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED3;
+    __IO uint16_t CRCR;
+    uint16_t      RESERVED4;
+    __IO uint16_t RCRCR;
+    uint16_t      RESERVED5;
+    __IO uint16_t TCRCR;
+    uint16_t      RESERVED6;
+    __IO uint16_t I2SCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t I2SPR;
+    uint16_t      RESERVED8;
+    __IO uint16_t HSCR;
+    uint16_t      RESERVED9;
+} SPI_TypeDef;
+
+/* TIM */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t SMCFGR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DMAINTENR;
+    uint16_t      RESERVED3;
+    __IO uint16_t INTFR;
+    uint16_t      RESERVED4;
+    __IO uint16_t SWEVGR;
+    uint16_t      RESERVED5;
+    __IO uint16_t CHCTLR1;
+    uint16_t      RESERVED6;
+    __IO uint16_t CHCTLR2;
+    uint16_t      RESERVED7;
+    __IO uint16_t CCER;
+    uint16_t      RESERVED8;
+    __IO uint16_t CNT;
+    uint16_t      RESERVED9;
+    __IO uint16_t PSC;
+    uint16_t      RESERVED10;
+    __IO uint16_t ATRLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t RPTCR;
+    uint16_t      RESERVED12;
+    __IO uint16_t CH1CVR;
+    uint16_t      RESERVED13;
+    __IO uint16_t CH2CVR;
+    uint16_t      RESERVED14;
+    __IO uint16_t CH3CVR;
+    uint16_t      RESERVED15;
+    __IO uint16_t CH4CVR;
+    uint16_t      RESERVED16;
+    __IO uint16_t BDTR;
+    uint16_t      RESERVED17;
+    __IO uint16_t DMACFGR;
+    uint16_t      RESERVED18;
+    __IO uint16_t DMAADR;
+    uint16_t      RESERVED19;
+} TIM_TypeDef;
+
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+typedef struct
+{
+    __IO uint16_t STATR;
+    uint16_t      RESERVED0;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED1;
+    __IO uint16_t BRR;
+    uint16_t      RESERVED2;
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED3;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED4;
+    __IO uint16_t CTLR3;
+    uint16_t      RESERVED5;
+    __IO uint16_t GPR;
+    uint16_t      RESERVED6;
+} USART_TypeDef;
+
+/* Window WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR;
+    __IO uint32_t STATR;
+} WWDG_TypeDef;
+
+/* Enhanced Registers */
+typedef struct
+{
+    __IO uint32_t EXTEN_CTR;
+} EXTEN_TypeDef;
+
+/* OPA Registers */
+typedef struct
+{
+    __IO uint32_t CR;
+} OPA_TypeDef;
+
+/* USBFS Registers */
+typedef struct
+{
+    __IO uint8_t  BASE_CTRL;
+    __IO uint8_t  UDEV_CTRL;
+    __IO uint8_t  INT_EN;
+    __IO uint8_t  DEV_ADDR;
+    __IO uint8_t  Reserve0;
+    __IO uint8_t  MIS_ST;
+    __IO uint8_t  INT_FG;
+    __IO uint8_t  INT_ST;
+    __IO uint32_t RX_LEN;
+    __IO uint8_t  UEP4_1_MOD;
+    __IO uint8_t  UEP2_3_MOD;
+    __IO uint8_t  UEP5_6_MOD;
+    __IO uint8_t  UEP7_MOD;
+    __IO uint32_t UEP0_DMA;
+    __IO uint32_t UEP1_DMA;
+    __IO uint32_t UEP2_DMA;
+    __IO uint32_t UEP3_DMA;
+    __IO uint32_t UEP4_DMA;
+    __IO uint32_t UEP5_DMA;
+    __IO uint32_t UEP6_DMA;
+    __IO uint32_t UEP7_DMA;
+    __IO uint16_t UEP0_TX_LEN;
+    __IO uint8_t  UEP0_TX_CTRL;
+    __IO uint8_t  UEP0_RX_CTRL;
+    __IO uint16_t UEP1_TX_LEN;
+    __IO uint8_t  UEP1_TX_CTRL;
+    __IO uint8_t  UEP1_RX_CTRL;
+    __IO uint16_t UEP2_TX_LEN;
+    __IO uint8_t  UEP2_TX_CTRL;
+    __IO uint8_t  UEP2_RX_CTRL;
+    __IO uint16_t UEP3_TX_LEN;
+    __IO uint8_t  UEP3_TX_CTRL;
+    __IO uint8_t  UEP3_RX_CTRL;
+    __IO uint16_t UEP4_TX_LEN;
+    __IO uint8_t  UEP4_TX_CTRL;
+    __IO uint8_t  UEP4_RX_CTRL;
+    __IO uint16_t UEP5_TX_LEN;
+    __IO uint8_t  UEP5_TX_CTRL;
+    __IO uint8_t  UEP5_RX_CTRL;
+    __IO uint16_t UEP6_TX_LEN;
+    __IO uint8_t  UEP6_TX_CTRL;
+    __IO uint8_t  UEP6_RX_CTRL;
+    __IO uint16_t UEP7_TX_LEN;
+    __IO uint8_t  UEP7_TX_CTRL;
+    __IO uint8_t  UEP7_RX_CTRL;
+    __IO uint32_t Reserve1;
+    __IO uint32_t OTG_CR;
+    __IO uint32_t OTG_SR;
+} USBOTG_FS_TypeDef;
+
+typedef struct
+{
+    __IO uint8_t   BASE_CTRL;
+    __IO uint8_t   HOST_CTRL;
+    __IO uint8_t   INT_EN;
+    __IO uint8_t   DEV_ADDR;
+    __IO uint8_t   Reserve0;
+    __IO uint8_t   MIS_ST;
+    __IO uint8_t   INT_FG;
+    __IO uint8_t   INT_ST;
+    __IO uint16_t  RX_LEN;
+    __IO uint16_t  Reserve1;
+    __IO uint8_t   Reserve2;
+    __IO uint8_t   HOST_EP_MOD;
+    __IO uint16_t  Reserve3;
+    __IO uint32_t  Reserve4;
+    __IO uint32_t  Reserve5;
+    __IO uint32_t  HOST_RX_DMA;
+    __IO uint32_t  HOST_TX_DMA;
+    __IO uint32_t  Reserve6;
+    __IO uint32_t  Reserve7;
+    __IO uint32_t  Reserve8;
+    __IO uint32_t  Reserve9;
+    __IO uint32_t  Reserve10;
+    __IO uint16_t  Reserve11;
+    __IO uint16_t  HOST_SETUP;
+    __IO uint8_t   HOST_EP_PID;
+    __IO uint8_t   Reserve12;
+    __IO uint8_t   Reserve13;
+    __IO uint8_t   HOST_RX_CTRL;
+    __IO uint16_t  HOST_TX_LEN;
+    __IO uint8_t   HOST_TX_CTRL;
+    __IO uint8_t   Reserve14;
+    __IO uint32_t  Reserve15;
+    __IO uint32_t  Reserve16;
+    __IO uint32_t  Reserve17;
+    __IO uint32_t  Reserve18;
+    __IO uint32_t  Reserve19;
+    __IO uint32_t  OTG_CR;
+    __IO uint32_t  OTG_SR;
+} USBOTG_FS_HOST_TypeDef;
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+/* ETH10M Registers */
+typedef struct
+{
+    __IO uint8_t reserved1;
+    __IO uint8_t reserved2;
+    __IO uint8_t reserved3;
+    __IO uint8_t EIE;
+
+    __IO uint8_t EIR;
+    __IO uint8_t ESTAT;
+    __IO uint8_t ECON2;
+    __IO uint8_t ECON1;
+
+    __IO uint16_t ETXST;
+    __IO uint16_t ETXLN;
+
+    __IO uint16_t ERXST;
+    __IO uint16_t ERXLN;
+
+    __IO uint32_t HTL;
+    __IO uint32_t HTH;
+
+    __IO uint8_t ERXFON;
+    __IO uint8_t MACON1;
+    __IO uint8_t MACON2;
+    __IO uint8_t MABBIPG;
+
+    __IO uint16_t EPAUS;
+    __IO uint16_t MAMXFL;
+
+    __IO uint16_t MIRD;
+    __IO uint16_t reserved4;
+
+    __IO uint8_t MIERGADR;
+    __IO uint8_t MISTAT;
+    __IO uint16_t MIWR;
+
+    __IO uint32_t MAADRL;
+
+    __IO uint16_t MAADRH;
+    __IO uint16_t reserved5;
+} ETH10M_TypeDef;
+#endif
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+/* OSC Registers */
+typedef struct
+{
+    __IO uint32_t HSE_CAL_CTRL;
+    __IO uint32_t Reserve0;
+    __IO uint16_t Reserve1;
+    __IO uint16_t LSI32K_TUNE;
+    __IO uint32_t Reserve2;
+    __IO uint32_t Reserve3;
+    __IO uint32_t Reserve4;
+    __IO uint32_t Reserve5;
+    __IO uint8_t  Reserve6;
+    __IO uint8_t  LSI32K_CAL_CFG;
+    __IO uint16_t Reserve7;
+    __IO uint16_t LSI32K_CAL_STATR;
+    __IO uint8_t  LSI32K_CAL_OV_CNT;
+    __IO uint8_t  LSI32K_CAL_CTRL;
+} OSC_TypeDef;
+
+#endif
+
+/* Peripheral memory map */
+#define FLASH_BASE                              ((uint32_t)0x08000000) /* FLASH base address in the alias region */
+#define SRAM_BASE                               ((uint32_t)0x20000000) /* SRAM base address in the alias region */
+#define PERIPH_BASE                             ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
+
+#define APB1PERIPH_BASE                         (PERIPH_BASE)
+#define APB2PERIPH_BASE                         (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE                          (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE                               (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE                               (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE                               (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE                               (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE                                (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE                               (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE                               (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE                               (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE                             (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE                             (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE                              (APB1PERIPH_BASE + 0x4C00)
+#define I2C1_BASE                               (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE                               (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE                               (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE                                (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE                                (APB1PERIPH_BASE + 0x7000)
+
+#define AFIO_BASE                               (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE                               (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE                              (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE                              (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE                              (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE                              (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE                              (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE                              (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE                              (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE                               (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE                               (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE                               (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE                               (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE                             (APB2PERIPH_BASE + 0x3800)
+
+#define DMA1_BASE                               (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE                      (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE                      (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE                      (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE                      (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE                      (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE                      (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE                      (AHBPERIPH_BASE + 0x0080)
+#define DMA1_Channel8_BASE                      (AHBPERIPH_BASE + 0x0094)
+#define RCC_BASE                                (AHBPERIPH_BASE + 0x1000)
+#define FLASH_R_BASE                            (AHBPERIPH_BASE + 0x2000)
+#define CRC_BASE                                (AHBPERIPH_BASE + 0x3000)
+#define EXTEN_BASE                              (AHBPERIPH_BASE + 0x3800)
+#define OPA_BASE                                (AHBPERIPH_BASE + 0x3804)
+#define ETH10M_BASE                             (AHBPERIPH_BASE + 0x8000)
+
+#define USBFS_BASE                              ((uint32_t)0x50000000)
+
+#define OB_BASE                                 ((uint32_t)0x1FFFF800)
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+#define OSC_BASE                                (AHBPERIPH_BASE + 0x202C)
+#endif
+
+/* Peripheral declaration */
+#define TIM2                                    ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3                                    ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4                                    ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5                                    ((TIM_TypeDef *)TIM5_BASE)
+#define RTC                                     ((RTC_TypeDef *)RTC_BASE)
+#define WWDG                                    ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG                                    ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2                                    ((SPI_TypeDef *)SPI2_BASE)
+#define USART2                                  ((USART_TypeDef *)USART2_BASE)
+#define USART3                                  ((USART_TypeDef *)USART3_BASE)
+#define UART4                                   ((USART_TypeDef *)UART4_BASE)
+#define I2C1                                    ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2                                    ((I2C_TypeDef *)I2C2_BASE)
+#define CAN1                                    ((CAN_TypeDef *)CAN1_BASE)
+#define BKP                                     ((BKP_TypeDef *)BKP_BASE)
+#define PWR                                     ((PWR_TypeDef *)PWR_BASE)
+
+#define AFIO                                    ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI                                    ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA                                   ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB                                   ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC                                   ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD                                   ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE                                   ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF                                   ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG                                   ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1                                    ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2                                    ((ADC_TypeDef *)ADC2_BASE)
+#define TKey1                                   ((ADC_TypeDef *)ADC1_BASE)
+#define TKey2                                   ((ADC_TypeDef *)ADC2_BASE)
+#define TIM1                                    ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1                                    ((SPI_TypeDef *)SPI1_BASE)
+#define USART1                                  ((USART_TypeDef *)USART1_BASE)
+
+#define DMA1                                    ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1                           ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2                           ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3                           ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4                           ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5                           ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6                           ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7                           ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA1_Channel8                           ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE)
+#define RCC                                     ((RCC_TypeDef *)RCC_BASE)
+#define FLASH                                   ((FLASH_TypeDef *)FLASH_R_BASE)
+#define CRC                                     ((CRC_TypeDef *)CRC_BASE)
+#define USBOTG_FS                               ((USBOTG_FS_TypeDef *)USBFS_BASE)
+#define USBOTG_H_FS                             ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE)
+#define EXTEN                                   ((EXTEN_TypeDef *)EXTEN_BASE)
+#define OPA                                     ((OPA_TypeDef *)OPA_BASE)
+#define ETH10M                                  ((ETH10M_TypeDef *)ETH10M_BASE)
+
+#define OB                                      ((OB_TypeDef *)OB_BASE)
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+#define OSC                                     ((OSC_TypeDef *)OSC_BASE)
+#endif
+
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                        Analog to Digital Converter                         */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STATR register  ********************/
+#define ADC_AWD                                 ((uint8_t)0x01) /* Analog watchdog flag */
+#define ADC_EOC                                 ((uint8_t)0x02) /* End of conversion */
+#define ADC_JEOC                                ((uint8_t)0x04) /* Injected channel end of conversion */
+#define ADC_JSTRT                               ((uint8_t)0x08) /* Injected channel Start flag */
+#define ADC_STRT                                ((uint8_t)0x10) /* Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTLR1 register  ********************/
+#define ADC_AWDCH                               ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_AWDCH_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_AWDCH_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_AWDCH_2                             ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_AWDCH_3                             ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_AWDCH_4                             ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_EOCIE                               ((uint32_t)0x00000020) /* Interrupt enable for EOC */
+#define ADC_AWDIE                               ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */
+#define ADC_JEOCIE                              ((uint32_t)0x00000080) /* Interrupt enable for injected channels */
+#define ADC_SCAN                                ((uint32_t)0x00000100) /* Scan mode */
+#define ADC_AWDSGL                              ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */
+#define ADC_JAUTO                               ((uint32_t)0x00000400) /* Automatic injected group conversion */
+#define ADC_DISCEN                              ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */
+#define ADC_JDISCEN                             ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */
+
+#define ADC_DISCNUM                             ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_DISCNUM_0                           ((uint32_t)0x00002000) /* Bit 0 */
+#define ADC_DISCNUM_1                           ((uint32_t)0x00004000) /* Bit 1 */
+#define ADC_DISCNUM_2                           ((uint32_t)0x00008000) /* Bit 2 */
+
+#define ADC_DUALMOD                             ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_DUALMOD_0                           ((uint32_t)0x00010000) /* Bit 0 */
+#define ADC_DUALMOD_1                           ((uint32_t)0x00020000) /* Bit 1 */
+#define ADC_DUALMOD_2                           ((uint32_t)0x00040000) /* Bit 2 */
+#define ADC_DUALMOD_3                           ((uint32_t)0x00080000) /* Bit 3 */
+
+#define ADC_JAWDEN                              ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
+#define ADC_AWDEN                               ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTLR2 register  ********************/
+#define ADC_ADON                                ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
+#define ADC_CONT                                ((uint32_t)0x00000002) /* Continuous Conversion */
+#define ADC_CAL                                 ((uint32_t)0x00000004) /* A/D Calibration */
+#define ADC_RSTCAL                              ((uint32_t)0x00000008) /* Reset Calibration */
+#define ADC_DMA                                 ((uint32_t)0x00000100) /* Direct Memory access mode */
+#define ADC_ALIGN                               ((uint32_t)0x00000800) /* Data Alignment */
+
+#define ADC_JEXTSEL                             ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_JEXTSEL_0                           ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_JEXTSEL_1                           ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_JEXTSEL_2                           ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_JEXTTRIG                            ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */
+
+#define ADC_EXTSEL                              ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_EXTSEL_0                            ((uint32_t)0x00020000) /* Bit 0 */
+#define ADC_EXTSEL_1                            ((uint32_t)0x00040000) /* Bit 1 */
+#define ADC_EXTSEL_2                            ((uint32_t)0x00080000) /* Bit 2 */
+
+#define ADC_EXTTRIG                             ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
+#define ADC_JSWSTART                            ((uint32_t)0x00200000) /* Start Conversion of injected channels */
+#define ADC_SWSTART                             ((uint32_t)0x00400000) /* Start Conversion of regular channels */
+#define ADC_TSVREFE                             ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPTR1 register  *******************/
+#define ADC_SMP10                               ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMP10_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP10_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP10_2                             ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP11                               ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMP11_0                             ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP11_1                             ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP11_2                             ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP12                               ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMP12_0                             ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP12_1                             ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP12_2                             ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP13                               ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMP13_0                             ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP13_1                             ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP13_2                             ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP14                               ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMP14_0                             ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP14_1                             ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP14_2                             ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP15                               ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMP15_0                             ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP15_1                             ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP15_2                             ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP16                               ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMP16_0                             ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP16_1                             ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP16_2                             ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP17                               ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMP17_0                             ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP17_1                             ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP17_2                             ((uint32_t)0x00800000) /* Bit 2 */
+
+/******************  Bit definition for ADC_SAMPTR2 register  *******************/
+#define ADC_SMP0                                ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMP0_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP0_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP0_2                              ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP1                                ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMP1_0                              ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP1_1                              ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP1_2                              ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP2                                ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMP2_0                              ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP2_1                              ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP2_2                              ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP3                                ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMP3_0                              ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP3_1                              ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP3_2                              ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP4                                ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMP4_0                              ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP4_1                              ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP4_2                              ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP5                                ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMP5_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP5_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP5_2                              ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP6                                ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMP6_0                              ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP6_1                              ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP6_2                              ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP7                                ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMP7_0                              ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP7_1                              ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP7_2                              ((uint32_t)0x00800000) /* Bit 2 */
+
+#define ADC_SMP8                                ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMP8_0                              ((uint32_t)0x01000000) /* Bit 0 */
+#define ADC_SMP8_1                              ((uint32_t)0x02000000) /* Bit 1 */
+#define ADC_SMP8_2                              ((uint32_t)0x04000000) /* Bit 2 */
+
+#define ADC_SMP9                                ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMP9_0                              ((uint32_t)0x08000000) /* Bit 0 */
+#define ADC_SMP9_1                              ((uint32_t)0x10000000) /* Bit 1 */
+#define ADC_SMP9_2                              ((uint32_t)0x20000000) /* Bit 2 */
+
+/******************  Bit definition for ADC_IOFR1 register  *******************/
+#define ADC_JOFFSET1                            ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_IOFR2 register  *******************/
+#define ADC_JOFFSET2                            ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_IOFR3 register  *******************/
+#define ADC_JOFFSET3                            ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_IOFR4 register  *******************/
+#define ADC_JOFFSET4                            ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDHTR register  ********************/
+#define ADC_HT                                  ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDLTR register  ********************/
+#define ADC_LT                                  ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQR1 register  *******************/
+#define ADC_SQ13                                ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQ13_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ13_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ13_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ13_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ13_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ14                                ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQ14_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ14_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ14_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ14_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ14_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ15                                ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQ15_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ15_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ15_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ15_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ15_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ16                                ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQ16_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ16_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ16_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ16_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ16_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_L                                   ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
+#define ADC_L_0                                 ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_L_1                                 ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_L_2                                 ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_L_3                                 ((uint32_t)0x00800000) /* Bit 3 */
+
+/*******************  Bit definition for ADC_RSQR2 register  *******************/
+#define ADC_SQ7                                 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQ7_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ7_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ7_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ7_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ7_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ8                                 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQ8_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ8_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ8_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ8_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ8_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ9                                 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQ9_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ9_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ9_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ9_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ9_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ10                                ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQ10_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ10_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ10_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ10_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ10_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ11                                ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQ11_0                              ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ11_1                              ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ11_2                              ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ11_3                              ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ11_4                              ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ12                                ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQ12_0                              ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ12_1                              ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ12_2                              ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ12_3                              ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ12_4                              ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_RSQR3 register  *******************/
+#define ADC_SQ1                                 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQ1_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ1_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ1_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ1_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ1_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ2                                 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQ2_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ2_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ2_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ2_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ2_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ3                                 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQ3_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ3_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ3_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ3_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ3_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ4                                 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQ4_0                               ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ4_1                               ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ4_2                               ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ4_3                               ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ4_4                               ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ5                                 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQ5_0                               ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ5_1                               ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ5_2                               ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ5_3                               ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ5_4                               ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ6                                 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQ6_0                               ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ6_1                               ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ6_2                               ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ6_3                               ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ6_4                               ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_ISQR register  *******************/
+#define ADC_JSQ1                                ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQ1_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_JSQ1_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_JSQ1_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_JSQ1_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_JSQ1_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_JSQ2                                ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQ2_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_JSQ2_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_JSQ2_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_JSQ2_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_JSQ2_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_JSQ3                                ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQ3_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_JSQ3_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_JSQ3_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_JSQ3_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_JSQ3_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_JSQ4                                ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQ4_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_JSQ4_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_JSQ4_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_JSQ4_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_JSQ4_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_JL                                  ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
+#define ADC_JL_0                                ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_JL_1                                ((uint32_t)0x00200000) /* Bit 1 */
+
+/*******************  Bit definition for ADC_IDATAR1 register  *******************/
+#define ADC_IDATAR1_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR2 register  *******************/
+#define ADC_IDATAR2_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR3 register  *******************/
+#define ADC_IDATAR3_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR4 register  *******************/
+#define ADC_IDATAR4_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/********************  Bit definition for ADC_RDATAR register  ********************/
+#define ADC_RDATAR_DATA                         ((uint32_t)0x0000FFFF) /* Regular data */
+#define ADC_RDATAR_ADC2DATA                     ((uint32_t)0xFFFF0000) /* ADC2 data */
+
+/******************************************************************************/
+/*                            Backup registers                                */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DATAR1 register  ********************/
+#define BKP_DATAR1_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR2 register  ********************/
+#define BKP_DATAR2_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR3 register  ********************/
+#define BKP_DATAR3_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR4 register  ********************/
+#define BKP_DATAR4_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR5 register  ********************/
+#define BKP_DATAR5_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR6 register  ********************/
+#define BKP_DATAR6_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR7 register  ********************/
+#define BKP_DATAR7_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR8 register  ********************/
+#define BKP_DATAR8_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR9 register  ********************/
+#define BKP_DATAR9_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR10 register  *******************/
+#define BKP_DATAR10_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR11 register  *******************/
+#define BKP_DATAR11_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR12 register  *******************/
+#define BKP_DATAR12_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR13 register  *******************/
+#define BKP_DATAR13_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR14 register  *******************/
+#define BKP_DATAR14_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR15 register  *******************/
+#define BKP_DATAR15_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR16 register  *******************/
+#define BKP_DATAR16_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR17 register  *******************/
+#define BKP_DATAR17_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_DATAR18 register  ********************/
+#define BKP_DATAR18_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR19 register  *******************/
+#define BKP_DATAR19_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR20 register  *******************/
+#define BKP_DATAR20_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR21 register  *******************/
+#define BKP_DATAR21_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR22 register  *******************/
+#define BKP_DATAR22_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR23 register  *******************/
+#define BKP_DATAR23_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR24 register  *******************/
+#define BKP_DATAR24_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR25 register  *******************/
+#define BKP_DATAR25_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR26 register  *******************/
+#define BKP_DATAR26_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR27 register  *******************/
+#define BKP_DATAR27_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR28 register  *******************/
+#define BKP_DATAR28_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR29 register  *******************/
+#define BKP_DATAR29_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR30 register  *******************/
+#define BKP_DATAR30_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR31 register  *******************/
+#define BKP_DATAR31_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR32 register  *******************/
+#define BKP_DATAR32_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR33 register  *******************/
+#define BKP_DATAR33_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR34 register  *******************/
+#define BKP_DATAR34_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR35 register  *******************/
+#define BKP_DATAR35_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR36 register  *******************/
+#define BKP_DATAR36_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR37 register  *******************/
+#define BKP_DATAR37_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR38 register  *******************/
+#define BKP_DATAR38_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR39 register  *******************/
+#define BKP_DATAR39_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR40 register  *******************/
+#define BKP_DATAR40_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR41 register  *******************/
+#define BKP_DATAR41_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR42 register  *******************/
+#define BKP_DATAR42_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_OCTLR register  *******************/
+#define BKP_CAL                                 ((uint16_t)0x007F) /* Calibration value */
+#define BKP_CCO                                 ((uint16_t)0x0080) /* Calibration Clock Output */
+#define BKP_ASOE                                ((uint16_t)0x0100) /* Alarm or Second Output Enable */
+#define BKP_ASOS                                ((uint16_t)0x0200) /* Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_TPCTLR register  ********************/
+#define BKP_TPE                                 ((uint8_t)0x01) /* TAMPER pin enable */
+#define BKP_TPAL                                ((uint8_t)0x02) /* TAMPER pin active level */
+
+/*******************  Bit definition for BKP_TPCSR register  ********************/
+#define BKP_CTE                                 ((uint16_t)0x0001) /* Clear Tamper event */
+#define BKP_CTI                                 ((uint16_t)0x0002) /* Clear Tamper Interrupt */
+#define BKP_TPIE                                ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */
+#define BKP_TEF                                 ((uint16_t)0x0100) /* Tamper Event Flag */
+#define BKP_TIF                                 ((uint16_t)0x0200) /* Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                         Controller Area Network                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CAN_CTLR register  ********************/
+#define CAN_CTLR_INRQ                           ((uint16_t)0x0001) /* Initialization Request */
+#define CAN_CTLR_SLEEP                          ((uint16_t)0x0002) /* Sleep Mode Request */
+#define CAN_CTLR_TXFP                           ((uint16_t)0x0004) /* Transmit FIFO Priority */
+#define CAN_CTLR_RFLM                           ((uint16_t)0x0008) /* Receive FIFO Locked Mode */
+#define CAN_CTLR_NART                           ((uint16_t)0x0010) /* No Automatic Retransmission */
+#define CAN_CTLR_AWUM                           ((uint16_t)0x0020) /* Automatic Wakeup Mode */
+#define CAN_CTLR_ABOM                           ((uint16_t)0x0040) /* Automatic Bus-Off Management */
+#define CAN_CTLR_TTCM                           ((uint16_t)0x0080) /* Time Triggered Communication Mode */
+#define CAN_CTLR_RESET                          ((uint16_t)0x8000) /* CAN software master reset */
+
+/*******************  Bit definition for CAN_STATR register  ********************/
+#define CAN_STATR_INAK                          ((uint16_t)0x0001) /* Initialization Acknowledge */
+#define CAN_STATR_SLAK                          ((uint16_t)0x0002) /* Sleep Acknowledge */
+#define CAN_STATR_ERRI                          ((uint16_t)0x0004) /* Error Interrupt */
+#define CAN_STATR_WKUI                          ((uint16_t)0x0008) /* Wakeup Interrupt */
+#define CAN_STATR_SLAKI                         ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */
+#define CAN_STATR_TXM                           ((uint16_t)0x0100) /* Transmit Mode */
+#define CAN_STATR_RXM                           ((uint16_t)0x0200) /* Receive Mode */
+#define CAN_STATR_SAMP                          ((uint16_t)0x0400) /* Last Sample Point */
+#define CAN_STATR_RX                            ((uint16_t)0x0800) /* CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSTATR register  ********************/
+#define CAN_TSTATR_RQCP0                        ((uint32_t)0x00000001) /* Request Completed Mailbox0 */
+#define CAN_TSTATR_TXOK0                        ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */
+#define CAN_TSTATR_ALST0                        ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */
+#define CAN_TSTATR_TERR0                        ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */
+#define CAN_TSTATR_ABRQ0                        ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */
+#define CAN_TSTATR_RQCP1                        ((uint32_t)0x00000100) /* Request Completed Mailbox1 */
+#define CAN_TSTATR_TXOK1                        ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */
+#define CAN_TSTATR_ALST1                        ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */
+#define CAN_TSTATR_TERR1                        ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */
+#define CAN_TSTATR_ABRQ1                        ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */
+#define CAN_TSTATR_RQCP2                        ((uint32_t)0x00010000) /* Request Completed Mailbox2 */
+#define CAN_TSTATR_TXOK2                        ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */
+#define CAN_TSTATR_ALST2                        ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */
+#define CAN_TSTATR_TERR2                        ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */
+#define CAN_TSTATR_ABRQ2                        ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */
+#define CAN_TSTATR_CODE                         ((uint32_t)0x03000000) /* Mailbox Code */
+
+#define CAN_TSTATR_TME                          ((uint32_t)0x1C000000) /* TME[2:0] bits */
+#define CAN_TSTATR_TME0                         ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */
+#define CAN_TSTATR_TME1                         ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */
+#define CAN_TSTATR_TME2                         ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */
+
+#define CAN_TSTATR_LOW                          ((uint32_t)0xE0000000) /* LOW[2:0] bits */
+#define CAN_TSTATR_LOW0                         ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSTATR_LOW1                         ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSTATR_LOW2                         ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RFIFO0 register  *******************/
+#define CAN_RFIFO0_FMP0                         ((uint8_t)0x03) /* FIFO 0 Message Pending */
+#define CAN_RFIFO0_FULL0                        ((uint8_t)0x08) /* FIFO 0 Full */
+#define CAN_RFIFO0_FOVR0                        ((uint8_t)0x10) /* FIFO 0 Overrun */
+#define CAN_RFIFO0_RFOM0                        ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RFIFO1 register  *******************/
+#define CAN_RFIFO1_FMP1                         ((uint8_t)0x03) /* FIFO 1 Message Pending */
+#define CAN_RFIFO1_FULL1                        ((uint8_t)0x08) /* FIFO 1 Full */
+#define CAN_RFIFO1_FOVR1                        ((uint8_t)0x10) /* FIFO 1 Overrun */
+#define CAN_RFIFO1_RFOM1                        ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_INTENR register  *******************/
+#define CAN_INTENR_TMEIE                        ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */
+#define CAN_INTENR_FMPIE0                       ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */
+#define CAN_INTENR_FFIE0                        ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */
+#define CAN_INTENR_FOVIE0                       ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */
+#define CAN_INTENR_FMPIE1                       ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */
+#define CAN_INTENR_FFIE1                        ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */
+#define CAN_INTENR_FOVIE1                       ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */
+#define CAN_INTENR_EWGIE                        ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */
+#define CAN_INTENR_EPVIE                        ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */
+#define CAN_INTENR_BOFIE                        ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */
+#define CAN_INTENR_LECIE                        ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */
+#define CAN_INTENR_ERRIE                        ((uint32_t)0x00008000) /* Error Interrupt Enable */
+#define CAN_INTENR_WKUIE                        ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */
+#define CAN_INTENR_SLKIE                        ((uint32_t)0x00020000) /* Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ERRSR register  *******************/
+#define CAN_ERRSR_EWGF                          ((uint32_t)0x00000001) /* Error Warning Flag */
+#define CAN_ERRSR_EPVF                          ((uint32_t)0x00000002) /* Error Passive Flag */
+#define CAN_ERRSR_BOFF                          ((uint32_t)0x00000004) /* Bus-Off Flag */
+
+#define CAN_ERRSR_LEC                           ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */
+#define CAN_ERRSR_LEC_0                         ((uint32_t)0x00000010) /* Bit 0 */
+#define CAN_ERRSR_LEC_1                         ((uint32_t)0x00000020) /* Bit 1 */
+#define CAN_ERRSR_LEC_2                         ((uint32_t)0x00000040) /* Bit 2 */
+
+#define CAN_ERRSR_TEC                           ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ERRSR_REC                           ((uint32_t)0xFF000000) /* Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTIMR register  ********************/
+#define CAN_BTIMR_BRP                           ((uint32_t)0x000003FF) /* Baud Rate Prescaler */
+#define CAN_BTIMR_TS1                           ((uint32_t)0x000F0000) /* Time Segment 1 */
+#define CAN_BTIMR_TS2                           ((uint32_t)0x00700000) /* Time Segment 2 */
+#define CAN_BTIMR_SJW                           ((uint32_t)0x03000000) /* Resynchronization Jump Width */
+#define CAN_BTIMR_LBKM                          ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */
+#define CAN_BTIMR_SILM                          ((uint32_t)0x80000000) /* Silent Mode */
+
+/******************  Bit definition for CAN_TXMI0R register  ********************/
+#define CAN_TXMI0R_TXRQ                         ((uint32_t)0x00000001) /* Transmit Mailbox Request */
+#define CAN_TXMI0R_RTR                          ((uint32_t)0x00000002) /* Remote Transmission Request */
+#define CAN_TXMI0R_IDE                          ((uint32_t)0x00000004) /* Identifier Extension */
+#define CAN_TXMI0R_EXID                         ((uint32_t)0x001FFFF8) /* Extended Identifier */
+#define CAN_TXMI0R_STID                         ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TXMDT0R register  *******************/
+#define CAN_TXMDT0R_DLC                         ((uint32_t)0x0000000F) /* Data Length Code */
+#define CAN_TXMDT0R_TGT                         ((uint32_t)0x00000100) /* Transmit Global Time */
+#define CAN_TXMDT0R_TIME                        ((uint32_t)0xFFFF0000) /* Message Time Stamp */
+
+/******************  Bit definition for CAN_TXMDL0R register  *******************/
+#define CAN_TXMDL0R_DATA0                       ((uint32_t)0x000000FF) /* Data byte 0 */
+#define CAN_TXMDL0R_DATA1                       ((uint32_t)0x0000FF00) /* Data byte 1 */
+#define CAN_TXMDL0R_DATA2                       ((uint32_t)0x00FF0000) /* Data byte 2 */
+#define CAN_TXMDL0R_DATA3                       ((uint32_t)0xFF000000) /* Data byte 3 */
+
+/******************  Bit definition for CAN_TXMDH0R register  *******************/
+#define CAN_TXMDH0R_DATA4                       ((uint32_t)0x000000FF) /* Data byte 4 */
+#define CAN_TXMDH0R_DATA5                       ((uint32_t)0x0000FF00) /* Data byte 5 */
+#define CAN_TXMDH0R_DATA6                       ((uint32_t)0x00FF0000) /* Data byte 6 */
+#define CAN_TXMDH0R_DATA7                       ((uint32_t)0xFF000000) /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI1R register  *******************/
+#define CAN_TXMI1R_TXRQ                         ((uint32_t)0x00000001) /* Transmit Mailbox Request */
+#define CAN_TXMI1R_RTR                          ((uint32_t)0x00000002) /* Remote Transmission Request */
+#define CAN_TXMI1R_IDE                          ((uint32_t)0x00000004) /* Identifier Extension */
+#define CAN_TXMI1R_EXID                         ((uint32_t)0x001FFFF8) /* Extended Identifier */
+#define CAN_TXMI1R_STID                         ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT1R register  ******************/
+#define CAN_TXMDT1R_DLC                         ((uint32_t)0x0000000F) /* Data Length Code */
+#define CAN_TXMDT1R_TGT                         ((uint32_t)0x00000100) /* Transmit Global Time */
+#define CAN_TXMDT1R_TIME                        ((uint32_t)0xFFFF0000) /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL1R register  ******************/
+#define CAN_TXMDL1R_DATA0                       ((uint32_t)0x000000FF) /* Data byte 0 */
+#define CAN_TXMDL1R_DATA1                       ((uint32_t)0x0000FF00) /* Data byte 1 */
+#define CAN_TXMDL1R_DATA2                       ((uint32_t)0x00FF0000) /* Data byte 2 */
+#define CAN_TXMDL1R_DATA3                       ((uint32_t)0xFF000000) /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH1R register  ******************/
+#define CAN_TXMDH1R_DATA4                       ((uint32_t)0x000000FF) /* Data byte 4 */
+#define CAN_TXMDH1R_DATA5                       ((uint32_t)0x0000FF00) /* Data byte 5 */
+#define CAN_TXMDH1R_DATA6                       ((uint32_t)0x00FF0000) /* Data byte 6 */
+#define CAN_TXMDH1R_DATA7                       ((uint32_t)0xFF000000) /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI2R register  *******************/
+#define CAN_TXMI2R_TXRQ                         ((uint32_t)0x00000001) /* Transmit Mailbox Request */
+#define CAN_TXMI2R_RTR                          ((uint32_t)0x00000002) /* Remote Transmission Request */
+#define CAN_TXMI2R_IDE                          ((uint32_t)0x00000004) /* Identifier Extension */
+#define CAN_TXMI2R_EXID                         ((uint32_t)0x001FFFF8) /* Extended identifier */
+#define CAN_TXMI2R_STID                         ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT2R register  ******************/
+#define CAN_TXMDT2R_DLC                         ((uint32_t)0x0000000F) /* Data Length Code */
+#define CAN_TXMDT2R_TGT                         ((uint32_t)0x00000100) /* Transmit Global Time */
+#define CAN_TXMDT2R_TIME                        ((uint32_t)0xFFFF0000) /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL2R register  ******************/
+#define CAN_TXMDL2R_DATA0                       ((uint32_t)0x000000FF) /* Data byte 0 */
+#define CAN_TXMDL2R_DATA1                       ((uint32_t)0x0000FF00) /* Data byte 1 */
+#define CAN_TXMDL2R_DATA2                       ((uint32_t)0x00FF0000) /* Data byte 2 */
+#define CAN_TXMDL2R_DATA3                       ((uint32_t)0xFF000000) /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH2R register  ******************/
+#define CAN_TXMDH2R_DATA4                       ((uint32_t)0x000000FF) /* Data byte 4 */
+#define CAN_TXMDH2R_DATA5                       ((uint32_t)0x0000FF00) /* Data byte 5 */
+#define CAN_TXMDH2R_DATA6                       ((uint32_t)0x00FF0000) /* Data byte 6 */
+#define CAN_TXMDH2R_DATA7                       ((uint32_t)0xFF000000) /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI0R register  *******************/
+#define CAN_RXMI0R_RTR                          ((uint32_t)0x00000002) /* Remote Transmission Request */
+#define CAN_RXMI0R_IDE                          ((uint32_t)0x00000004) /* Identifier Extension */
+#define CAN_RXMI0R_EXID                         ((uint32_t)0x001FFFF8) /* Extended Identifier */
+#define CAN_RXMI0R_STID                         ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT0R register  ******************/
+#define CAN_RXMDT0R_DLC                         ((uint32_t)0x0000000F) /* Data Length Code */
+#define CAN_RXMDT0R_FMI                         ((uint32_t)0x0000FF00) /* Filter Match Index */
+#define CAN_RXMDT0R_TIME                        ((uint32_t)0xFFFF0000) /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL0R register  ******************/
+#define CAN_RXMDL0R_DATA0                       ((uint32_t)0x000000FF) /* Data byte 0 */
+#define CAN_RXMDL0R_DATA1                       ((uint32_t)0x0000FF00) /* Data byte 1 */
+#define CAN_RXMDL0R_DATA2                       ((uint32_t)0x00FF0000) /* Data byte 2 */
+#define CAN_RXMDL0R_DATA3                       ((uint32_t)0xFF000000) /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH0R register  ******************/
+#define CAN_RXMDH0R_DATA4                       ((uint32_t)0x000000FF) /* Data byte 4 */
+#define CAN_RXMDH0R_DATA5                       ((uint32_t)0x0000FF00) /* Data byte 5 */
+#define CAN_RXMDH0R_DATA6                       ((uint32_t)0x00FF0000) /* Data byte 6 */
+#define CAN_RXMDH0R_DATA7                       ((uint32_t)0xFF000000) /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI1R register  *******************/
+#define CAN_RXMI1R_RTR                          ((uint32_t)0x00000002) /* Remote Transmission Request */
+#define CAN_RXMI1R_IDE                          ((uint32_t)0x00000004) /* Identifier Extension */
+#define CAN_RXMI1R_EXID                         ((uint32_t)0x001FFFF8) /* Extended identifier */
+#define CAN_RXMI1R_STID                         ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT1R register  ******************/
+#define CAN_RXMDT1R_DLC                         ((uint32_t)0x0000000F) /* Data Length Code */
+#define CAN_RXMDT1R_FMI                         ((uint32_t)0x0000FF00) /* Filter Match Index */
+#define CAN_RXMDT1R_TIME                        ((uint32_t)0xFFFF0000) /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL1R register  ******************/
+#define CAN_RXMDL1R_DATA0                       ((uint32_t)0x000000FF) /* Data byte 0 */
+#define CAN_RXMDL1R_DATA1                       ((uint32_t)0x0000FF00) /* Data byte 1 */
+#define CAN_RXMDL1R_DATA2                       ((uint32_t)0x00FF0000) /* Data byte 2 */
+#define CAN_RXMDL1R_DATA3                       ((uint32_t)0xFF000000) /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH1R register  ******************/
+#define CAN_RXMDH1R_DATA4                       ((uint32_t)0x000000FF) /* Data byte 4 */
+#define CAN_RXMDH1R_DATA5                       ((uint32_t)0x0000FF00) /* Data byte 5 */
+#define CAN_RXMDH1R_DATA6                       ((uint32_t)0x00FF0000) /* Data byte 6 */
+#define CAN_RXMDH1R_DATA7                       ((uint32_t)0xFF000000) /* Data byte 7 */
+
+/*******************  Bit definition for CAN_FCTLR register  ********************/
+#define CAN_FCTLR_FINIT                         ((uint8_t)0x01) /* Filter Init Mode */
+
+/*******************  Bit definition for CAN_FMCFGR register  *******************/
+#define CAN_FMCFGR_FBM                          ((uint16_t)0x3FFF) /* Filter Mode */
+#define CAN_FMCFGR_FBM0                         ((uint16_t)0x0001) /* Filter Init Mode bit 0 */
+#define CAN_FMCFGR_FBM1                         ((uint16_t)0x0002) /* Filter Init Mode bit 1 */
+#define CAN_FMCFGR_FBM2                         ((uint16_t)0x0004) /* Filter Init Mode bit 2 */
+#define CAN_FMCFGR_FBM3                         ((uint16_t)0x0008) /* Filter Init Mode bit 3 */
+#define CAN_FMCFGR_FBM4                         ((uint16_t)0x0010) /* Filter Init Mode bit 4 */
+#define CAN_FMCFGR_FBM5                         ((uint16_t)0x0020) /* Filter Init Mode bit 5 */
+#define CAN_FMCFGR_FBM6                         ((uint16_t)0x0040) /* Filter Init Mode bit 6 */
+#define CAN_FMCFGR_FBM7                         ((uint16_t)0x0080) /* Filter Init Mode bit 7 */
+#define CAN_FMCFGR_FBM8                         ((uint16_t)0x0100) /* Filter Init Mode bit 8 */
+#define CAN_FMCFGR_FBM9                         ((uint16_t)0x0200) /* Filter Init Mode bit 9 */
+#define CAN_FMCFGR_FBM10                        ((uint16_t)0x0400) /* Filter Init Mode bit 10 */
+#define CAN_FMCFGR_FBM11                        ((uint16_t)0x0800) /* Filter Init Mode bit 11 */
+#define CAN_FMCFGR_FBM12                        ((uint16_t)0x1000) /* Filter Init Mode bit 12 */
+#define CAN_FMCFGR_FBM13                        ((uint16_t)0x2000) /* Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FSCFGR register  *******************/
+#define CAN_FSCFGR_FSC                          ((uint16_t)0x3FFF) /* Filter Scale Configuration */
+#define CAN_FSCFGR_FSC0                         ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */
+#define CAN_FSCFGR_FSC1                         ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */
+#define CAN_FSCFGR_FSC2                         ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */
+#define CAN_FSCFGR_FSC3                         ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */
+#define CAN_FSCFGR_FSC4                         ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */
+#define CAN_FSCFGR_FSC5                         ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */
+#define CAN_FSCFGR_FSC6                         ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */
+#define CAN_FSCFGR_FSC7                         ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */
+#define CAN_FSCFGR_FSC8                         ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */
+#define CAN_FSCFGR_FSC9                         ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */
+#define CAN_FSCFGR_FSC10                        ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */
+#define CAN_FSCFGR_FSC11                        ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */
+#define CAN_FSCFGR_FSC12                        ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */
+#define CAN_FSCFGR_FSC13                        ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FAFIFOR register  *******************/
+#define CAN_FAFIFOR_FFA                         ((uint16_t)0x3FFF) /* Filter FIFO Assignment */
+#define CAN_FAFIFOR_FFA0                        ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */
+#define CAN_FAFIFOR_FFA1                        ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */
+#define CAN_FAFIFOR_FFA2                        ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */
+#define CAN_FAFIFOR_FFA3                        ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */
+#define CAN_FAFIFOR_FFA4                        ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */
+#define CAN_FAFIFOR_FFA5                        ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */
+#define CAN_FAFIFOR_FFA6                        ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */
+#define CAN_FAFIFOR_FFA7                        ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */
+#define CAN_FAFIFOR_FFA8                        ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */
+#define CAN_FAFIFOR_FFA9                        ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */
+#define CAN_FAFIFOR_FFA10                       ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */
+#define CAN_FAFIFOR_FFA11                       ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */
+#define CAN_FAFIFOR_FFA12                       ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */
+#define CAN_FAFIFOR_FFA13                       ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FWR register  *******************/
+#define CAN_FWR_FACT                            ((uint16_t)0x3FFF) /* Filter Active */
+#define CAN_FWR_FACT0                           ((uint16_t)0x0001) /* Filter 0 Active */
+#define CAN_FWR_FACT1                           ((uint16_t)0x0002) /* Filter 1 Active */
+#define CAN_FWR_FACT2                           ((uint16_t)0x0004) /* Filter 2 Active */
+#define CAN_FWR_FACT3                           ((uint16_t)0x0008) /* Filter 3 Active */
+#define CAN_FWR_FACT4                           ((uint16_t)0x0010) /* Filter 4 Active */
+#define CAN_FWR_FACT5                           ((uint16_t)0x0020) /* Filter 5 Active */
+#define CAN_FWR_FACT6                           ((uint16_t)0x0040) /* Filter 6 Active */
+#define CAN_FWR_FACT7                           ((uint16_t)0x0080) /* Filter 7 Active */
+#define CAN_FWR_FACT8                           ((uint16_t)0x0100) /* Filter 8 Active */
+#define CAN_FWR_FACT9                           ((uint16_t)0x0200) /* Filter 9 Active */
+#define CAN_FWR_FACT10                          ((uint16_t)0x0400) /* Filter 10 Active */
+#define CAN_FWR_FACT11                          ((uint16_t)0x0800) /* Filter 11 Active */
+#define CAN_FWR_FACT12                          ((uint16_t)0x1000) /* Filter 12 Active */
+#define CAN_FWR_FACT13                          ((uint16_t)0x2000) /* Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F0R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F0R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F0R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F0R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F0R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F0R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F0R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F0R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F0R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F0R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F0R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F0R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F0R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F0R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F0R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F0R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F0R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F0R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F0R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F0R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F0R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F0R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F0R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F0R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F0R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F0R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F0R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F0R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F0R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F0R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F0R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F1R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F1R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F1R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F1R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F1R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F1R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F1R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F1R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F1R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F1R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F1R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F1R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F1R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F1R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F1R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F1R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F1R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F1R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F1R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F1R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F1R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F1R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F1R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F1R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F1R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F1R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F1R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F1R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F1R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F1R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F1R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F2R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F2R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F2R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F2R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F2R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F2R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F2R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F2R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F2R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F2R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F2R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F2R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F2R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F2R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F2R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F2R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F2R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F2R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F2R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F2R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F2R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F2R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F2R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F2R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F2R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F2R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F2R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F2R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F2R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F2R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F2R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F3R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F3R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F3R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F3R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F3R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F3R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F3R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F3R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F3R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F3R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F3R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F3R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F3R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F3R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F3R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F3R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F3R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F3R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F3R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F3R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F3R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F3R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F3R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F3R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F3R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F3R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F3R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F3R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F3R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F3R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F3R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F4R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F4R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F4R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F4R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F4R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F4R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F4R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F4R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F4R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F4R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F4R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F4R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F4R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F4R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F4R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F4R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F4R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F4R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F4R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F4R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F4R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F4R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F4R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F4R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F4R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F4R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F4R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F4R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F4R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F4R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F4R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F5R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F5R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F5R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F5R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F5R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F5R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F5R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F5R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F5R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F5R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F5R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F5R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F5R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F5R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F5R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F5R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F5R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F5R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F5R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F5R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F5R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F5R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F5R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F5R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F5R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F5R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F5R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F5R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F5R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F5R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F5R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F6R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F6R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F6R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F6R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F6R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F6R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F6R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F6R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F6R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F6R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F6R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F6R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F6R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F6R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F6R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F6R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F6R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F6R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F6R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F6R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F6R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F6R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F6R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F6R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F6R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F6R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F6R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F6R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F6R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F6R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F6R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F7R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F7R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F7R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F7R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F7R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F7R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F7R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F7R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F7R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F7R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F7R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F7R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F7R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F7R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F7R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F7R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F7R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F7R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F7R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F7R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F7R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F7R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F7R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F7R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F7R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F7R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F7R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F7R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F7R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F7R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F7R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F8R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F8R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F8R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F8R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F8R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F8R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F8R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F8R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F8R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F8R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F8R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F8R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F8R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F8R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F8R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F8R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F8R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F8R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F8R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F8R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F8R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F8R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F8R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F8R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F8R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F8R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F8R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F8R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F8R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F8R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F8R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F9R1_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F9R1_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F9R1_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F9R1_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F9R1_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F9R1_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F9R1_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F9R1_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F9R1_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F9R1_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F9R1_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F9R1_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F9R1_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F9R1_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F9R1_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F9R1_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F9R1_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F9R1_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F9R1_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F9R1_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F9R1_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F9R1_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F9R1_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F9R1_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F9R1_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F9R1_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F9R1_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F9R1_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F9R1_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F9R1_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F9R1_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F10R1_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F10R1_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F10R1_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F10R1_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F10R1_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F10R1_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F10R1_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F10R1_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F10R1_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F10R1_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F10R1_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F10R1_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F10R1_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F10R1_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F10R1_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F10R1_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F10R1_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F10R1_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F10R1_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F10R1_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F10R1_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F10R1_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F10R1_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F10R1_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F10R1_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F10R1_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F10R1_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F10R1_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F10R1_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F10R1_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F10R1_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F11R1_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F11R1_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F11R1_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F11R1_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F11R1_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F11R1_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F11R1_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F11R1_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F11R1_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F11R1_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F11R1_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F11R1_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F11R1_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F11R1_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F11R1_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F11R1_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F11R1_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F11R1_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F11R1_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F11R1_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F11R1_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F11R1_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F11R1_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F11R1_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F11R1_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F11R1_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F11R1_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F11R1_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F11R1_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F11R1_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F11R1_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F12R1_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F12R1_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F12R1_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F12R1_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F12R1_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F12R1_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F12R1_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F12R1_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F12R1_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F12R1_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F12R1_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F12R1_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F12R1_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F12R1_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F12R1_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F12R1_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F12R1_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F12R1_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F12R1_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F12R1_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F12R1_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F12R1_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F12R1_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F12R1_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F12R1_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F12R1_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F12R1_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F12R1_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F12R1_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F12R1_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F12R1_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F13R1_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F13R1_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F13R1_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F13R1_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F13R1_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F13R1_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F13R1_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F13R1_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F13R1_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F13R1_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F13R1_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F13R1_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F13R1_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F13R1_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F13R1_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F13R1_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F13R1_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F13R1_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F13R1_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F13R1_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F13R1_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F13R1_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F13R1_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F13R1_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F13R1_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F13R1_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F13R1_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F13R1_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F13R1_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F13R1_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F13R1_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F0R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F0R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F0R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F0R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F0R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F0R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F0R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F0R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F0R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F0R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F0R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F0R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F0R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F0R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F0R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F0R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F0R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F0R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F0R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F0R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F0R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F0R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F0R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F0R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F0R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F0R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F0R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F0R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F0R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F0R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F0R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F1R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F1R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F1R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F1R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F1R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F1R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F1R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F1R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F1R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F1R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F1R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F1R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F1R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F1R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F1R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F1R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F1R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F1R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F1R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F1R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F1R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F1R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F1R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F1R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F1R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F1R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F1R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F1R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F1R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F1R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F1R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F2R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F2R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F2R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F2R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F2R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F2R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F2R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F2R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F2R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F2R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F2R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F2R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F2R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F2R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F2R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F2R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F2R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F2R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F2R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F2R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F2R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F2R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F2R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F2R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F2R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F2R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F2R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F2R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F2R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F2R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F2R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F3R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F3R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F3R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F3R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F3R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F3R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F3R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F3R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F3R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F3R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F3R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F3R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F3R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F3R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F3R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F3R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F3R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F3R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F3R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F3R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F3R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F3R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F3R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F3R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F3R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F3R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F3R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F3R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F3R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F3R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F3R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F4R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F4R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F4R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F4R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F4R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F4R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F4R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F4R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F4R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F4R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F4R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F4R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F4R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F4R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F4R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F4R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F4R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F4R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F4R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F4R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F4R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F4R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F4R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F4R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F4R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F4R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F4R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F4R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F4R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F4R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F4R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F5R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F5R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F5R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F5R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F5R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F5R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F5R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F5R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F5R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F5R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F5R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F5R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F5R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F5R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F5R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F5R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F5R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F5R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F5R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F5R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F5R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F5R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F5R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F5R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F5R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F5R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F5R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F5R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F5R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F5R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F5R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F6R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F6R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F6R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F6R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F6R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F6R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F6R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F6R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F6R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F6R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F6R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F6R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F6R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F6R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F6R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F6R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F6R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F6R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F6R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F6R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F6R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F6R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F6R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F6R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F6R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F6R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F6R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F6R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F6R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F6R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F6R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F7R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F7R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F7R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F7R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F7R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F7R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F7R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F7R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F7R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F7R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F7R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F7R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F7R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F7R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F7R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F7R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F7R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F7R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F7R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F7R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F7R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F7R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F7R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F7R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F7R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F7R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F7R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F7R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F7R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F7R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F7R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F8R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F8R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F8R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F8R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F8R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F8R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F8R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F8R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F8R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F8R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F8R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F8R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F8R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F8R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F8R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F8R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F8R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F8R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F8R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F8R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F8R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F8R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F8R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F8R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F8R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F8R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F8R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F8R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F8R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F8R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F8R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0                            ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F9R2_FB1                            ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F9R2_FB2                            ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F9R2_FB3                            ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F9R2_FB4                            ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F9R2_FB5                            ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F9R2_FB6                            ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F9R2_FB7                            ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F9R2_FB8                            ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F9R2_FB9                            ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F9R2_FB10                           ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F9R2_FB11                           ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F9R2_FB12                           ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F9R2_FB13                           ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F9R2_FB14                           ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F9R2_FB15                           ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F9R2_FB16                           ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F9R2_FB17                           ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F9R2_FB18                           ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F9R2_FB19                           ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F9R2_FB20                           ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F9R2_FB21                           ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F9R2_FB22                           ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F9R2_FB23                           ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F9R2_FB24                           ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F9R2_FB25                           ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F9R2_FB26                           ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F9R2_FB27                           ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F9R2_FB28                           ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F9R2_FB29                           ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F9R2_FB30                           ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F9R2_FB31                           ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F10R2_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F10R2_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F10R2_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F10R2_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F10R2_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F10R2_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F10R2_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F10R2_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F10R2_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F10R2_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F10R2_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F10R2_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F10R2_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F10R2_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F10R2_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F10R2_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F10R2_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F10R2_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F10R2_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F10R2_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F10R2_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F10R2_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F10R2_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F10R2_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F10R2_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F10R2_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F10R2_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F10R2_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F10R2_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F10R2_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F10R2_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F11R2_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F11R2_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F11R2_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F11R2_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F11R2_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F11R2_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F11R2_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F11R2_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F11R2_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F11R2_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F11R2_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F11R2_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F11R2_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F11R2_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F11R2_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F11R2_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F11R2_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F11R2_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F11R2_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F11R2_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F11R2_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F11R2_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F11R2_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F11R2_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F11R2_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F11R2_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F11R2_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F11R2_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F11R2_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F11R2_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F11R2_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F12R2_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F12R2_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F12R2_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F12R2_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F12R2_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F12R2_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F12R2_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F12R2_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F12R2_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F12R2_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F12R2_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F12R2_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F12R2_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F12R2_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F12R2_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F12R2_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F12R2_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F12R2_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F12R2_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F12R2_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F12R2_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F12R2_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F12R2_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F12R2_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F12R2_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F12R2_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F12R2_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F12R2_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F12R2_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F12R2_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F12R2_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0                           ((uint32_t)0x00000001) /* Filter bit 0 */
+#define CAN_F13R2_FB1                           ((uint32_t)0x00000002) /* Filter bit 1 */
+#define CAN_F13R2_FB2                           ((uint32_t)0x00000004) /* Filter bit 2 */
+#define CAN_F13R2_FB3                           ((uint32_t)0x00000008) /* Filter bit 3 */
+#define CAN_F13R2_FB4                           ((uint32_t)0x00000010) /* Filter bit 4 */
+#define CAN_F13R2_FB5                           ((uint32_t)0x00000020) /* Filter bit 5 */
+#define CAN_F13R2_FB6                           ((uint32_t)0x00000040) /* Filter bit 6 */
+#define CAN_F13R2_FB7                           ((uint32_t)0x00000080) /* Filter bit 7 */
+#define CAN_F13R2_FB8                           ((uint32_t)0x00000100) /* Filter bit 8 */
+#define CAN_F13R2_FB9                           ((uint32_t)0x00000200) /* Filter bit 9 */
+#define CAN_F13R2_FB10                          ((uint32_t)0x00000400) /* Filter bit 10 */
+#define CAN_F13R2_FB11                          ((uint32_t)0x00000800) /* Filter bit 11 */
+#define CAN_F13R2_FB12                          ((uint32_t)0x00001000) /* Filter bit 12 */
+#define CAN_F13R2_FB13                          ((uint32_t)0x00002000) /* Filter bit 13 */
+#define CAN_F13R2_FB14                          ((uint32_t)0x00004000) /* Filter bit 14 */
+#define CAN_F13R2_FB15                          ((uint32_t)0x00008000) /* Filter bit 15 */
+#define CAN_F13R2_FB16                          ((uint32_t)0x00010000) /* Filter bit 16 */
+#define CAN_F13R2_FB17                          ((uint32_t)0x00020000) /* Filter bit 17 */
+#define CAN_F13R2_FB18                          ((uint32_t)0x00040000) /* Filter bit 18 */
+#define CAN_F13R2_FB19                          ((uint32_t)0x00080000) /* Filter bit 19 */
+#define CAN_F13R2_FB20                          ((uint32_t)0x00100000) /* Filter bit 20 */
+#define CAN_F13R2_FB21                          ((uint32_t)0x00200000) /* Filter bit 21 */
+#define CAN_F13R2_FB22                          ((uint32_t)0x00400000) /* Filter bit 22 */
+#define CAN_F13R2_FB23                          ((uint32_t)0x00800000) /* Filter bit 23 */
+#define CAN_F13R2_FB24                          ((uint32_t)0x01000000) /* Filter bit 24 */
+#define CAN_F13R2_FB25                          ((uint32_t)0x02000000) /* Filter bit 25 */
+#define CAN_F13R2_FB26                          ((uint32_t)0x04000000) /* Filter bit 26 */
+#define CAN_F13R2_FB27                          ((uint32_t)0x08000000) /* Filter bit 27 */
+#define CAN_F13R2_FB28                          ((uint32_t)0x10000000) /* Filter bit 28 */
+#define CAN_F13R2_FB29                          ((uint32_t)0x20000000) /* Filter bit 29 */
+#define CAN_F13R2_FB30                          ((uint32_t)0x40000000) /* Filter bit 30 */
+#define CAN_F13R2_FB31                          ((uint32_t)0x80000000) /* Filter bit 31 */
+
+/******************************************************************************/
+/*                          CRC Calculation Unit                              */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DATAR register  *********************/
+#define CRC_DATAR_DR                            ((uint32_t)0xFFFFFFFF) /* Data register bits */
+
+/*******************  Bit definition for CRC_IDATAR register  ********************/
+#define CRC_IDR_IDATAR                          ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CTLR register  ********************/
+#define CRC_CTLR_RESET                          ((uint8_t)0x01) /* RESET bit */
+
+/******************************************************************************/
+/*                             DMA Controller                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTFR register  ********************/
+#define DMA_GIF1                                ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */
+#define DMA_TCIF1                               ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */
+#define DMA_HTIF1                               ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */
+#define DMA_TEIF1                               ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */
+#define DMA_GIF2                                ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */
+#define DMA_TCIF2                               ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */
+#define DMA_HTIF2                               ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */
+#define DMA_TEIF2                               ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */
+#define DMA_GIF3                                ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */
+#define DMA_TCIF3                               ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */
+#define DMA_HTIF3                               ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */
+#define DMA_TEIF3                               ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */
+#define DMA_GIF4                                ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */
+#define DMA_TCIF4                               ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */
+#define DMA_HTIF4                               ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */
+#define DMA_TEIF4                               ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */
+#define DMA_GIF5                                ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */
+#define DMA_TCIF5                               ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */
+#define DMA_HTIF5                               ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */
+#define DMA_TEIF5                               ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */
+#define DMA_GIF6                                ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */
+#define DMA_TCIF6                               ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */
+#define DMA_HTIF6                               ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */
+#define DMA_TEIF6                               ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */
+#define DMA_GIF7                                ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */
+#define DMA_TCIF7                               ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */
+#define DMA_HTIF7                               ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
+#define DMA_TEIF7                               ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
+
+#define DMA_GIF8                                ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */
+#define DMA_TCIF8                               ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */
+#define DMA_HTIF8                               ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */
+#define DMA_TEIF8                               ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */
+#define DMA_GIF9                                ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */
+#define DMA_TCIF9                               ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */
+#define DMA_HTIF9                               ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */
+#define DMA_TEIF9                               ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */
+#define DMA_GIF10                               ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */
+#define DMA_TCIF10                              ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */
+#define DMA_HTIF10                              ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */
+#define DMA_TEIF10                              ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */
+#define DMA_GIF11                               ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */
+#define DMA_TCIF11                              ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */
+#define DMA_HTIF11                              ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */
+#define DMA_TEIF11                              ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTFCR register  *******************/
+#define DMA_CGIF1                               ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
+#define DMA_CTCIF1                              ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
+#define DMA_CHTIF1                              ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */
+#define DMA_CTEIF1                              ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */
+#define DMA_CGIF2                               ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */
+#define DMA_CTCIF2                              ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */
+#define DMA_CHTIF2                              ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */
+#define DMA_CTEIF2                              ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */
+#define DMA_CGIF3                               ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */
+#define DMA_CTCIF3                              ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */
+#define DMA_CHTIF3                              ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */
+#define DMA_CTEIF3                              ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */
+#define DMA_CGIF4                               ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */
+#define DMA_CTCIF4                              ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */
+#define DMA_CHTIF4                              ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */
+#define DMA_CTEIF4                              ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */
+#define DMA_CGIF5                               ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */
+#define DMA_CTCIF5                              ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */
+#define DMA_CHTIF5                              ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */
+#define DMA_CTEIF5                              ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */
+#define DMA_CGIF6                               ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */
+#define DMA_CTCIF6                              ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */
+#define DMA_CHTIF6                              ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */
+#define DMA_CTEIF6                              ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */
+#define DMA_CGIF7                               ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */
+#define DMA_CTCIF7                              ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */
+#define DMA_CHTIF7                              ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */
+#define DMA_CTEIF7                              ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CFGR1 register  *******************/
+#define DMA_CFGR1_EN                            ((uint16_t)0x0001) /* Channel enable*/
+#define DMA_CFGR1_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR1_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR1_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR1_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR1_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR1_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR1_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR1_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR1_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR1_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR1_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR1_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR1_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR1_PL                            ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */
+#define DMA_CFGR1_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR1_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR1_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR2 register  *******************/
+#define DMA_CFGR2_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR2_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR2_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR2_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR2_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR2_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR2_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR2_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR2_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR2_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR2_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR2_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR2_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR2_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR2_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR2_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR2_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR2_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR3 register  *******************/
+#define DMA_CFGR3_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR3_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR3_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR3_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR3_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR3_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR3_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR3_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR3_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR3_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR3_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR3_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR3_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR3_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR3_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR3_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR3_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR3_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG4 register  *******************/
+#define DMA_CFG4_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG4_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG4_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG4_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG4_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG4_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG4_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG4_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG4_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG4_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG4_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG4_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG4_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG4_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG4_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG4_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG4_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG4_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/******************  Bit definition for DMA_CFG5 register  *******************/
+#define DMA_CFG5_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG5_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG5_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG5_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG5_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG5_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG5_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG5_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG5_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG5_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG5_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG5_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG5_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG5_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG5_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG5_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG5_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG5_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CFG6 register  *******************/
+#define DMA_CFG6_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG6_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG6_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG6_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG6_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG6_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG6_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG6_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG6_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG6_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG6_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG6_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG6_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG6_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG6_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG6_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG6_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG6_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG7 register  *******************/
+#define DMA_CFG7_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG7_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG7_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG7_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG7_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG7_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG7_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG7_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG7_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG7_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG7_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG7_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG7_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG7_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG7_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG7_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG7_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG7_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNTR1 register  ******************/
+#define DMA_CNTR1_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR2 register  ******************/
+#define DMA_CNTR2_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR3 register  ******************/
+#define DMA_CNTR3_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR4 register  ******************/
+#define DMA_CNTR4_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR5 register  ******************/
+#define DMA_CNTR5_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR6 register  ******************/
+#define DMA_CNTR6_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR7 register  ******************/
+#define DMA_CNTR7_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define DMA_PADDR1_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define DMA_PADDR2_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define DMA_PADDR3_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define DMA_PADDR4_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define DMA_PADDR5_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define DMA_PADDR6_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define DMA_PADDR7_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define DMA_MADDR1_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define DMA_MADDR2_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define DMA_MADDR3_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define DMA_MADDR4_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define DMA_MADDR5_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define DMA_MADDR6_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define DMA_MADDR7_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************************************************************************/
+/*                    External Interrupt/Event Controller                     */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTENR register  *******************/
+#define EXTI_INTENR_MR0                         ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */
+#define EXTI_INTENR_MR1                         ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */
+#define EXTI_INTENR_MR2                         ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */
+#define EXTI_INTENR_MR3                         ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */
+#define EXTI_INTENR_MR4                         ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */
+#define EXTI_INTENR_MR5                         ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */
+#define EXTI_INTENR_MR6                         ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */
+#define EXTI_INTENR_MR7                         ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */
+#define EXTI_INTENR_MR8                         ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */
+#define EXTI_INTENR_MR9                         ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */
+#define EXTI_INTENR_MR10                        ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */
+#define EXTI_INTENR_MR11                        ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */
+#define EXTI_INTENR_MR12                        ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */
+#define EXTI_INTENR_MR13                        ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */
+#define EXTI_INTENR_MR14                        ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */
+#define EXTI_INTENR_MR15                        ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */
+#define EXTI_INTENR_MR16                        ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */
+#define EXTI_INTENR_MR17                        ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */
+#define EXTI_INTENR_MR18                        ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */
+#define EXTI_INTENR_MR19                        ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVENR register  *******************/
+#define EXTI_EVENR_MR0                          ((uint32_t)0x00000001) /* Event Mask on line 0 */
+#define EXTI_EVENR_MR1                          ((uint32_t)0x00000002) /* Event Mask on line 1 */
+#define EXTI_EVENR_MR2                          ((uint32_t)0x00000004) /* Event Mask on line 2 */
+#define EXTI_EVENR_MR3                          ((uint32_t)0x00000008) /* Event Mask on line 3 */
+#define EXTI_EVENR_MR4                          ((uint32_t)0x00000010) /* Event Mask on line 4 */
+#define EXTI_EVENR_MR5                          ((uint32_t)0x00000020) /* Event Mask on line 5 */
+#define EXTI_EVENR_MR6                          ((uint32_t)0x00000040) /* Event Mask on line 6 */
+#define EXTI_EVENR_MR7                          ((uint32_t)0x00000080) /* Event Mask on line 7 */
+#define EXTI_EVENR_MR8                          ((uint32_t)0x00000100) /* Event Mask on line 8 */
+#define EXTI_EVENR_MR9                          ((uint32_t)0x00000200) /* Event Mask on line 9 */
+#define EXTI_EVENR_MR10                         ((uint32_t)0x00000400) /* Event Mask on line 10 */
+#define EXTI_EVENR_MR11                         ((uint32_t)0x00000800) /* Event Mask on line 11 */
+#define EXTI_EVENR_MR12                         ((uint32_t)0x00001000) /* Event Mask on line 12 */
+#define EXTI_EVENR_MR13                         ((uint32_t)0x00002000) /* Event Mask on line 13 */
+#define EXTI_EVENR_MR14                         ((uint32_t)0x00004000) /* Event Mask on line 14 */
+#define EXTI_EVENR_MR15                         ((uint32_t)0x00008000) /* Event Mask on line 15 */
+#define EXTI_EVENR_MR16                         ((uint32_t)0x00010000) /* Event Mask on line 16 */
+#define EXTI_EVENR_MR17                         ((uint32_t)0x00020000) /* Event Mask on line 17 */
+#define EXTI_EVENR_MR18                         ((uint32_t)0x00040000) /* Event Mask on line 18 */
+#define EXTI_EVENR_MR19                         ((uint32_t)0x00080000) /* Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTENR register  *******************/
+#define EXTI_RTENR_TR0                          ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */
+#define EXTI_RTENR_TR1                          ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */
+#define EXTI_RTENR_TR2                          ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */
+#define EXTI_RTENR_TR3                          ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */
+#define EXTI_RTENR_TR4                          ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */
+#define EXTI_RTENR_TR5                          ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */
+#define EXTI_RTENR_TR6                          ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */
+#define EXTI_RTENR_TR7                          ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */
+#define EXTI_RTENR_TR8                          ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */
+#define EXTI_RTENR_TR9                          ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */
+#define EXTI_RTENR_TR10                         ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */
+#define EXTI_RTENR_TR11                         ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */
+#define EXTI_RTENR_TR12                         ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */
+#define EXTI_RTENR_TR13                         ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */
+#define EXTI_RTENR_TR14                         ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */
+#define EXTI_RTENR_TR15                         ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */
+#define EXTI_RTENR_TR16                         ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */
+#define EXTI_RTENR_TR17                         ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */
+#define EXTI_RTENR_TR18                         ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */
+#define EXTI_RTENR_TR19                         ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTENR register  *******************/
+#define EXTI_FTENR_TR0                          ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */
+#define EXTI_FTENR_TR1                          ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */
+#define EXTI_FTENR_TR2                          ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */
+#define EXTI_FTENR_TR3                          ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */
+#define EXTI_FTENR_TR4                          ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */
+#define EXTI_FTENR_TR5                          ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */
+#define EXTI_FTENR_TR6                          ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */
+#define EXTI_FTENR_TR7                          ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */
+#define EXTI_FTENR_TR8                          ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */
+#define EXTI_FTENR_TR9                          ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */
+#define EXTI_FTENR_TR10                         ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */
+#define EXTI_FTENR_TR11                         ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */
+#define EXTI_FTENR_TR12                         ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */
+#define EXTI_FTENR_TR13                         ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */
+#define EXTI_FTENR_TR14                         ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */
+#define EXTI_FTENR_TR15                         ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */
+#define EXTI_FTENR_TR16                         ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */
+#define EXTI_FTENR_TR17                         ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */
+#define EXTI_FTENR_TR18                         ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */
+#define EXTI_FTENR_TR19                         ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIEVR register  ******************/
+#define EXTI_SWIEVR_SWIEVR0                     ((uint32_t)0x00000001) /* Software Interrupt on line 0 */
+#define EXTI_SWIEVR_SWIEVR1                     ((uint32_t)0x00000002) /* Software Interrupt on line 1 */
+#define EXTI_SWIEVR_SWIEVR2                     ((uint32_t)0x00000004) /* Software Interrupt on line 2 */
+#define EXTI_SWIEVR_SWIEVR3                     ((uint32_t)0x00000008) /* Software Interrupt on line 3 */
+#define EXTI_SWIEVR_SWIEVR4                     ((uint32_t)0x00000010) /* Software Interrupt on line 4 */
+#define EXTI_SWIEVR_SWIEVR5                     ((uint32_t)0x00000020) /* Software Interrupt on line 5 */
+#define EXTI_SWIEVR_SWIEVR6                     ((uint32_t)0x00000040) /* Software Interrupt on line 6 */
+#define EXTI_SWIEVR_SWIEVR7                     ((uint32_t)0x00000080) /* Software Interrupt on line 7 */
+#define EXTI_SWIEVR_SWIEVR8                     ((uint32_t)0x00000100) /* Software Interrupt on line 8 */
+#define EXTI_SWIEVR_SWIEVR9                     ((uint32_t)0x00000200) /* Software Interrupt on line 9 */
+#define EXTI_SWIEVR_SWIEVR10                    ((uint32_t)0x00000400) /* Software Interrupt on line 10 */
+#define EXTI_SWIEVR_SWIEVR11                    ((uint32_t)0x00000800) /* Software Interrupt on line 11 */
+#define EXTI_SWIEVR_SWIEVR12                    ((uint32_t)0x00001000) /* Software Interrupt on line 12 */
+#define EXTI_SWIEVR_SWIEVR13                    ((uint32_t)0x00002000) /* Software Interrupt on line 13 */
+#define EXTI_SWIEVR_SWIEVR14                    ((uint32_t)0x00004000) /* Software Interrupt on line 14 */
+#define EXTI_SWIEVR_SWIEVR15                    ((uint32_t)0x00008000) /* Software Interrupt on line 15 */
+#define EXTI_SWIEVR_SWIEVR16                    ((uint32_t)0x00010000) /* Software Interrupt on line 16 */
+#define EXTI_SWIEVR_SWIEVR17                    ((uint32_t)0x00020000) /* Software Interrupt on line 17 */
+#define EXTI_SWIEVR_SWIEVR18                    ((uint32_t)0x00040000) /* Software Interrupt on line 18 */
+#define EXTI_SWIEVR_SWIEVR19                    ((uint32_t)0x00080000) /* Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_INTFR register  ********************/
+#define EXTI_INTF_INTF0                         ((uint32_t)0x00000001) /* Pending bit for line 0 */
+#define EXTI_INTF_INTF1                         ((uint32_t)0x00000002) /* Pending bit for line 1 */
+#define EXTI_INTF_INTF2                         ((uint32_t)0x00000004) /* Pending bit for line 2 */
+#define EXTI_INTF_INTF3                         ((uint32_t)0x00000008) /* Pending bit for line 3 */
+#define EXTI_INTF_INTF4                         ((uint32_t)0x00000010) /* Pending bit for line 4 */
+#define EXTI_INTF_INTF5                         ((uint32_t)0x00000020) /* Pending bit for line 5 */
+#define EXTI_INTF_INTF6                         ((uint32_t)0x00000040) /* Pending bit for line 6 */
+#define EXTI_INTF_INTF7                         ((uint32_t)0x00000080) /* Pending bit for line 7 */
+#define EXTI_INTF_INTF8                         ((uint32_t)0x00000100) /* Pending bit for line 8 */
+#define EXTI_INTF_INTF9                         ((uint32_t)0x00000200) /* Pending bit for line 9 */
+#define EXTI_INTF_INTF10                        ((uint32_t)0x00000400) /* Pending bit for line 10 */
+#define EXTI_INTF_INTF11                        ((uint32_t)0x00000800) /* Pending bit for line 11 */
+#define EXTI_INTF_INTF12                        ((uint32_t)0x00001000) /* Pending bit for line 12 */
+#define EXTI_INTF_INTF13                        ((uint32_t)0x00002000) /* Pending bit for line 13 */
+#define EXTI_INTF_INTF14                        ((uint32_t)0x00004000) /* Pending bit for line 14 */
+#define EXTI_INTF_INTF15                        ((uint32_t)0x00008000) /* Pending bit for line 15 */
+#define EXTI_INTF_INTF16                        ((uint32_t)0x00010000) /* Pending bit for line 16 */
+#define EXTI_INTF_INTF17                        ((uint32_t)0x00020000) /* Pending bit for line 17 */
+#define EXTI_INTF_INTF18                        ((uint32_t)0x00040000) /* Pending bit for line 18 */
+#define EXTI_INTF_INTF19                        ((uint32_t)0x00080000) /* Pending bit for line 19 */
+
+/******************************************************************************/
+/*                      FLASH and Option Bytes Registers                      */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACTLR register  ******************/
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define FLASH_KEYR_FKEYR                        ((uint32_t)0xFFFFFFFF) /* FPEC Key */
+
+/*****************  Bit definition for FLASH_OBKEYR register  ****************/
+#define FLASH_OBKEYR_OBKEYR                     ((uint32_t)0xFFFFFFFF) /* Option Byte Key */
+
+/******************  Bit definition for FLASH_STATR register  *******************/
+#define FLASH_STATR_BSY                         ((uint8_t)0x01) /* Busy */
+#define FLASH_STATR_PGERR                       ((uint8_t)0x04) /* Programming Error */
+#define FLASH_STATR_WRPRTERR                    ((uint8_t)0x10) /* Write Protection Error */
+#define FLASH_STATR_EOP                         ((uint8_t)0x20) /* End of operation */
+
+/*******************  Bit definition for FLASH_CTLR register  *******************/
+#define FLASH_CTLR_PG                           ((uint32_t)0x00000001) /* Programming */
+#define FLASH_CTLR_PER                          ((uint32_t)0x00000002) /* Sector Erase 4K */
+#define FLASH_CTLR_MER                          ((uint32_t)0x00000004) /* Mass Erase */
+#define FLASH_CTLR_OPTPG                        ((uint32_t)0x00000010) /* Option Byte Programming */
+#define FLASH_CTLR_OPTER                        ((uint32_t)0x00000020) /* Option Byte Erase */
+#define FLASH_CTLR_STRT                         ((uint32_t)0x00000040) /* Start */
+#define FLASH_CTLR_LOCK                         ((uint32_t)0x00000080) /* Lock */
+#define FLASH_CTLR_OPTWRE                       ((uint32_t)0x00000200) /* Option Bytes Write Enable */
+#define FLASH_CTLR_ERRIE                        ((uint32_t)0x00000400) /* Error Interrupt Enable */
+#define FLASH_CTLR_EOPIE                        ((uint32_t)0x00001000) /* End of operation interrupt enable */
+#define FLASH_CTLR_FAST_LOCK                    ((uint32_t)0x00008000) /* Fast Lock */
+#define FLASH_CTLR_PAGE_PG                      ((uint32_t)0x00010000) /* Page Programming 256Byte */
+#define FLASH_CTLR_PAGE_ER                      ((uint32_t)0x00020000) /* Page Erase 256Byte */
+#define FLASH_CTLR_PAGE_BER32                   ((uint32_t)0x00040000) /* Block Erase 32K */
+#define FLASH_CTLR_PAGE_BER64                   ((uint32_t)0x00080000) /* Block Erase 64K */
+#define FLASH_CTLR_PG_STRT                      ((uint32_t)0x00200000) /* Page Programming Start */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define FLASH_ADDR_FAR                          ((uint32_t)0xFFFFFFFF) /* Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define FLASH_OBR_OPTERR                        ((uint16_t)0x0001) /* Option Byte Error */
+#define FLASH_OBR_RDPRT                         ((uint16_t)0x0002) /* Read protection */
+
+#define FLASH_OBR_USER                          ((uint16_t)0x03FC) /* User Option Bytes */
+#define FLASH_OBR_WDG_SW                        ((uint16_t)0x0004) /* WDG_SW */
+#define FLASH_OBR_nRST_STOP                     ((uint16_t)0x0008) /* nRST_STOP */
+#define FLASH_OBR_nRST_STDBY                    ((uint16_t)0x0010) /* nRST_STDBY */
+#define FLASH_OBR_BFB2                          ((uint16_t)0x0020) /* BFB2 */
+
+/******************  Bit definition for FLASH_WPR register  ******************/
+#define FLASH_WPR_WRP                           ((uint32_t)0xFFFFFFFF) /* Write Protect */
+
+/******************  Bit definition for FLASH_RDPR register  *******************/
+#define FLASH_RDPR_RDPR                         ((uint32_t)0x000000FF) /* Read protection option byte */
+#define FLASH_RDPR_nRDPR                        ((uint32_t)0x0000FF00) /* Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define FLASH_USER_USER                         ((uint32_t)0x00FF0000) /* User option byte */
+#define FLASH_USER_nUSER                        ((uint32_t)0xFF000000) /* User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define FLASH_Data0_Data0                       ((uint32_t)0x000000FF) /* User data storage option byte */
+#define FLASH_Data0_nData0                      ((uint32_t)0x0000FF00) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define FLASH_Data1_Data1                       ((uint32_t)0x00FF0000) /* User data storage option byte */
+#define FLASH_Data1_nData1                      ((uint32_t)0xFF000000) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPR0 register  ******************/
+#define FLASH_WRPR0_WRPR0                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR0_nWRPR0                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR1 register  ******************/
+#define FLASH_WRPR1_WRPR1                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR1_nWRPR1                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR2 register  ******************/
+#define FLASH_WRPR2_WRPR2                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR2_nWRPR2                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR3 register  ******************/
+#define FLASH_WRPR3_WRPR3                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR3_nWRPR3                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                General Purpose and Alternate Function I/O                  */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CFGLR register  *******************/
+#define GPIO_CFGLR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGLR_MODE0                        ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CFGLR_MODE0_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGLR_MODE0_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE1                        ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CFGLR_MODE1_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGLR_MODE1_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE2                        ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CFGLR_MODE2_0                      ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGLR_MODE2_1                      ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE3                        ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CFGLR_MODE3_0                      ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGLR_MODE3_1                      ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE4                        ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CFGLR_MODE4_0                      ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGLR_MODE4_1                      ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE5                        ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CFGLR_MODE5_0                      ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGLR_MODE5_1                      ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE6                        ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CFGLR_MODE6_0                      ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE6_1                      ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE7                        ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CFGLR_MODE7_0                      ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE7_1                      ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGLR_CNF0                         ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CFGLR_CNF0_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGLR_CNF0_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF1                         ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CFGLR_CNF1_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGLR_CNF1_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF2                         ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CFGLR_CNF2_0                       ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGLR_CNF2_1                       ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF3                         ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CFGLR_CNF3_0                       ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGLR_CNF3_1                       ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF4                         ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CFGLR_CNF4_0                       ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGLR_CNF4_1                       ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF5                         ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CFGLR_CNF5_0                       ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGLR_CNF5_1                       ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF6                         ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CFGLR_CNF6_0                       ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF6_1                       ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF7                         ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CFGLR_CNF7_0                       ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF7_1                       ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_CFGHR register  *******************/
+#define GPIO_CFGHR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGHR_MODE8                        ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CFGHR_MODE8_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGHR_MODE8_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE9                        ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CFGHR_MODE9_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGHR_MODE9_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE10                       ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CFGHR_MODE10_0                     ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGHR_MODE10_1                     ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE11                       ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CFGHR_MODE11_0                     ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGHR_MODE11_1                     ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE12                       ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CFGHR_MODE12_0                     ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGHR_MODE12_1                     ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE13                       ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CFGHR_MODE13_0                     ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGHR_MODE13_1                     ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE14                       ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CFGHR_MODE14_0                     ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE14_1                     ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE15                       ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CFGHR_MODE15_0                     ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE15_1                     ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGHR_CNF8                         ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CFGHR_CNF8_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGHR_CNF8_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF9                         ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CFGHR_CNF9_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGHR_CNF9_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF10                        ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CFGHR_CNF10_0                      ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGHR_CNF10_1                      ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF11                        ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CFGHR_CNF11_0                      ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGHR_CNF11_1                      ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF12                        ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CFGHR_CNF12_0                      ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGHR_CNF12_1                      ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF13                        ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CFGHR_CNF13_0                      ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGHR_CNF13_1                      ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF14                        ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CFGHR_CNF14_0                      ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF14_1                      ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF15                        ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CFGHR_CNF15_0                      ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF15_1                      ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_INDR register  *******************/
+#define GPIO_INDR_IDR0                          ((uint16_t)0x0001) /* Port input data, bit 0 */
+#define GPIO_INDR_IDR1                          ((uint16_t)0x0002) /* Port input data, bit 1 */
+#define GPIO_INDR_IDR2                          ((uint16_t)0x0004) /* Port input data, bit 2 */
+#define GPIO_INDR_IDR3                          ((uint16_t)0x0008) /* Port input data, bit 3 */
+#define GPIO_INDR_IDR4                          ((uint16_t)0x0010) /* Port input data, bit 4 */
+#define GPIO_INDR_IDR5                          ((uint16_t)0x0020) /* Port input data, bit 5 */
+#define GPIO_INDR_IDR6                          ((uint16_t)0x0040) /* Port input data, bit 6 */
+#define GPIO_INDR_IDR7                          ((uint16_t)0x0080) /* Port input data, bit 7 */
+#define GPIO_INDR_IDR8                          ((uint16_t)0x0100) /* Port input data, bit 8 */
+#define GPIO_INDR_IDR9                          ((uint16_t)0x0200) /* Port input data, bit 9 */
+#define GPIO_INDR_IDR10                         ((uint16_t)0x0400) /* Port input data, bit 10 */
+#define GPIO_INDR_IDR11                         ((uint16_t)0x0800) /* Port input data, bit 11 */
+#define GPIO_INDR_IDR12                         ((uint16_t)0x1000) /* Port input data, bit 12 */
+#define GPIO_INDR_IDR13                         ((uint16_t)0x2000) /* Port input data, bit 13 */
+#define GPIO_INDR_IDR14                         ((uint16_t)0x4000) /* Port input data, bit 14 */
+#define GPIO_INDR_IDR15                         ((uint16_t)0x8000) /* Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OUTDR register  *******************/
+#define GPIO_OUTDR_ODR0                         ((uint16_t)0x0001) /* Port output data, bit 0 */
+#define GPIO_OUTDR_ODR1                         ((uint16_t)0x0002) /* Port output data, bit 1 */
+#define GPIO_OUTDR_ODR2                         ((uint16_t)0x0004) /* Port output data, bit 2 */
+#define GPIO_OUTDR_ODR3                         ((uint16_t)0x0008) /* Port output data, bit 3 */
+#define GPIO_OUTDR_ODR4                         ((uint16_t)0x0010) /* Port output data, bit 4 */
+#define GPIO_OUTDR_ODR5                         ((uint16_t)0x0020) /* Port output data, bit 5 */
+#define GPIO_OUTDR_ODR6                         ((uint16_t)0x0040) /* Port output data, bit 6 */
+#define GPIO_OUTDR_ODR7                         ((uint16_t)0x0080) /* Port output data, bit 7 */
+#define GPIO_OUTDR_ODR8                         ((uint16_t)0x0100) /* Port output data, bit 8 */
+#define GPIO_OUTDR_ODR9                         ((uint16_t)0x0200) /* Port output data, bit 9 */
+#define GPIO_OUTDR_ODR10                        ((uint16_t)0x0400) /* Port output data, bit 10 */
+#define GPIO_OUTDR_ODR11                        ((uint16_t)0x0800) /* Port output data, bit 11 */
+#define GPIO_OUTDR_ODR12                        ((uint16_t)0x1000) /* Port output data, bit 12 */
+#define GPIO_OUTDR_ODR13                        ((uint16_t)0x2000) /* Port output data, bit 13 */
+#define GPIO_OUTDR_ODR14                        ((uint16_t)0x4000) /* Port output data, bit 14 */
+#define GPIO_OUTDR_ODR15                        ((uint16_t)0x8000) /* Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSHR register  *******************/
+#define GPIO_BSHR_BS0                           ((uint32_t)0x00000001) /* Port x Set bit 0 */
+#define GPIO_BSHR_BS1                           ((uint32_t)0x00000002) /* Port x Set bit 1 */
+#define GPIO_BSHR_BS2                           ((uint32_t)0x00000004) /* Port x Set bit 2 */
+#define GPIO_BSHR_BS3                           ((uint32_t)0x00000008) /* Port x Set bit 3 */
+#define GPIO_BSHR_BS4                           ((uint32_t)0x00000010) /* Port x Set bit 4 */
+#define GPIO_BSHR_BS5                           ((uint32_t)0x00000020) /* Port x Set bit 5 */
+#define GPIO_BSHR_BS6                           ((uint32_t)0x00000040) /* Port x Set bit 6 */
+#define GPIO_BSHR_BS7                           ((uint32_t)0x00000080) /* Port x Set bit 7 */
+#define GPIO_BSHR_BS8                           ((uint32_t)0x00000100) /* Port x Set bit 8 */
+#define GPIO_BSHR_BS9                           ((uint32_t)0x00000200) /* Port x Set bit 9 */
+#define GPIO_BSHR_BS10                          ((uint32_t)0x00000400) /* Port x Set bit 10 */
+#define GPIO_BSHR_BS11                          ((uint32_t)0x00000800) /* Port x Set bit 11 */
+#define GPIO_BSHR_BS12                          ((uint32_t)0x00001000) /* Port x Set bit 12 */
+#define GPIO_BSHR_BS13                          ((uint32_t)0x00002000) /* Port x Set bit 13 */
+#define GPIO_BSHR_BS14                          ((uint32_t)0x00004000) /* Port x Set bit 14 */
+#define GPIO_BSHR_BS15                          ((uint32_t)0x00008000) /* Port x Set bit 15 */
+
+#define GPIO_BSHR_BR0                           ((uint32_t)0x00010000) /* Port x Reset bit 0 */
+#define GPIO_BSHR_BR1                           ((uint32_t)0x00020000) /* Port x Reset bit 1 */
+#define GPIO_BSHR_BR2                           ((uint32_t)0x00040000) /* Port x Reset bit 2 */
+#define GPIO_BSHR_BR3                           ((uint32_t)0x00080000) /* Port x Reset bit 3 */
+#define GPIO_BSHR_BR4                           ((uint32_t)0x00100000) /* Port x Reset bit 4 */
+#define GPIO_BSHR_BR5                           ((uint32_t)0x00200000) /* Port x Reset bit 5 */
+#define GPIO_BSHR_BR6                           ((uint32_t)0x00400000) /* Port x Reset bit 6 */
+#define GPIO_BSHR_BR7                           ((uint32_t)0x00800000) /* Port x Reset bit 7 */
+#define GPIO_BSHR_BR8                           ((uint32_t)0x01000000) /* Port x Reset bit 8 */
+#define GPIO_BSHR_BR9                           ((uint32_t)0x02000000) /* Port x Reset bit 9 */
+#define GPIO_BSHR_BR10                          ((uint32_t)0x04000000) /* Port x Reset bit 10 */
+#define GPIO_BSHR_BR11                          ((uint32_t)0x08000000) /* Port x Reset bit 11 */
+#define GPIO_BSHR_BR12                          ((uint32_t)0x10000000) /* Port x Reset bit 12 */
+#define GPIO_BSHR_BR13                          ((uint32_t)0x20000000) /* Port x Reset bit 13 */
+#define GPIO_BSHR_BR14                          ((uint32_t)0x40000000) /* Port x Reset bit 14 */
+#define GPIO_BSHR_BR15                          ((uint32_t)0x80000000) /* Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BCR register  *******************/
+#define GPIO_BCR_BR0                            ((uint16_t)0x0001) /* Port x Reset bit 0 */
+#define GPIO_BCR_BR1                            ((uint16_t)0x0002) /* Port x Reset bit 1 */
+#define GPIO_BCR_BR2                            ((uint16_t)0x0004) /* Port x Reset bit 2 */
+#define GPIO_BCR_BR3                            ((uint16_t)0x0008) /* Port x Reset bit 3 */
+#define GPIO_BCR_BR4                            ((uint16_t)0x0010) /* Port x Reset bit 4 */
+#define GPIO_BCR_BR5                            ((uint16_t)0x0020) /* Port x Reset bit 5 */
+#define GPIO_BCR_BR6                            ((uint16_t)0x0040) /* Port x Reset bit 6 */
+#define GPIO_BCR_BR7                            ((uint16_t)0x0080) /* Port x Reset bit 7 */
+#define GPIO_BCR_BR8                            ((uint16_t)0x0100) /* Port x Reset bit 8 */
+#define GPIO_BCR_BR9                            ((uint16_t)0x0200) /* Port x Reset bit 9 */
+#define GPIO_BCR_BR10                           ((uint16_t)0x0400) /* Port x Reset bit 10 */
+#define GPIO_BCR_BR11                           ((uint16_t)0x0800) /* Port x Reset bit 11 */
+#define GPIO_BCR_BR12                           ((uint16_t)0x1000) /* Port x Reset bit 12 */
+#define GPIO_BCR_BR13                           ((uint16_t)0x2000) /* Port x Reset bit 13 */
+#define GPIO_BCR_BR14                           ((uint16_t)0x4000) /* Port x Reset bit 14 */
+#define GPIO_BCR_BR15                           ((uint16_t)0x8000) /* Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCK0                               ((uint32_t)0x00000001) /* Port x Lock bit 0 */
+#define GPIO_LCK1                               ((uint32_t)0x00000002) /* Port x Lock bit 1 */
+#define GPIO_LCK2                               ((uint32_t)0x00000004) /* Port x Lock bit 2 */
+#define GPIO_LCK3                               ((uint32_t)0x00000008) /* Port x Lock bit 3 */
+#define GPIO_LCK4                               ((uint32_t)0x00000010) /* Port x Lock bit 4 */
+#define GPIO_LCK5                               ((uint32_t)0x00000020) /* Port x Lock bit 5 */
+#define GPIO_LCK6                               ((uint32_t)0x00000040) /* Port x Lock bit 6 */
+#define GPIO_LCK7                               ((uint32_t)0x00000080) /* Port x Lock bit 7 */
+#define GPIO_LCK8                               ((uint32_t)0x00000100) /* Port x Lock bit 8 */
+#define GPIO_LCK9                               ((uint32_t)0x00000200) /* Port x Lock bit 9 */
+#define GPIO_LCK10                              ((uint32_t)0x00000400) /* Port x Lock bit 10 */
+#define GPIO_LCK11                              ((uint32_t)0x00000800) /* Port x Lock bit 11 */
+#define GPIO_LCK12                              ((uint32_t)0x00001000) /* Port x Lock bit 12 */
+#define GPIO_LCK13                              ((uint32_t)0x00002000) /* Port x Lock bit 13 */
+#define GPIO_LCK14                              ((uint32_t)0x00004000) /* Port x Lock bit 14 */
+#define GPIO_LCK15                              ((uint32_t)0x00008000) /* Port x Lock bit 15 */
+#define GPIO_LCKK                               ((uint32_t)0x00010000) /* Lock key */
+
+/******************  Bit definition for AFIO_ECR register  *******************/
+#define AFIO_ECR_PIN                            ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */
+#define AFIO_ECR_PIN_0                          ((uint8_t)0x01) /* Bit 0 */
+#define AFIO_ECR_PIN_1                          ((uint8_t)0x02) /* Bit 1 */
+#define AFIO_ECR_PIN_2                          ((uint8_t)0x04) /* Bit 2 */
+#define AFIO_ECR_PIN_3                          ((uint8_t)0x08) /* Bit 3 */
+
+#define AFIO_ECR_PIN_PX0                        ((uint8_t)0x00) /* Pin 0 selected */
+#define AFIO_ECR_PIN_PX1                        ((uint8_t)0x01) /* Pin 1 selected */
+#define AFIO_ECR_PIN_PX2                        ((uint8_t)0x02) /* Pin 2 selected */
+#define AFIO_ECR_PIN_PX3                        ((uint8_t)0x03) /* Pin 3 selected */
+#define AFIO_ECR_PIN_PX4                        ((uint8_t)0x04) /* Pin 4 selected */
+#define AFIO_ECR_PIN_PX5                        ((uint8_t)0x05) /* Pin 5 selected */
+#define AFIO_ECR_PIN_PX6                        ((uint8_t)0x06) /* Pin 6 selected */
+#define AFIO_ECR_PIN_PX7                        ((uint8_t)0x07) /* Pin 7 selected */
+#define AFIO_ECR_PIN_PX8                        ((uint8_t)0x08) /* Pin 8 selected */
+#define AFIO_ECR_PIN_PX9                        ((uint8_t)0x09) /* Pin 9 selected */
+#define AFIO_ECR_PIN_PX10                       ((uint8_t)0x0A) /* Pin 10 selected */
+#define AFIO_ECR_PIN_PX11                       ((uint8_t)0x0B) /* Pin 11 selected */
+#define AFIO_ECR_PIN_PX12                       ((uint8_t)0x0C) /* Pin 12 selected */
+#define AFIO_ECR_PIN_PX13                       ((uint8_t)0x0D) /* Pin 13 selected */
+#define AFIO_ECR_PIN_PX14                       ((uint8_t)0x0E) /* Pin 14 selected */
+#define AFIO_ECR_PIN_PX15                       ((uint8_t)0x0F) /* Pin 15 selected */
+
+#define AFIO_ECR_PORT                           ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */
+#define AFIO_ECR_PORT_0                         ((uint8_t)0x10) /* Bit 0 */
+#define AFIO_ECR_PORT_1                         ((uint8_t)0x20) /* Bit 1 */
+#define AFIO_ECR_PORT_2                         ((uint8_t)0x40) /* Bit 2 */
+
+#define AFIO_ECR_PORT_PA                        ((uint8_t)0x00) /* Port A selected */
+#define AFIO_ECR_PORT_PB                        ((uint8_t)0x10) /* Port B selected */
+#define AFIO_ECR_PORT_PC                        ((uint8_t)0x20) /* Port C selected */
+#define AFIO_ECR_PORT_PD                        ((uint8_t)0x30) /* Port D selected */
+#define AFIO_ECR_PORT_PE                        ((uint8_t)0x40) /* Port E selected */
+
+#define AFIO_ECR_EVOE                           ((uint8_t)0x80) /* Event Output Enable */
+
+/******************  Bit definition for AFIO_PCFR1register  *******************/
+#define AFIO_PCFR1_SPI1_REMAP                   ((uint32_t)0x00000001) /* SPI1 remapping */
+#define AFIO_PCFR1_I2C1_REMAP                   ((uint32_t)0x00000002) /* I2C1 remapping */
+#define AFIO_PCFR1_USART1_REMAP                 ((uint32_t)0x00000004) /* USART1 remapping */
+#define AFIO_PCFR1_USART2_REMAP                 ((uint32_t)0x00000008) /* USART2 remapping */
+
+#define AFIO_PCFR1_USART3_REMAP                 ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_PCFR1_USART3_REMAP_0               ((uint32_t)0x00000010) /* Bit 0 */
+#define AFIO_PCFR1_USART3_REMAP_1               ((uint32_t)0x00000020) /* Bit 1 */
+
+#define AFIO_PCFR1_USART3_REMAP_NOREMAP         ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP    ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_FULLREMAP       ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_PCFR1_TIM1_REMAP                   ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_PCFR1_TIM1_REMAP_0                 ((uint32_t)0x00000040) /* Bit 0 */
+#define AFIO_PCFR1_TIM1_REMAP_1                 ((uint32_t)0x00000080) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM1_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP      ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP         ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_PCFR1_TIM2_REMAP                   ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_PCFR1_TIM2_REMAP_0                 ((uint32_t)0x00000100) /* Bit 0 */
+#define AFIO_PCFR1_TIM2_REMAP_1                 ((uint32_t)0x00000200) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM2_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1     ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2     ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP         ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_PCFR1_TIM3_REMAP                   ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_PCFR1_TIM3_REMAP_0                 ((uint32_t)0x00000400) /* Bit 0 */
+#define AFIO_PCFR1_TIM3_REMAP_1                 ((uint32_t)0x00000800) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM3_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP      ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP         ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_PCFR1_TIM4_REMAP                   ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_PCFR1_CAN_REMAP                    ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_PCFR1_CAN_REMAP_0                  ((uint32_t)0x00002000) /* Bit 0 */
+#define AFIO_PCFR1_CAN_REMAP_1                  ((uint32_t)0x00004000) /* Bit 1 */
+
+#define AFIO_PCFR1_CAN_REMAP_REMAP1             ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP2             ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP3             ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_PCFR1_PD01_REMAP                   ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCFR1_TIM5CH4_IREMAP               ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
+#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP           ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC1_ETRGREG_REMAP           ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP           ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGREG_REMAP           ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
+
+#define AFIO_PCFR1_SWJ_CFG                      ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_PCFR1_SWJ_CFG_0                    ((uint32_t)0x01000000) /* Bit 0 */
+#define AFIO_PCFR1_SWJ_CFG_1                    ((uint32_t)0x02000000) /* Bit 1 */
+#define AFIO_PCFR1_SWJ_CFG_2                    ((uint32_t)0x04000000) /* Bit 2 */
+
+#define AFIO_PCFR1_SWJ_CFG_RESET                ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_PCFR1_SWJ_CFG_NOJNTRST             ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE          ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_PCFR1_SWJ_CFG_DISABLE              ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                      ((uint16_t)0x000F) /* EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                      ((uint16_t)0x00F0) /* EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                      ((uint16_t)0x0F00) /* EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                      ((uint16_t)0xF000) /* EXTI 3 configuration */
+
+#define AFIO_EXTICR1_EXTI0_PA                   ((uint16_t)0x0000) /* PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                   ((uint16_t)0x0001) /* PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                   ((uint16_t)0x0002) /* PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                   ((uint16_t)0x0003) /* PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                   ((uint16_t)0x0004) /* PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                   ((uint16_t)0x0005) /* PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                   ((uint16_t)0x0006) /* PG[0] pin */
+
+#define AFIO_EXTICR1_EXTI1_PA                   ((uint16_t)0x0000) /* PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                   ((uint16_t)0x0010) /* PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                   ((uint16_t)0x0020) /* PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                   ((uint16_t)0x0030) /* PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                   ((uint16_t)0x0040) /* PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                   ((uint16_t)0x0050) /* PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                   ((uint16_t)0x0060) /* PG[1] pin */
+
+#define AFIO_EXTICR1_EXTI2_PA                   ((uint16_t)0x0000) /* PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                   ((uint16_t)0x0100) /* PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                   ((uint16_t)0x0200) /* PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                   ((uint16_t)0x0300) /* PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                   ((uint16_t)0x0400) /* PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                   ((uint16_t)0x0500) /* PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                   ((uint16_t)0x0600) /* PG[2] pin */
+
+#define AFIO_EXTICR1_EXTI3_PA                   ((uint16_t)0x0000) /* PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                   ((uint16_t)0x1000) /* PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                   ((uint16_t)0x2000) /* PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                   ((uint16_t)0x3000) /* PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                   ((uint16_t)0x4000) /* PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                   ((uint16_t)0x5000) /* PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                   ((uint16_t)0x6000) /* PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                      ((uint16_t)0x000F) /* EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                      ((uint16_t)0x00F0) /* EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                      ((uint16_t)0x0F00) /* EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                      ((uint16_t)0xF000) /* EXTI 7 configuration */
+
+#define AFIO_EXTICR2_EXTI4_PA                   ((uint16_t)0x0000) /* PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                   ((uint16_t)0x0001) /* PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                   ((uint16_t)0x0002) /* PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                   ((uint16_t)0x0003) /* PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                   ((uint16_t)0x0004) /* PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                   ((uint16_t)0x0005) /* PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                   ((uint16_t)0x0006) /* PG[4] pin */
+
+#define AFIO_EXTICR2_EXTI5_PA                   ((uint16_t)0x0000) /* PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                   ((uint16_t)0x0010) /* PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                   ((uint16_t)0x0020) /* PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                   ((uint16_t)0x0030) /* PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                   ((uint16_t)0x0040) /* PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                   ((uint16_t)0x0050) /* PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                   ((uint16_t)0x0060) /* PG[5] pin */
+
+#define AFIO_EXTICR2_EXTI6_PA                   ((uint16_t)0x0000) /* PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                   ((uint16_t)0x0100) /* PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                   ((uint16_t)0x0200) /* PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                   ((uint16_t)0x0300) /* PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                   ((uint16_t)0x0400) /* PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                   ((uint16_t)0x0500) /* PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                   ((uint16_t)0x0600) /* PG[6] pin */
+
+#define AFIO_EXTICR2_EXTI7_PA                   ((uint16_t)0x0000) /* PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                   ((uint16_t)0x1000) /* PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                   ((uint16_t)0x2000) /* PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                   ((uint16_t)0x3000) /* PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                   ((uint16_t)0x4000) /* PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                   ((uint16_t)0x5000) /* PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                   ((uint16_t)0x6000) /* PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                      ((uint16_t)0x000F) /* EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                      ((uint16_t)0x00F0) /* EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                     ((uint16_t)0x0F00) /* EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                     ((uint16_t)0xF000) /* EXTI 11 configuration */
+
+#define AFIO_EXTICR3_EXTI8_PA                   ((uint16_t)0x0000) /* PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                   ((uint16_t)0x0001) /* PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                   ((uint16_t)0x0002) /* PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                   ((uint16_t)0x0003) /* PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                   ((uint16_t)0x0004) /* PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                   ((uint16_t)0x0005) /* PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                   ((uint16_t)0x0006) /* PG[8] pin */
+
+#define AFIO_EXTICR3_EXTI9_PA                   ((uint16_t)0x0000) /* PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                   ((uint16_t)0x0010) /* PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                   ((uint16_t)0x0020) /* PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                   ((uint16_t)0x0030) /* PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                   ((uint16_t)0x0040) /* PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                   ((uint16_t)0x0050) /* PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                   ((uint16_t)0x0060) /* PG[9] pin */
+
+#define AFIO_EXTICR3_EXTI10_PA                  ((uint16_t)0x0000) /* PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB                  ((uint16_t)0x0100) /* PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC                  ((uint16_t)0x0200) /* PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD                  ((uint16_t)0x0300) /* PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE                  ((uint16_t)0x0400) /* PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF                  ((uint16_t)0x0500) /* PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG                  ((uint16_t)0x0600) /* PG[10] pin */
+
+#define AFIO_EXTICR3_EXTI11_PA                  ((uint16_t)0x0000) /* PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB                  ((uint16_t)0x1000) /* PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC                  ((uint16_t)0x2000) /* PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD                  ((uint16_t)0x3000) /* PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE                  ((uint16_t)0x4000) /* PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF                  ((uint16_t)0x5000) /* PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG                  ((uint16_t)0x6000) /* PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                     ((uint16_t)0x000F) /* EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                     ((uint16_t)0x00F0) /* EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                     ((uint16_t)0x0F00) /* EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                     ((uint16_t)0xF000) /* EXTI 15 configuration */
+
+#define AFIO_EXTICR4_EXTI12_PA                  ((uint16_t)0x0000) /* PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB                  ((uint16_t)0x0001) /* PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC                  ((uint16_t)0x0002) /* PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD                  ((uint16_t)0x0003) /* PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE                  ((uint16_t)0x0004) /* PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF                  ((uint16_t)0x0005) /* PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG                  ((uint16_t)0x0006) /* PG[12] pin */
+
+#define AFIO_EXTICR4_EXTI13_PA                  ((uint16_t)0x0000) /* PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB                  ((uint16_t)0x0010) /* PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC                  ((uint16_t)0x0020) /* PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD                  ((uint16_t)0x0030) /* PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE                  ((uint16_t)0x0040) /* PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF                  ((uint16_t)0x0050) /* PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG                  ((uint16_t)0x0060) /* PG[13] pin */
+
+#define AFIO_EXTICR4_EXTI14_PA                  ((uint16_t)0x0000) /* PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB                  ((uint16_t)0x0100) /* PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC                  ((uint16_t)0x0200) /* PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD                  ((uint16_t)0x0300) /* PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE                  ((uint16_t)0x0400) /* PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF                  ((uint16_t)0x0500) /* PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG                  ((uint16_t)0x0600) /* PG[14] pin */
+
+#define AFIO_EXTICR4_EXTI15_PA                  ((uint16_t)0x0000) /* PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB                  ((uint16_t)0x1000) /* PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC                  ((uint16_t)0x2000) /* PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD                  ((uint16_t)0x3000) /* PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE                  ((uint16_t)0x4000) /* PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF                  ((uint16_t)0x5000) /* PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG                  ((uint16_t)0x6000) /* PG[15] pin */
+
+/******************************************************************************/
+/*                           Independent WATCHDOG                             */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_CTLR register  ********************/
+#define IWDG_KEY                                ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSCR register  ********************/
+#define IWDG_PR                                 ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */
+#define IWDG_PR_0                               ((uint8_t)0x01) /* Bit 0 */
+#define IWDG_PR_1                               ((uint8_t)0x02) /* Bit 1 */
+#define IWDG_PR_2                               ((uint8_t)0x04) /* Bit 2 */
+
+/*******************  Bit definition for IWDG_RLDR register  *******************/
+#define IWDG_RL                                 ((uint16_t)0x0FFF) /* Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STATR register  ********************/
+#define IWDG_PVU                                ((uint8_t)0x01) /* Watchdog prescaler value update */
+#define IWDG_RVU                                ((uint8_t)0x02) /* Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                      Inter-integrated Circuit Interface                    */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTLR1 register  ********************/
+#define I2C_CTLR1_PE                            ((uint16_t)0x0001) /* Peripheral Enable */
+#define I2C_CTLR1_SMBUS                         ((uint16_t)0x0002) /* SMBus Mode */
+#define I2C_CTLR1_SMBTYPE                       ((uint16_t)0x0008) /* SMBus Type */
+#define I2C_CTLR1_ENARP                         ((uint16_t)0x0010) /* ARP Enable */
+#define I2C_CTLR1_ENPEC                         ((uint16_t)0x0020) /* PEC Enable */
+#define I2C_CTLR1_ENGC                          ((uint16_t)0x0040) /* General Call Enable */
+#define I2C_CTLR1_NOSTRETCH                     ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
+#define I2C_CTLR1_START                         ((uint16_t)0x0100) /* Start Generation */
+#define I2C_CTLR1_STOP                          ((uint16_t)0x0200) /* Stop Generation */
+#define I2C_CTLR1_ACK                           ((uint16_t)0x0400) /* Acknowledge Enable */
+#define I2C_CTLR1_POS                           ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
+#define I2C_CTLR1_PEC                           ((uint16_t)0x1000) /* Packet Error Checking */
+#define I2C_CTLR1_ALERT                         ((uint16_t)0x2000) /* SMBus Alert */
+#define I2C_CTLR1_SWRST                         ((uint16_t)0x8000) /* Software Reset */
+
+/*******************  Bit definition for I2C_CTLR2 register  ********************/
+#define I2C_CTLR2_FREQ                          ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTLR2_FREQ_0                        ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_CTLR2_FREQ_1                        ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_CTLR2_FREQ_2                        ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_CTLR2_FREQ_3                        ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_CTLR2_FREQ_4                        ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_CTLR2_FREQ_5                        ((uint16_t)0x0020) /* Bit 5 */
+
+#define I2C_CTLR2_ITERREN                       ((uint16_t)0x0100) /* Error Interrupt Enable */
+#define I2C_CTLR2_ITEVTEN                       ((uint16_t)0x0200) /* Event Interrupt Enable */
+#define I2C_CTLR2_ITBUFEN                       ((uint16_t)0x0400) /* Buffer Interrupt Enable */
+#define I2C_CTLR2_DMAEN                         ((uint16_t)0x0800) /* DMA Requests Enable */
+#define I2C_CTLR2_LAST                          ((uint16_t)0x1000) /* DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define I2C_OADDR1_ADD1_7                       ((uint16_t)0x00FE) /* Interface Address */
+#define I2C_OADDR1_ADD8_9                       ((uint16_t)0x0300) /* Interface Address */
+
+#define I2C_OADDR1_ADD0                         ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_OADDR1_ADD1                         ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_OADDR1_ADD2                         ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_OADDR1_ADD3                         ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_OADDR1_ADD4                         ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_OADDR1_ADD5                         ((uint16_t)0x0020) /* Bit 5 */
+#define I2C_OADDR1_ADD6                         ((uint16_t)0x0040) /* Bit 6 */
+#define I2C_OADDR1_ADD7                         ((uint16_t)0x0080) /* Bit 7 */
+#define I2C_OADDR1_ADD8                         ((uint16_t)0x0100) /* Bit 8 */
+#define I2C_OADDR1_ADD9                         ((uint16_t)0x0200) /* Bit 9 */
+
+#define I2C_OADDR1_ADDMODE                      ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define I2C_OADDR2_ENDUAL                       ((uint8_t)0x01) /* Dual addressing mode enable */
+#define I2C_OADDR2_ADD2                         ((uint8_t)0xFE) /* Interface address */
+
+/********************  Bit definition for I2C_DATAR register  ********************/
+#define I2C_DR_DATAR                            ((uint8_t)0xFF) /* 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STAR1 register  ********************/
+#define I2C_STAR1_SB                            ((uint16_t)0x0001) /* Start Bit (Master mode) */
+#define I2C_STAR1_ADDR                          ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */
+#define I2C_STAR1_BTF                           ((uint16_t)0x0004) /* Byte Transfer Finished */
+#define I2C_STAR1_ADD10                         ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */
+#define I2C_STAR1_STOPF                         ((uint16_t)0x0010) /* Stop detection (Slave mode) */
+#define I2C_STAR1_RXNE                          ((uint16_t)0x0040) /* Data Register not Empty (receivers) */
+#define I2C_STAR1_TXE                           ((uint16_t)0x0080) /* Data Register Empty (transmitters) */
+#define I2C_STAR1_BERR                          ((uint16_t)0x0100) /* Bus Error */
+#define I2C_STAR1_ARLO                          ((uint16_t)0x0200) /* Arbitration Lost (master mode) */
+#define I2C_STAR1_AF                            ((uint16_t)0x0400) /* Acknowledge Failure */
+#define I2C_STAR1_OVR                           ((uint16_t)0x0800) /* Overrun/Underrun */
+#define I2C_STAR1_PECERR                        ((uint16_t)0x1000) /* PEC Error in reception */
+#define I2C_STAR1_TIMEOUT                       ((uint16_t)0x4000) /* Timeout or Tlow Error */
+#define I2C_STAR1_SMBALERT                      ((uint16_t)0x8000) /* SMBus Alert */
+
+/*******************  Bit definition for I2C_STAR2 register  ********************/
+#define I2C_STAR2_MSL                           ((uint16_t)0x0001) /* Master/Slave */
+#define I2C_STAR2_BUSY                          ((uint16_t)0x0002) /* Bus Busy */
+#define I2C_STAR2_TRA                           ((uint16_t)0x0004) /* Transmitter/Receiver */
+#define I2C_STAR2_GENCALL                       ((uint16_t)0x0010) /* General Call Address (Slave mode) */
+#define I2C_STAR2_SMBDEFAULT                    ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
+#define I2C_STAR2_SMBHOST                       ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
+#define I2C_STAR2_DUALF                         ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
+#define I2C_STAR2_PEC                           ((uint16_t)0xFF00) /* Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CKCFGR register  ********************/
+#define I2C_CKCFGR_CCR                          ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CKCFGR_DUTY                         ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
+#define I2C_CKCFGR_FS                           ((uint16_t)0x8000) /* I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_RTR register  *******************/
+#define I2C_RTR_TRISE                           ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                             Power Control                                  */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTLR register  ********************/
+#define PWR_CTLR_LPDS                           ((uint16_t)0x0001) /* Low-Power Deepsleep */
+#define PWR_CTLR_PDDS                           ((uint16_t)0x0002) /* Power Down Deepsleep */
+#define PWR_CTLR_CWUF                           ((uint16_t)0x0004) /* Clear Wakeup Flag */
+#define PWR_CTLR_CSBF                           ((uint16_t)0x0008) /* Clear Standby Flag */
+#define PWR_CTLR_PVDE                           ((uint16_t)0x0010) /* Power Voltage Detector Enable */
+
+#define PWR_CTLR_PLS                            ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CTLR_PLS_0                          ((uint16_t)0x0020) /* Bit 0 */
+#define PWR_CTLR_PLS_1                          ((uint16_t)0x0040) /* Bit 1 */
+#define PWR_CTLR_PLS_2                          ((uint16_t)0x0080) /* Bit 2 */
+
+#define PWR_CTLR_PLS_2V2                        ((uint16_t)0x0000) /* PVD level 2.2V */
+#define PWR_CTLR_PLS_2V3                        ((uint16_t)0x0020) /* PVD level 2.3V */
+#define PWR_CTLR_PLS_2V4                        ((uint16_t)0x0040) /* PVD level 2.4V */
+#define PWR_CTLR_PLS_2V5                        ((uint16_t)0x0060) /* PVD level 2.5V */
+#define PWR_CTLR_PLS_2V6                        ((uint16_t)0x0080) /* PVD level 2.6V */
+#define PWR_CTLR_PLS_2V7                        ((uint16_t)0x00A0) /* PVD level 2.7V */
+#define PWR_CTLR_PLS_2V8                        ((uint16_t)0x00C0) /* PVD level 2.8V */
+#define PWR_CTLR_PLS_2V9                        ((uint16_t)0x00E0) /* PVD level 2.9V */
+
+#define PWR_CTLR_DBP                            ((uint16_t)0x0100) /* Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF                             ((uint16_t)0x0001) /* Wakeup Flag */
+#define PWR_CSR_SBF                             ((uint16_t)0x0002) /* Standby Flag */
+#define PWR_CSR_PVDO                            ((uint16_t)0x0004) /* PVD Output */
+#define PWR_CSR_EWUP                            ((uint16_t)0x0100) /* Enable WKUP pin */
+
+/******************************************************************************/
+/*                         Reset and Clock Control                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTLR register  ********************/
+#define RCC_HSION                               ((uint32_t)0x00000001) /* Internal High Speed clock enable */
+#define RCC_HSIRDY                              ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */
+#define RCC_HSITRIM                             ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */
+#define RCC_HSICAL                              ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */
+#define RCC_HSEON                               ((uint32_t)0x00010000) /* External High Speed clock enable */
+#define RCC_HSERDY                              ((uint32_t)0x00020000) /* External High Speed clock ready flag */
+#define RCC_HSEBYP                              ((uint32_t)0x00040000) /* External High Speed clock Bypass */
+#define RCC_CSSON                               ((uint32_t)0x00080000) /* Clock Security System enable */
+#define RCC_PLLON                               ((uint32_t)0x01000000) /* PLL enable */
+#define RCC_PLLRDY                              ((uint32_t)0x02000000) /* PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR0 register  *******************/
+#define RCC_SW                                  ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
+#define RCC_SW_0                                ((uint32_t)0x00000001) /* Bit 0 */
+#define RCC_SW_1                                ((uint32_t)0x00000002) /* Bit 1 */
+
+#define RCC_SW_HSI                              ((uint32_t)0x00000000) /* HSI selected as system clock */
+#define RCC_SW_HSE                              ((uint32_t)0x00000001) /* HSE selected as system clock */
+#define RCC_SW_PLL                              ((uint32_t)0x00000002) /* PLL selected as system clock */
+
+#define RCC_SWS                                 ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_SWS_0                               ((uint32_t)0x00000004) /* Bit 0 */
+#define RCC_SWS_1                               ((uint32_t)0x00000008) /* Bit 1 */
+
+#define RCC_SWS_HSI                             ((uint32_t)0x00000000) /* HSI oscillator used as system clock */
+#define RCC_SWS_HSE                             ((uint32_t)0x00000004) /* HSE oscillator used as system clock */
+#define RCC_SWS_PLL                             ((uint32_t)0x00000008) /* PLL used as system clock */
+
+#define RCC_HPRE                                ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
+#define RCC_HPRE_0                              ((uint32_t)0x00000010) /* Bit 0 */
+#define RCC_HPRE_1                              ((uint32_t)0x00000020) /* Bit 1 */
+#define RCC_HPRE_2                              ((uint32_t)0x00000040) /* Bit 2 */
+#define RCC_HPRE_3                              ((uint32_t)0x00000080) /* Bit 3 */
+
+#define RCC_HPRE_DIV1                           ((uint32_t)0x00000000) /* SYSCLK not divided */
+#define RCC_HPRE_DIV2                           ((uint32_t)0x00000080) /* SYSCLK divided by 2 */
+#define RCC_HPRE_DIV4                           ((uint32_t)0x00000090) /* SYSCLK divided by 4 */
+#define RCC_HPRE_DIV8                           ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */
+#define RCC_HPRE_DIV16                          ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */
+#define RCC_HPRE_DIV64                          ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */
+#define RCC_HPRE_DIV128                         ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */
+#define RCC_HPRE_DIV256                         ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */
+#define RCC_HPRE_DIV512                         ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */
+
+#define RCC_PPRE1                               ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_PPRE1_0                             ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_PPRE1_1                             ((uint32_t)0x00000200) /* Bit 1 */
+#define RCC_PPRE1_2                             ((uint32_t)0x00000400) /* Bit 2 */
+
+#define RCC_PPRE1_DIV1                          ((uint32_t)0x00000000) /* PPRE1 not divided */
+#define RCC_PPRE1_DIV2                          ((uint32_t)0x00000400) /* PPRE1 divided by 2 */
+#define RCC_PPRE1_DIV4                          ((uint32_t)0x00000500) /* PPRE1 divided by 4 */
+#define RCC_PPRE1_DIV8                          ((uint32_t)0x00000600) /* PPRE1 divided by 8 */
+#define RCC_PPRE1_DIV16                         ((uint32_t)0x00000700) /* PPRE1 divided by 16 */
+
+#define RCC_PPRE2                               ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_PPRE2_0                             ((uint32_t)0x00000800) /* Bit 0 */
+#define RCC_PPRE2_1                             ((uint32_t)0x00001000) /* Bit 1 */
+#define RCC_PPRE2_2                             ((uint32_t)0x00002000) /* Bit 2 */
+
+#define RCC_PPRE2_DIV1                          ((uint32_t)0x00000000) /* PPRE2 not divided */
+#define RCC_PPRE2_DIV2                          ((uint32_t)0x00002000) /* PPRE2 divided by 2 */
+#define RCC_PPRE2_DIV4                          ((uint32_t)0x00002800) /* PPRE2 divided by 4 */
+#define RCC_PPRE2_DIV8                          ((uint32_t)0x00003000) /* PPRE2 divided by 8 */
+#define RCC_PPRE2_DIV16                         ((uint32_t)0x00003800) /* PPRE2 divided by 16 */
+
+#define RCC_ADCPRE                              ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_ADCPRE_0                            ((uint32_t)0x00004000) /* Bit 0 */
+#define RCC_ADCPRE_1                            ((uint32_t)0x00008000) /* Bit 1 */
+
+#define RCC_ADCPRE_DIV2                         ((uint32_t)0x00000000) /* ADCPRE divided by 2 */
+#define RCC_ADCPRE_DIV4                         ((uint32_t)0x00004000) /* ADCPRE divided by 4 */
+#define RCC_ADCPRE_DIV6                         ((uint32_t)0x00008000) /* ADCPRE divided by 6 */
+#define RCC_ADCPRE_DIV8                         ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */
+
+#define RCC_PLLSRC                              ((uint32_t)0x00010000) /* PLL entry clock source */
+
+#define RCC_PLLXTPRE                            ((uint32_t)0x00020000) /* HSE divider for PLL entry */
+
+#define RCC_PLLMULL                             ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_PLLMULL_0                           ((uint32_t)0x00040000) /* Bit 0 */
+#define RCC_PLLMULL_1                           ((uint32_t)0x00080000) /* Bit 1 */
+#define RCC_PLLMULL_2                           ((uint32_t)0x00100000) /* Bit 2 */
+#define RCC_PLLMULL_3                           ((uint32_t)0x00200000) /* Bit 3 */
+
+#define RCC_PLLSRC_HSI_Div2                     ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSRC_HSE                          ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */
+
+#define RCC_PLLXTPRE_HSE                        ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
+#define RCC_PLLXTPRE_HSE_Div2                   ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
+
+/* for other CH32V20x */
+#define RCC_PLLMULL2                            ((uint32_t)0x00000000) /* PLL input clock*2 */
+#define RCC_PLLMULL3                            ((uint32_t)0x00040000) /* PLL input clock*3 */
+#define RCC_PLLMULL4                            ((uint32_t)0x00080000) /* PLL input clock*4 */
+#define RCC_PLLMULL5                            ((uint32_t)0x000C0000) /* PLL input clock*5 */
+#define RCC_PLLMULL6                            ((uint32_t)0x00100000) /* PLL input clock*6 */
+#define RCC_PLLMULL7                            ((uint32_t)0x00140000) /* PLL input clock*7 */
+#define RCC_PLLMULL8                            ((uint32_t)0x00180000) /* PLL input clock*8 */
+#define RCC_PLLMULL9                            ((uint32_t)0x001C0000) /* PLL input clock*9 */
+#define RCC_PLLMULL10                           ((uint32_t)0x00200000) /* PLL input clock10 */
+#define RCC_PLLMULL11                           ((uint32_t)0x00240000) /* PLL input clock*11 */
+#define RCC_PLLMULL12                           ((uint32_t)0x00280000) /* PLL input clock*12 */
+#define RCC_PLLMULL13                           ((uint32_t)0x002C0000) /* PLL input clock*13 */
+#define RCC_PLLMULL14                           ((uint32_t)0x00300000) /* PLL input clock*14 */
+#define RCC_PLLMULL15                           ((uint32_t)0x00340000) /* PLL input clock*15 */
+#define RCC_PLLMULL16                           ((uint32_t)0x00380000) /* PLL input clock*16 */
+#define RCC_PLLMULL18                           ((uint32_t)0x003C0000) /* PLL input clock*18 */
+
+#define RCC_USBPRE                              ((uint32_t)0x00400000) /* USB Device prescaler */
+
+#define RCC_CFGR0_MCO                           ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_MCO_0                               ((uint32_t)0x01000000) /* Bit 0 */
+#define RCC_MCO_1                               ((uint32_t)0x02000000) /* Bit 1 */
+#define RCC_MCO_2                               ((uint32_t)0x04000000) /* Bit 2 */
+
+#define RCC_MCO_NOCLOCK                         ((uint32_t)0x00000000) /* No clock */
+#define RCC_CFGR0_MCO_SYSCLK                    ((uint32_t)0x04000000) /* System clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSI                       ((uint32_t)0x05000000) /* HSI clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSE                       ((uint32_t)0x06000000) /* HSE clock selected as MCO source  */
+#define RCC_CFGR0_MCO_PLL                       ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */
+
+/*******************  Bit definition for RCC_INTR register  ********************/
+#define RCC_LSIRDYF                             ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
+#define RCC_LSERDYF                             ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
+#define RCC_HSIRDYF                             ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
+#define RCC_HSERDYF                             ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
+#define RCC_PLLRDYF                             ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
+#define RCC_CSSF                                ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
+#define RCC_LSIRDYIE                            ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
+#define RCC_LSERDYIE                            ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
+#define RCC_HSIRDYIE                            ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
+#define RCC_HSERDYIE                            ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
+#define RCC_PLLRDYIE                            ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
+#define RCC_LSIRDYC                             ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
+#define RCC_LSERDYC                             ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
+#define RCC_HSIRDYC                             ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
+#define RCC_HSERDYC                             ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
+#define RCC_PLLRDYC                             ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
+#define RCC_CSSC                                ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2PRSTR register  *****************/
+#define RCC_AFIORST                             ((uint32_t)0x00000001) /* Alternate Function I/O reset */
+#define RCC_IOPARST                             ((uint32_t)0x00000004) /* I/O port A reset */
+#define RCC_IOPBRST                             ((uint32_t)0x00000008) /* I/O port B reset */
+#define RCC_IOPCRST                             ((uint32_t)0x00000010) /* I/O port C reset */
+#define RCC_IOPDRST                             ((uint32_t)0x00000020) /* I/O port D reset */
+#define RCC_ADC1RST                             ((uint32_t)0x00000200) /* ADC 1 interface reset */
+
+#define RCC_ADC2RST                             ((uint32_t)0x00000400) /* ADC 2 interface reset */
+
+#define RCC_TIM1RST                             ((uint32_t)0x00000800) /* TIM1 Timer reset */
+#define RCC_SPI1RST                             ((uint32_t)0x00001000) /* SPI 1 reset */
+#define RCC_USART1RST                           ((uint32_t)0x00004000) /* USART1 reset */
+
+#define RCC_IOPERST                             ((uint32_t)0x00000040) /* I/O port E reset */
+
+/*****************  Bit definition for RCC_APB1PRSTR register  *****************/
+#define RCC_TIM2RST                             ((uint32_t)0x00000001) /* Timer 2 reset */
+#define RCC_TIM3RST                             ((uint32_t)0x00000002) /* Timer 3 reset */
+#define RCC_WWDGRST                             ((uint32_t)0x00000800) /* Window Watchdog reset */
+#define RCC_USART2RST                           ((uint32_t)0x00020000) /* USART 2 reset */
+#define RCC_I2C1RST                             ((uint32_t)0x00200000) /* I2C 1 reset */
+
+#define RCC_CAN1RST                             ((uint32_t)0x02000000) /* CAN1 reset */
+
+#define RCC_BKPRST                              ((uint32_t)0x08000000) /* Backup interface reset */
+#define RCC_PWRRST                              ((uint32_t)0x10000000) /* Power interface reset */
+
+#define RCC_TIM4RST                             ((uint32_t)0x00000004) /* Timer 4 reset */
+#define RCC_SPI2RST                             ((uint32_t)0x00004000) /* SPI 2 reset */
+#define RCC_USART3RST                           ((uint32_t)0x00040000) /* USART 3 reset */
+#define RCC_I2C2RST                             ((uint32_t)0x00400000) /* I2C 2 reset */
+
+#define RCC_USBRST                              ((uint32_t)0x00800000) /* USB Device reset */
+
+/******************  Bit definition for RCC_AHBPCENR register  ******************/
+#define RCC_DMA1EN                              ((uint16_t)0x0001) /* DMA1 clock enable */
+#define RCC_SRAMEN                              ((uint16_t)0x0004) /* SRAM interface clock enable */
+#define RCC_FLITFEN                             ((uint16_t)0x0010) /* FLITF clock enable */
+#define RCC_CRCEN                               ((uint16_t)0x0040) /* CRC clock enable */
+#define RCC_USBHD                               ((uint16_t)0x1000)
+
+/******************  Bit definition for RCC_APB2PCENR register  *****************/
+#define RCC_AFIOEN                              ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
+#define RCC_IOPAEN                              ((uint32_t)0x00000004) /* I/O port A clock enable */
+#define RCC_IOPBEN                              ((uint32_t)0x00000008) /* I/O port B clock enable */
+#define RCC_IOPCEN                              ((uint32_t)0x00000010) /* I/O port C clock enable */
+#define RCC_IOPDEN                              ((uint32_t)0x00000020) /* I/O port D clock enable */
+#define RCC_ADC1EN                              ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
+
+#define RCC_ADC2EN                              ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
+
+#define RCC_TIM1EN                              ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
+#define RCC_SPI1EN                              ((uint32_t)0x00001000) /* SPI 1 clock enable */
+#define RCC_USART1EN                            ((uint32_t)0x00004000) /* USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCENR register  ******************/
+#define RCC_TIM2EN                              ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
+#define RCC_TIM3EN                              ((uint32_t)0x00000002) /* Timer 3 clock enable */
+#define RCC_WWDGEN                              ((uint32_t)0x00000800) /* Window Watchdog clock enable */
+#define RCC_USART2EN                            ((uint32_t)0x00020000) /* USART 2 clock enable */
+#define RCC_I2C1EN                              ((uint32_t)0x00200000) /* I2C 1 clock enable */
+
+#define RCC_BKPEN                               ((uint32_t)0x08000000) /* Backup interface clock enable */
+#define RCC_PWREN                               ((uint32_t)0x10000000) /* Power interface clock enable */
+
+#define RCC_USBEN                               ((uint32_t)0x00800000) /* USB Device clock enable */
+
+/*******************  Bit definition for RCC_BDCTLR register  *******************/
+#define RCC_LSEON                               ((uint32_t)0x00000001) /* External Low Speed oscillator enable */
+#define RCC_LSERDY                              ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */
+#define RCC_LSEBYP                              ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */
+
+#define RCC_RTCSEL                              ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_RTCSEL_0                            ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_RTCSEL_1                            ((uint32_t)0x00000200) /* Bit 1 */
+
+#define RCC_RTCSEL_NOCLOCK                      ((uint32_t)0x00000000) /* No clock */
+#define RCC_RTCSEL_LSE                          ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */
+#define RCC_RTCSEL_LSI                          ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */
+#define RCC_RTCSEL_HSE                          ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_RTCEN                               ((uint32_t)0x00008000) /* RTC clock enable */
+#define RCC_BDRST                               ((uint32_t)0x00010000) /* Backup domain software reset  */
+
+/*******************  Bit definition for RCC_RSTSCKR register  ********************/
+#define RCC_LSION                               ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
+#define RCC_LSIRDY                              ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
+#define RCC_RMVF                                ((uint32_t)0x01000000) /* Remove reset flag */
+#define RCC_PINRSTF                             ((uint32_t)0x04000000) /* PIN reset flag */
+#define RCC_PORRSTF                             ((uint32_t)0x08000000) /* POR/PDR reset flag */
+#define RCC_SFTRSTF                             ((uint32_t)0x10000000) /* Software Reset flag */
+#define RCC_IWDGRSTF                            ((uint32_t)0x20000000) /* Independent Watchdog reset flag */
+#define RCC_WWDGRSTF                            ((uint32_t)0x40000000) /* Window watchdog reset flag */
+#define RCC_LPWRRSTF                            ((uint32_t)0x80000000) /* Low-Power reset flag */
+
+/******************************************************************************/
+/*                             Real-Time Clock                                */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CTLRH register  ********************/
+#define RTC_CTLRH_SECIE                         ((uint8_t)0x01) /* Second Interrupt Enable */
+#define RTC_CTLRH_ALRIE                         ((uint8_t)0x02) /* Alarm Interrupt Enable */
+#define RTC_CTLRH_OWIE                          ((uint8_t)0x04) /* OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTLRL register  ********************/
+#define RTC_CTLRL_SECF                          ((uint8_t)0x01) /* Second Flag */
+#define RTC_CTLRL_ALRF                          ((uint8_t)0x02) /* Alarm Flag */
+#define RTC_CTLRL_OWF                           ((uint8_t)0x04) /* OverfloW Flag */
+#define RTC_CTLRL_RSF                           ((uint8_t)0x08) /* Registers Synchronized Flag */
+#define RTC_CTLRL_CNF                           ((uint8_t)0x10) /* Configuration Flag */
+#define RTC_CTLRL_RTOFF                         ((uint8_t)0x20) /* RTC operation OFF */
+
+/*******************  Bit definition for RTC_PSCH register  *******************/
+#define RTC_PSCH_PRL                            ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define RTC_PSCL_PRL                            ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define RTC_DIVH_RTC_DIV                        ((uint16_t)0x000F) /* RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define RTC_DIVL_RTC_DIV                        ((uint16_t)0xFFFF) /* RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define RTC_CNTH_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define RTC_CNTL_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRMH register  *******************/
+#define RTC_ALRMH_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRML register  *******************/
+#define RTC_ALRML_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm Low */
+
+/******************************************************************************/
+/*                        Serial Peripheral Interface                         */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTLR1 register  ********************/
+#define SPI_CTLR1_CPHA                          ((uint16_t)0x0001) /* Clock Phase */
+#define SPI_CTLR1_CPOL                          ((uint16_t)0x0002) /* Clock Polarity */
+#define SPI_CTLR1_MSTR                          ((uint16_t)0x0004) /* Master Selection */
+
+#define SPI_CTLR1_BR                            ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTLR1_BR_0                          ((uint16_t)0x0008) /* Bit 0 */
+#define SPI_CTLR1_BR_1                          ((uint16_t)0x0010) /* Bit 1 */
+#define SPI_CTLR1_BR_2                          ((uint16_t)0x0020) /* Bit 2 */
+
+#define SPI_CTLR1_SPE                           ((uint16_t)0x0040) /* SPI Enable */
+#define SPI_CTLR1_LSBFIRST                      ((uint16_t)0x0080) /* Frame Format */
+#define SPI_CTLR1_SSI                           ((uint16_t)0x0100) /* Internal slave select */
+#define SPI_CTLR1_SSM                           ((uint16_t)0x0200) /* Software slave management */
+#define SPI_CTLR1_RXONLY                        ((uint16_t)0x0400) /* Receive only */
+#define SPI_CTLR1_DFF                           ((uint16_t)0x0800) /* Data Frame Format */
+#define SPI_CTLR1_CRCNEXT                       ((uint16_t)0x1000) /* Transmit CRC next */
+#define SPI_CTLR1_CRCEN                         ((uint16_t)0x2000) /* Hardware CRC calculation enable */
+#define SPI_CTLR1_BIDIOE                        ((uint16_t)0x4000) /* Output enable in bidirectional mode */
+#define SPI_CTLR1_BIDIMODE                      ((uint16_t)0x8000) /* Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTLR2 register  ********************/
+#define SPI_CTLR2_RXDMAEN                       ((uint8_t)0x01) /* Rx Buffer DMA Enable */
+#define SPI_CTLR2_TXDMAEN                       ((uint8_t)0x02) /* Tx Buffer DMA Enable */
+#define SPI_CTLR2_SSOE                          ((uint8_t)0x04) /* SS Output Enable */
+#define SPI_CTLR2_ERRIE                         ((uint8_t)0x20) /* Error Interrupt Enable */
+#define SPI_CTLR2_RXNEIE                        ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */
+#define SPI_CTLR2_TXEIE                         ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STATR register  ********************/
+#define SPI_STATR_RXNE                          ((uint8_t)0x01) /* Receive buffer Not Empty */
+#define SPI_STATR_TXE                           ((uint8_t)0x02) /* Transmit buffer Empty */
+#define SPI_STATR_CHSIDE                        ((uint8_t)0x04) /* Channel side */
+#define SPI_STATR_UDR                           ((uint8_t)0x08) /* Underrun flag */
+#define SPI_STATR_CRCERR                        ((uint8_t)0x10) /* CRC Error flag */
+#define SPI_STATR_MODF                          ((uint8_t)0x20) /* Mode fault */
+#define SPI_STATR_OVR                           ((uint8_t)0x40) /* Overrun flag */
+#define SPI_STATR_BSY                           ((uint8_t)0x80) /* Busy flag */
+
+/********************  Bit definition for SPI_DATAR register  ********************/
+#define SPI_DATAR_DR                            ((uint16_t)0xFFFF) /* Data Register */
+
+/*******************  Bit definition for SPI_CRCR register  ******************/
+#define SPI_CRCR_CRCPOLY                        ((uint16_t)0xFFFF) /* CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRCR register  ******************/
+#define SPI_RCRCR_RXCRC                         ((uint16_t)0xFFFF) /* Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRCR register  ******************/
+#define SPI_TCRCR_TXCRC                         ((uint16_t)0xFFFF) /* Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN                       ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN                      ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0                    ((uint16_t)0x0002) /* Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1                    ((uint16_t)0x0004) /* Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL                       ((uint16_t)0x0008) /* steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD                      ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0                    ((uint16_t)0x0010) /* Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1                    ((uint16_t)0x0020) /* Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC                     ((uint16_t)0x0080) /* PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG                      ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                    ((uint16_t)0x0100) /* Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1                    ((uint16_t)0x0200) /* Bit 1 */
+
+#define SPI_I2SCFGR_I2SE                        ((uint16_t)0x0400) /* I2S Enable */
+#define SPI_I2SCFGR_I2SMOD                      ((uint16_t)0x0800) /* I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV                        ((uint16_t)0x00FF) /* I2S Linear prescaler */
+#define SPI_I2SPR_ODD                           ((uint16_t)0x0100) /* Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE                         ((uint16_t)0x0200) /* Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                    TIM                                     */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTLR1 register  ********************/
+#define TIM_CEN                                 ((uint16_t)0x0001) /* Counter enable */
+#define TIM_UDIS                                ((uint16_t)0x0002) /* Update disable */
+#define TIM_URS                                 ((uint16_t)0x0004) /* Update request source */
+#define TIM_OPM                                 ((uint16_t)0x0008) /* One pulse mode */
+#define TIM_DIR                                 ((uint16_t)0x0010) /* Direction */
+
+#define TIM_CMS                                 ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CMS_0                               ((uint16_t)0x0020) /* Bit 0 */
+#define TIM_CMS_1                               ((uint16_t)0x0040) /* Bit 1 */
+
+#define TIM_ARPE                                ((uint16_t)0x0080) /* Auto-reload preload enable */
+
+#define TIM_CTLR1_CKD                           ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */
+#define TIM_CKD_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CKD_1                               ((uint16_t)0x0200) /* Bit 1 */
+
+/*******************  Bit definition for TIM_CTLR2 register  ********************/
+#define TIM_CCPC                                ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */
+#define TIM_CCUS                                ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */
+#define TIM_CCDS                                ((uint16_t)0x0008) /* Capture/Compare DMA Selection */
+
+#define TIM_MMS                                 ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
+#define TIM_MMS_0                               ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_MMS_1                               ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_MMS_2                               ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_TI1S                                ((uint16_t)0x0080) /* TI1 Selection */
+#define TIM_OIS1                                ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */
+#define TIM_OIS1N                               ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */
+#define TIM_OIS2                                ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */
+#define TIM_OIS2N                               ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */
+#define TIM_OIS3                                ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */
+#define TIM_OIS3N                               ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */
+#define TIM_OIS4                                ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCFGR register  *******************/
+#define TIM_SMS                                 ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMS_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_SMS_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_SMS_2                               ((uint16_t)0x0004) /* Bit 2 */
+
+#define TIM_TS                                  ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */
+#define TIM_TS_0                                ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_TS_1                                ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_TS_2                                ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_MSM                                 ((uint16_t)0x0080) /* Master/slave mode */
+
+#define TIM_ETF                                 ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */
+#define TIM_ETF_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_ETF_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_ETF_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_ETF_3                               ((uint16_t)0x0800) /* Bit 3 */
+
+#define TIM_ETPS                                ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_ETPS_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_ETPS_1                              ((uint16_t)0x2000) /* Bit 1 */
+
+#define TIM_ECE                                 ((uint16_t)0x4000) /* External clock enable */
+#define TIM_ETP                                 ((uint16_t)0x8000) /* External trigger polarity */
+
+/*******************  Bit definition for TIM_DMAINTENR register  *******************/
+#define TIM_UIE                                 ((uint16_t)0x0001) /* Update interrupt enable */
+#define TIM_CC1IE                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */
+#define TIM_CC2IE                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */
+#define TIM_CC3IE                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */
+#define TIM_CC4IE                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */
+#define TIM_COMIE                               ((uint16_t)0x0020) /* COM interrupt enable */
+#define TIM_TIE                                 ((uint16_t)0x0040) /* Trigger interrupt enable */
+#define TIM_BIE                                 ((uint16_t)0x0080) /* Break interrupt enable */
+#define TIM_UDE                                 ((uint16_t)0x0100) /* Update DMA request enable */
+#define TIM_CC1DE                               ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */
+#define TIM_CC2DE                               ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */
+#define TIM_CC3DE                               ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */
+#define TIM_CC4DE                               ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */
+#define TIM_COMDE                               ((uint16_t)0x2000) /* COM DMA request enable */
+#define TIM_TDE                                 ((uint16_t)0x4000) /* Trigger DMA request enable */
+
+/********************  Bit definition for TIM_INTFR register  ********************/
+#define TIM_UIF                                 ((uint16_t)0x0001) /* Update interrupt Flag */
+#define TIM_CC1IF                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */
+#define TIM_CC2IF                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */
+#define TIM_CC3IF                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */
+#define TIM_CC4IF                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */
+#define TIM_COMIF                               ((uint16_t)0x0020) /* COM interrupt Flag */
+#define TIM_TIF                                 ((uint16_t)0x0040) /* Trigger interrupt Flag */
+#define TIM_BIF                                 ((uint16_t)0x0080) /* Break interrupt Flag */
+#define TIM_CC1OF                               ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */
+#define TIM_CC2OF                               ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */
+#define TIM_CC3OF                               ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */
+#define TIM_CC4OF                               ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_SWEVGR register  ********************/
+#define TIM_UG                                  ((uint8_t)0x01) /* Update Generation */
+#define TIM_CC1G                                ((uint8_t)0x02) /* Capture/Compare 1 Generation */
+#define TIM_CC2G                                ((uint8_t)0x04) /* Capture/Compare 2 Generation */
+#define TIM_CC3G                                ((uint8_t)0x08) /* Capture/Compare 3 Generation */
+#define TIM_CC4G                                ((uint8_t)0x10) /* Capture/Compare 4 Generation */
+#define TIM_COMG                                ((uint8_t)0x20) /* Capture/Compare Control Update Generation */
+#define TIM_TG                                  ((uint8_t)0x40) /* Trigger Generation */
+#define TIM_BG                                  ((uint8_t)0x80) /* Break Generation */
+
+/******************  Bit definition for TIM_CHCTLR1 register  *******************/
+#define TIM_CC1S                                ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CC1S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC1S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC1FE                               ((uint16_t)0x0004) /* Output Compare 1 Fast enable */
+#define TIM_OC1PE                               ((uint16_t)0x0008) /* Output Compare 1 Preload enable */
+
+#define TIM_OC1M                                ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_OC1M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC1M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC1M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC1CE                               ((uint16_t)0x0080) /* Output Compare 1Clear Enable */
+
+#define TIM_CC2S                                ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CC2S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC2S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC2FE                               ((uint16_t)0x0400) /* Output Compare 2 Fast enable */
+#define TIM_OC2PE                               ((uint16_t)0x0800) /* Output Compare 2 Preload enable */
+
+#define TIM_OC2M                                ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_OC2M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC2M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC2M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC2CE                               ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */
+
+#define TIM_IC1PSC                              ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_IC1PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC1PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC1F                                ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_IC1F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC1F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC1F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC1F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC2PSC                              ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_IC2PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC2PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC2F                                ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_IC2F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC2F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC2F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC2F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/******************  Bit definition for TIM_CHCTLR2 register  *******************/
+#define TIM_CC3S                                ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CC3S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC3S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC3FE                               ((uint16_t)0x0004) /* Output Compare 3 Fast enable */
+#define TIM_OC3PE                               ((uint16_t)0x0008) /* Output Compare 3 Preload enable */
+
+#define TIM_OC3M                                ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_OC3M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC3M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC3M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC3CE                               ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */
+
+#define TIM_CC4S                                ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CC4S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC4S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC4FE                               ((uint16_t)0x0400) /* Output Compare 4 Fast enable */
+#define TIM_OC4PE                               ((uint16_t)0x0800) /* Output Compare 4 Preload enable */
+
+#define TIM_OC4M                                ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_OC4M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC4M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC4M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC4CE                               ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */
+
+#define TIM_IC3PSC                              ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_IC3PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC3PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC3F                                ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_IC3F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC3F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC3F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC3F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC4PSC                              ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_IC4PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC4PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC4F                                ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_IC4F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC4F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC4F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC4F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CC1E                                ((uint16_t)0x0001) /* Capture/Compare 1 output enable */
+#define TIM_CC1P                                ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */
+#define TIM_CC1NE                               ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */
+#define TIM_CC1NP                               ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */
+#define TIM_CC2E                                ((uint16_t)0x0010) /* Capture/Compare 2 output enable */
+#define TIM_CC2P                                ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */
+#define TIM_CC2NE                               ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */
+#define TIM_CC2NP                               ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */
+#define TIM_CC3E                                ((uint16_t)0x0100) /* Capture/Compare 3 output enable */
+#define TIM_CC3P                                ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */
+#define TIM_CC3NE                               ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */
+#define TIM_CC3NP                               ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
+#define TIM_CC4E                                ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
+#define TIM_CC4P                                ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
+#define TIM_CC4NP                               ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT                                 ((uint16_t)0xFFFF) /* Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC                                 ((uint16_t)0xFFFF) /* Prescaler Value */
+
+/*******************  Bit definition for TIM_ATRLR register  ********************/
+#define TIM_ARR                                 ((uint16_t)0xFFFF) /* actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RPTCR register  ********************/
+#define TIM_REP                                 ((uint8_t)0xFF) /* Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CH1CVR register  *******************/
+#define TIM_CCR1                                ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CH2CVR register  *******************/
+#define TIM_CCR2                                ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CH3CVR register  *******************/
+#define TIM_CCR3                                ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CH4CVR register  *******************/
+#define TIM_CCR4                                ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_DTG                                 ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_DTG_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DTG_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DTG_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DTG_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DTG_4                               ((uint16_t)0x0010) /* Bit 4 */
+#define TIM_DTG_5                               ((uint16_t)0x0020) /* Bit 5 */
+#define TIM_DTG_6                               ((uint16_t)0x0040) /* Bit 6 */
+#define TIM_DTG_7                               ((uint16_t)0x0080) /* Bit 7 */
+
+#define TIM_LOCK                                ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
+#define TIM_LOCK_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_LOCK_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OSSI                                ((uint16_t)0x0400) /* Off-State Selection for Idle mode */
+#define TIM_OSSR                                ((uint16_t)0x0800) /* Off-State Selection for Run mode */
+#define TIM_BKE                                 ((uint16_t)0x1000) /* Break enable */
+#define TIM_BKP                                 ((uint16_t)0x2000) /* Break Polarity */
+#define TIM_AOE                                 ((uint16_t)0x4000) /* Automatic Output enable */
+#define TIM_MOE                                 ((uint16_t)0x8000) /* Main Output enable */
+
+/*******************  Bit definition for TIM_DMACFGR register  ********************/
+#define TIM_DBA                                 ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */
+#define TIM_DBA_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DBA_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DBA_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DBA_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DBA_4                               ((uint16_t)0x0010) /* Bit 4 */
+
+#define TIM_DBL                                 ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DBL_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_DBL_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_DBL_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_DBL_3                               ((uint16_t)0x0800) /* Bit 3 */
+#define TIM_DBL_4                               ((uint16_t)0x1000) /* Bit 4 */
+
+/*******************  Bit definition for TIM_DMAADR register  *******************/
+#define TIM_DMAR_DMAB                           ((uint16_t)0xFFFF) /* DMA register for burst accesses */
+
+/******************************************************************************/
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STATR register  *******************/
+#define USART_STATR_PE                          ((uint16_t)0x0001) /* Parity Error */
+#define USART_STATR_FE                          ((uint16_t)0x0002) /* Framing Error */
+#define USART_STATR_NE                          ((uint16_t)0x0004) /* Noise Error Flag */
+#define USART_STATR_ORE                         ((uint16_t)0x0008) /* OverRun Error */
+#define USART_STATR_IDLE                        ((uint16_t)0x0010) /* IDLE line detected */
+#define USART_STATR_RXNE                        ((uint16_t)0x0020) /* Read Data Register Not Empty */
+#define USART_STATR_TC                          ((uint16_t)0x0040) /* Transmission Complete */
+#define USART_STATR_TXE                         ((uint16_t)0x0080) /* Transmit Data Register Empty */
+#define USART_STATR_LBD                         ((uint16_t)0x0100) /* LIN Break Detection Flag */
+#define USART_STATR_CTS                         ((uint16_t)0x0200) /* CTS Flag */
+
+/*******************  Bit definition for USART_DATAR register  *******************/
+#define USART_DATAR_DR                          ((uint16_t)0x01FF) /* Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction                  ((uint16_t)0x000F) /* Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa                  ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTLR1 register  *******************/
+#define USART_CTLR1_SBK                         ((uint16_t)0x0001) /* Send Break */
+#define USART_CTLR1_RWU                         ((uint16_t)0x0002) /* Receiver wakeup */
+#define USART_CTLR1_RE                          ((uint16_t)0x0004) /* Receiver Enable */
+#define USART_CTLR1_TE                          ((uint16_t)0x0008) /* Transmitter Enable */
+#define USART_CTLR1_IDLEIE                      ((uint16_t)0x0010) /* IDLE Interrupt Enable */
+#define USART_CTLR1_RXNEIE                      ((uint16_t)0x0020) /* RXNE Interrupt Enable */
+#define USART_CTLR1_TCIE                        ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */
+#define USART_CTLR1_TXEIE                       ((uint16_t)0x0080) /* PE Interrupt Enable */
+#define USART_CTLR1_PEIE                        ((uint16_t)0x0100) /* PE Interrupt Enable */
+#define USART_CTLR1_PS                          ((uint16_t)0x0200) /* Parity Selection */
+#define USART_CTLR1_PCE                         ((uint16_t)0x0400) /* Parity Control Enable */
+#define USART_CTLR1_WAKE                        ((uint16_t)0x0800) /* Wakeup method */
+#define USART_CTLR1_M                           ((uint16_t)0x1000) /* Word length */
+#define USART_CTLR1_UE                          ((uint16_t)0x2000) /* USART Enable */
+#define USART_CTLR1_OVER8                       ((uint16_t)0x8000) /* USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTLR2 register  *******************/
+#define USART_CTLR2_ADD                         ((uint16_t)0x000F) /* Address of the USART node */
+#define USART_CTLR2_LBDL                        ((uint16_t)0x0020) /* LIN Break Detection Length */
+#define USART_CTLR2_LBDIE                       ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */
+#define USART_CTLR2_LBCL                        ((uint16_t)0x0100) /* Last Bit Clock pulse */
+#define USART_CTLR2_CPHA                        ((uint16_t)0x0200) /* Clock Phase */
+#define USART_CTLR2_CPOL                        ((uint16_t)0x0400) /* Clock Polarity */
+#define USART_CTLR2_CLKEN                       ((uint16_t)0x0800) /* Clock Enable */
+
+#define USART_CTLR2_STOP                        ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */
+#define USART_CTLR2_STOP_0                      ((uint16_t)0x1000) /* Bit 0 */
+#define USART_CTLR2_STOP_1                      ((uint16_t)0x2000) /* Bit 1 */
+
+#define USART_CTLR2_LINEN                       ((uint16_t)0x4000) /* LIN mode enable */
+
+/******************  Bit definition for USART_CTLR3 register  *******************/
+#define USART_CTLR3_EIE                         ((uint16_t)0x0001) /* Error Interrupt Enable */
+#define USART_CTLR3_IREN                        ((uint16_t)0x0002) /* IrDA mode Enable */
+#define USART_CTLR3_IRLP                        ((uint16_t)0x0004) /* IrDA Low-Power */
+#define USART_CTLR3_HDSEL                       ((uint16_t)0x0008) /* Half-Duplex Selection */
+#define USART_CTLR3_NACK                        ((uint16_t)0x0010) /* Smartcard NACK enable */
+#define USART_CTLR3_SCEN                        ((uint16_t)0x0020) /* Smartcard mode enable */
+#define USART_CTLR3_DMAR                        ((uint16_t)0x0040) /* DMA Enable Receiver */
+#define USART_CTLR3_DMAT                        ((uint16_t)0x0080) /* DMA Enable Transmitter */
+#define USART_CTLR3_RTSE                        ((uint16_t)0x0100) /* RTS Enable */
+#define USART_CTLR3_CTSE                        ((uint16_t)0x0200) /* CTS Enable */
+#define USART_CTLR3_CTSIE                       ((uint16_t)0x0400) /* CTS Interrupt Enable */
+#define USART_CTLR3_ONEBIT                      ((uint16_t)0x0800) /* One Bit method */
+
+/******************  Bit definition for USART_GPR register  ******************/
+#define USART_GPR_PSC                           ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
+#define USART_GPR_PSC_0                         ((uint16_t)0x0001) /* Bit 0 */
+#define USART_GPR_PSC_1                         ((uint16_t)0x0002) /* Bit 1 */
+#define USART_GPR_PSC_2                         ((uint16_t)0x0004) /* Bit 2 */
+#define USART_GPR_PSC_3                         ((uint16_t)0x0008) /* Bit 3 */
+#define USART_GPR_PSC_4                         ((uint16_t)0x0010) /* Bit 4 */
+#define USART_GPR_PSC_5                         ((uint16_t)0x0020) /* Bit 5 */
+#define USART_GPR_PSC_6                         ((uint16_t)0x0040) /* Bit 6 */
+#define USART_GPR_PSC_7                         ((uint16_t)0x0080) /* Bit 7 */
+
+#define USART_GPR_GT                            ((uint16_t)0xFF00) /* Guard time value */
+
+/******************************************************************************/
+/*                            Window WATCHDOG                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTLR register  ********************/
+#define WWDG_CTLR_T                             ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTLR_T0                            ((uint8_t)0x01) /* Bit 0 */
+#define WWDG_CTLR_T1                            ((uint8_t)0x02) /* Bit 1 */
+#define WWDG_CTLR_T2                            ((uint8_t)0x04) /* Bit 2 */
+#define WWDG_CTLR_T3                            ((uint8_t)0x08) /* Bit 3 */
+#define WWDG_CTLR_T4                            ((uint8_t)0x10) /* Bit 4 */
+#define WWDG_CTLR_T5                            ((uint8_t)0x20) /* Bit 5 */
+#define WWDG_CTLR_T6                            ((uint8_t)0x40) /* Bit 6 */
+
+#define WWDG_CTLR_WDGA                          ((uint8_t)0x80) /* Activation bit */
+
+/*******************  Bit definition for WWDG_CFGR register  *******************/
+#define WWDG_CFGR_W                             ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */
+#define WWDG_CFGR_W0                            ((uint16_t)0x0001) /* Bit 0 */
+#define WWDG_CFGR_W1                            ((uint16_t)0x0002) /* Bit 1 */
+#define WWDG_CFGR_W2                            ((uint16_t)0x0004) /* Bit 2 */
+#define WWDG_CFGR_W3                            ((uint16_t)0x0008) /* Bit 3 */
+#define WWDG_CFGR_W4                            ((uint16_t)0x0010) /* Bit 4 */
+#define WWDG_CFGR_W5                            ((uint16_t)0x0020) /* Bit 5 */
+#define WWDG_CFGR_W6                            ((uint16_t)0x0040) /* Bit 6 */
+
+#define WWDG_CFGR_WDGTB                         ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFGR_WDGTB0                        ((uint16_t)0x0080) /* Bit 0 */
+#define WWDG_CFGR_WDGTB1                        ((uint16_t)0x0100) /* Bit 1 */
+
+#define WWDG_CFGR_EWI                           ((uint16_t)0x0200) /* Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STATR register  ********************/
+#define WWDG_STATR_EWIF                         ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                          ENHANCED FUNNCTION                                */
+/******************************************************************************/
+
+/****************************  Enhanced register  *****************************/
+#define EXTEN_USBD_LS                           ((uint32_t)0x00000001) /* Bit 0 */
+#define EXTEN_USBD_PU_EN                        ((uint32_t)0x00000002) /* Bit 1 */
+#define EXTEN_ETH_10M_EN                        ((uint32_t)0x00000004) /* Bit 2 */
+#define EXTEN_PLL_HSI_PRE                       ((uint32_t)0x00000010) /* Bit 4 */
+#define EXTEN_LOCKUP_EN                         ((uint32_t)0x00000040) /* Bit 5 */
+#define EXTEN_LOCKUP_RSTF                       ((uint32_t)0x00000080) /* Bit 7 */
+
+#define EXTEN_ULLDO_TRIM                        ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
+#define EXTEN_ULLDO_TRIM0                       ((uint32_t)0x00000100) /* Bit 0 */
+#define EXTEN_ULLDO_TRIM1                       ((uint32_t)0x00000200) /* Bit 1 */
+
+#define EXTEN_LDO_TRIM                          ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */
+#define EXTEN_LDO_TRIM0                         ((uint32_t)0x00000400) /* Bit 0 */
+#define EXTEN_LDO_TRIM1                         ((uint32_t)0x00000800) /* Bit 1 */
+
+/******************************************************************************/
+/*                                  DVP                                       */
+/******************************************************************************/
+
+/*******************  Bit definition for DVP_CR0 register  ********************/
+#define RB_DVP_ENABLE                           0x01  // RW, DVP enable
+#define RB_DVP_V_POLAR                          0x02  // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert
+#define RB_DVP_H_POLAR                          0x04  // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert
+#define RB_DVP_P_POLAR                          0x08  // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert
+#define RB_DVP_MSK_DAT_MOD                      0x30
+#define RB_DVP_D8_MOD                           0x00  // RW, DVP 8bits data mode
+#define RB_DVP_D10_MOD                          0x10  // RW, DVP 10bits data mode
+#define RB_DVP_D12_MOD                          0x20  // RW, DVP 12bits data mode
+#define RB_DVP_JPEG                             0x40  // RW, DVP JPEG mode
+
+/*******************  Bit definition for DVP_CR1 register  ********************/
+#define RB_DVP_DMA_EN                           0x01  // RW, DVP dma enable
+#define RB_DVP_ALL_CLR                          0x02  // RW, DVP all clear, high action
+#define RB_DVP_RCV_CLR                          0x04  // RW, DVP receive logic clear, high action
+#define RB_DVP_BUF_TOG                          0x08  // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0
+#define RB_DVP_CM                               0x10  // RW, DVP capture mode
+#define RB_DVP_CROP                             0x20  // RW, DVP Crop feature enable
+#define RB_DVP_FCRC                             0xC0  // RW, DVP frame capture rate control:
+#define DVP_RATE_100P                           0x00  //00 = every frame captured (100%)
+#define DVP_RATE_50P                            0x40  //01 = every alternate frame captured (50%)
+#define DVP_RATE_25P                            0x80  //10 = one frame in four frame captured (25%)
+
+/*******************  Bit definition for DVP_IER register  ********************/
+#define RB_DVP_IE_STR_FRM                       0x01  // RW, DVP frame start interrupt enable
+#define RB_DVP_IE_ROW_DONE                      0x02  // RW, DVP row received done interrupt enable
+#define RB_DVP_IE_FRM_DONE                      0x04  // RW, DVP frame received done interrupt enable
+#define RB_DVP_IE_FIFO_OV                       0x08  // RW, DVP receive fifo overflow interrupt enable
+#define RB_DVP_IE_STP_FRM                       0x10  // RW, DVP frame stop interrupt enable
+
+/*******************  Bit definition for DVP_IFR register  ********************/
+#define RB_DVP_IF_STR_FRM                       0x01  // RW1, interrupt flag for DVP frame start
+#define RB_DVP_IF_ROW_DONE                      0x02  // RW1, interrupt flag for DVP row receive done
+#define RB_DVP_IF_FRM_DONE                      0x04  // RW1, interrupt flag for DVP frame receive done
+#define RB_DVP_IF_FIFO_OV                       0x08  // RW1, interrupt flag for DVP receive fifo overflow
+#define RB_DVP_IF_STP_FRM                       0x10  // RW1, interrupt flag for DVP frame stop
+
+/*******************  Bit definition for DVP_STATUS register  ********************/
+#define RB_DVP_FIFO_RDY                         0x01  // RO, DVP receive fifo ready
+#define RB_DVP_FIFO_FULL                        0x02  // RO, DVP receive fifo full
+#define RB_DVP_FIFO_OV                          0x04  // RO, DVP receive fifo overflow
+#define RB_DVP_MSK_FIFO_CNT                     0x70  // RO, DVP receive fifo count
+
+
+/******************************************************************************/
+/*                                  ETH10M                                    */
+/******************************************************************************/
+/* ETH register */
+#define R8_ETH_EIE              (*((volatile uint8_t *)(0x40028000+3))) /* Interrupt Enable Register */
+#define  RB_ETH_EIE_INTIE       0x80                  /* RW interrupt enable*/
+#define  RB_ETH_EIE_RXIE        0x40                  /* RW Receive complete interrupt enable */
+#define  RB_ETH_EIE_LINKIE      0x10                  /* RW Link Change Interrupt Enable */
+#define  RB_ETH_EIE_TXIE        0x08                  /* RW send complete interrupt enable */
+#define  RB_ETH_EIE_R_EN50      0x04                  /* RW TX 50�� resistor adjustment. 1: On-chip 50�� connected 0: On-chip 50�� disconnected */
+#define  RB_ETH_EIE_TXERIE      0x02                  /* RW Transmit Error Interrupt Enable */
+#define  RB_ETH_EIE_RXERIE      0x01                  /* RW1 receive error flag */
+#define R8_ETH_EIR              (*((volatile uint8_t *)(0x40028000+4))) /* Interrupt Flag Register */
+#define  RB_ETH_EIR_RXIF        0x40                  /* RW1 Receive complete flag */
+#define  RB_ETH_EIR_LINKIF      0x10                  /* RW1 Link Change Flag */
+#define  RB_ETH_EIR_TXIF        0x08                  /* RW1 Link Change Flag */
+#define  RB_ETH_EIR_TXERIF      0x02                  /* RW1 send error flag */
+#define  RB_ETH_EIR_RXERIF      0x01                  /* RW1 receive error flag */
+#define R8_ETH_ESTAT            (*((volatile uint8_t *)(0x40028000+5))) /* status register */
+#define  RB_ETH_ESTAT_INT       0x80                  /* RW1 interrupt */
+#define  RB_ETH_ESTAT_BUFER     0x40                  /* RW1 Buffer error */
+#define  RB_ETH_ESTAT_RXCRCER   0x20                  /* RO receive crc error */
+#define  RB_ETH_ESTAT_RXNIBBLE  0x10                  /* RO receives nibble error */
+#define  RB_ETH_ESTAT_RXMORE    0x08                  /* RO receives more than maximum packets */
+#define  RB_ETH_ESTAT_RXBUSY    0x04                  /* RO receive busy */
+#define  RB_ETH_ESTAT_TXABRT    0x02                  /* RO send interrupted by mcu */
+#define R8_ETH_ECON2            (*((volatile uint8_t *)(0x40028000+6))) /* ETH PHY Analog Block Control Register */
+#define  RB_ETH_ECON2_RX        0x0E                  /* 011b must be written */
+#define  RB_ETH_ECON2_TX        0x01
+#define  RB_ETH_ECON2_MUST      0x06                  /* 011b must be written */
+#define R8_ETH_ECON1            (*((volatile uint8_t *)(0x40028000+7))) /* Transceiver Control Register */
+#define  RB_ETH_ECON1_TXRST     0x80                  /* RW Send module reset */
+#define  RB_ETH_ECON1_RXRST     0x40                  /* RW Receiver module reset */
+#define  RB_ETH_ECON1_TXRTS     0x08                  /* RW The transmission starts, and it is automatically cleared after the transmission is completed. */
+#define  RB_ETH_ECON1_RXEN      0x04                  /* RW Receive is enabled, when cleared, the error flag RXERIF will change to 1 if it is receiving */
+
+#define R32_ETH_TX              (*((volatile uint32_t *)(0x40028000+8))) /* send control */
+#define R16_ETH_ETXST           (*((volatile uint16_t *)(0x40028000+8))) /* RW Send DMA buffer start address */
+#define R16_ETH_ETXLN           (*((volatile uint16_t *)(0x40028000+0xA))) /* RW send length */
+#define R32_ETH_RX              (*((volatile uint32_t *)(0x40028000+0xC))) /* receive control */
+#define R16_ETH_ERXST           (*((volatile uint16_t *)(0x40028000+0xC))) /* RW Receive DMA buffer start address */
+#define R16_ETH_ERXLN           (*((volatile uint16_t *)(0x40028000+0xE))) /* RO receive length */
+
+#define R32_ETH_HTL             (*((volatile uint32_t *)(0x40028000+0x10)))
+#define R8_ETH_EHT0             (*((volatile uint8_t *)(0x40028000+0x10))) /* RW Hash Table Byte0 */
+#define R8_ETH_EHT1             (*((volatile uint8_t *)(0x40028000+0x11))) /* RW Hash Table Byte1 */
+#define R8_ETH_EHT2             (*((volatile uint8_t *)(0x40028000+0x12))) /* RW Hash Table Byte2 */
+#define R8_ETH_EHT3             (*((volatile uint8_t *)(0x40028000+0x13))) /* RW Hash Table Byte3 */
+#define R32_ETH_HTH             (*((volatile uint32_t *)(0x40028000+0x14)))
+#define R8_ETH_EHT4             (*((volatile uint8_t *)(0x40028000+0x14))) /* RW Hash Table Byte4 */
+#define R8_ETH_EHT5             (*((volatile uint8_t *)(0x40028000+0x15))) /* RW Hash Table Byte5 */
+#define R8_ETH_EHT6             (*((volatile uint8_t *)(0x40028000+0x16))) /* RW Hash Table Byte6 */
+#define R8_ETH_EHT7             (*((volatile uint8_t *)(0x40028000+0x17))) /* RW Hash Table Byte7 */
+
+#define R32_ETH_MACON           (*((volatile uint32_t *)(0x40028000+0x18)))
+#define R8_ETH_ERXFCON          (*((volatile uint8_t *)(0x40028000+0x18))) /* Received Packet Filtering Control Register */
+/* RW 0=Do not enable this filter condition, 1=When ANDOR=1,
+target address mismatch will be filtered, when ANDOR=0, target address match will be accepted */
+#define  RB_ETH_ERXFCON_UCEN    0x80
+#define  RB_ETH_ERXFCON_CRCEN   0x20
+#define  RB_ETH_ERXFCON_EN      0x10
+#define  RB_ETH_ERXFCON_MPEN    0x08
+#define  RB_ETH_ERXFCON_HTEN    0x04
+#define  RB_ETH_ERXFCON_MCEN    0x02
+#define  RB_ETH_ERXFCON_BCEN    0x01
+#define R8_ETH_MACON1           (*((volatile uint8_t *)(0x40028000+0x19))) /* Mac flow control registers */
+/* RW When FULDPX=0 is invalid, when FULDPX=1, 11=send 0 timer pause frame,
+then stop sending, 10=send pause frame periodically, 01=send pause frame once, then stop sending, 00=stop sending pause frame */
+#define  RB_ETH_MACON1_FCEN     0x30
+#define  RB_ETH_MACON1_TXPAUS   0x08                  /* RW Send pause frame enable*/
+#define  RB_ETH_MACON1_RXPAUS   0x04                  /* RW Receive pause frame enable */
+#define  RB_ETH_MACON1_PASSALL  0x02                  /* RW 1=Unfiltered control frames will be written to the buffer, 0=Control frames will be filtered */
+#define  RB_ETH_MACON1_MARXEN   0x01                  /* RW MAC layer receive enable */
+#define R8_ETH_MACON2           (*((volatile uint8_t *)(0x40028000+0x1A))) /* Mac Layer Packet Control Register */
+#define  RB_ETH_MACON2_PADCFG   0xE0                  /* RW Short Packet Padding Settings */
+#define  RB_ETH_MACON2_TXCRCEN  0x10                  /* RW Send to add crc, if you need to add crc in PADCFG, this position is 1 */
+#define  RB_ETH_MACON2_PHDREN   0x08                  /* RW Special 4 bytes do not participate in crc check */
+#define  RB_ETH_MACON2_HFRMEN   0x04                  /* RW Allow jumbo frames */
+#define  RB_ETH_MACON2_FULDPX   0x01                  /* RW full duplex */
+#define R8_ETH_MABBIPG          (*((volatile uint8_t *)(0x40028000+0x1B))) /* Minimum Interpacket Interval Register */
+#define  RB_ETH_MABBIPG_MABBIPG 0x7F                  /* RW Minimum number of bytes between packets */
+
+#define R32_ETH_TIM             (*((volatile uint32_t *)(0x40028000+0x1C)))
+#define R16_ETH_EPAUS           (*((volatile uint16_t *)(0x40028000+0x1C))) /* RW Flow Control Pause Frame Time Register */
+#define R16_ETH_MAMXFL          (*((volatile uint16_t *)(0x40028000+0x1E))) /* RW Maximum Received Packet Length Register */
+#define R16_ETH_MIRD            (*((volatile uint16_t *)(0x40028000+0x20))) /* RW MII read data register */
+
+#define R32_ETH_MIWR            (*((volatile uint32_t *)(0x40028000+0x24)))
+#define R8_ETH_MIREGADR         (*((volatile uint8_t *)(0x40028000+0x24))) /* MII address register*/
+#define  RB_ETH_MIREGADR_MASK   0x1F                  /* RW PHY register address mask */
+#define R8_ETH_MISTAT           (*((volatile uint8_t *)(0x40028000+0x25))) /* RW PHY register address mask */
+//#define  RB_ETH_MIREGADR_MIIWR  0x20                  /* WO MII write command */
+#define R16_ETH_MIWR            (*((volatile uint16_t *)(0x40028000+0x26))) /* WO MII Write Data Register */
+#define R32_ETH_MAADRL          (*((volatile uint32_t *)(0x40028000+0x28))) /* RW MAC 1-4 */
+#define R8_ETH_MAADRL1          (*((volatile uint8_t *)(0x40028000+0x28))) /* RW MAC 1 */
+#define R8_ETH_MAADRL2          (*((volatile uint8_t *)(0x40028000+0x29))) /* RW MAC 2 */
+#define R8_ETH_MAADRL3          (*((volatile uint8_t *)(0x40028000+0x2A))) /* RW MAC 3 */
+#define R8_ETH_MAADRL4          (*((volatile uint8_t *)(0x40028000+0x2B))) /* RW MAC 4 */
+#define R16_ETH_MAADRH          (*((volatile uint16_t *)(0x40028000+0x2C))) /* RW MAC 5-6 */
+#define R8_ETH_MAADRL5          (*((volatile uint8_t *)(0x40028000+0x2C))) /* RW MAC 4 */
+#define R8_ETH_MAADRL6          (*((volatile uint8_t *)(0x40028000+0x2D))) /* RW MAC 4 */
+
+//PHY address
+#define PHY_BMCR                0x00                                            /* Control Register */
+#define PHY_BMSR                0x01                                            /* Status Register */
+#define PHY_ANAR                0x04                                            /* Auto-Negotiation Advertisement Register */
+#define PHY_ANLPAR              0x05                                            /* Auto-Negotiation Link Partner Base  Page Ability Register*/
+#define PHY_ANER                0x06                                            /* Auto-Negotiation Expansion Register */
+#define PHY_MDIX                0x1e                                            /* Custom MDIX Mode Register */
+//Custom MDIX Mode Register  @PHY_MDIX
+#define PN_NORMAL               0x04                                            /* Analog p, n polarity selection */
+#define MDIX_MODE_MASK          0x03                                            /* mdix settings */
+#define MDIX_MODE_AUTO          0x00                                            /*  */
+#define MDIX_MODE_MDIX          0x01
+#define MDIX_MODE_MDI           0x02
+//ECON2 test mode, to be determined
+#define RX_VCM_MODE_0
+#define RX_VCM_MODE_1
+#define RX_VCM_MODE_2
+#define RX_VCM_MODE_3
+//RX reference voltage value setting  @RX_REF
+#define RX_REF_25mV             (0<<2)                                          /* 25mV */
+#define RX_REF_49mV             (1<<2)                                          /* 49mV */
+#define RX_REF_74mV             (2<<2)                                          /* 74mV */
+#define RX_REF_98mV             (3<<2)                                          /* 98mV */
+#define RX_REF_123mV            (4<<2)                                          /* 123mV */
+#define RX_REF_148mV            (5<<2)                                          /* 148mV */
+#define RX_REF_173mV            (6<<2)                                          /* 173mV */
+#define RX_REF_198mV            (7<<2)                                          /* 198mV */
+//TX DRIVER Bias Current  @TX_AMP
+#define TX_AMP_0                (0<<0)                                          /* 43mA   / 14.5mA   (1.4V/0.7V) */
+#define TX_AMP_1                (1<<0)                                          /* 53.1mA / 18mA     (1.8V/0.9V) */
+#define TX_AMP_2                (2<<0)                                          /* 75.6mA / 25.6mA   (2.6V/1.3V) */
+#define TX_AMP_3                (3<<0)                                          /* 122mA  / 41.45mA  (4.1V/2.3V) */
+//FCEN pause frame control      @FCEN
+#define FCEN_0_TIMER            (3<<4)                                          /* Send a 0 timer pause frame, then stop sending */
+#define FCEN_CYCLE              (2<<4)                                          /* Periodically send pause frames */
+#define FCEN_ONCE               (1<<4)                                          /* Send pause frame once, then stop sending */
+#define FCEN_STOP               (0<<4)                                          /* Stop sending pause frames */
+//PADCFG short packet control  @PADCFG
+#define PADCFG_AUTO_0           (7<<5)                                          /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */
+#define PADCFG_NO_ACT_0         (6<<5)                                          /* No padding for short packets */
+/* The detected VLAN network packet whose field is 8100h is automatically filled
+with 00h to 64 bytes, otherwise the short packet is filled with 60 bytes of 0, and then 4 bytes of crc after filling */
+#define PADCFG_DETE_AUTO        (5<<5)
+#define PADCFG_NO_ACT_1         (4<<5)                                          /* No padding for short packets */
+#define PADCFG_AUTO_1           (3<<5)                                          /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */
+#define PADCFG_NO_ACT_2         (2<<5)                                          /* No padding for short packets */
+#define PADCFG_AUTO_3           (1<<5)                                          /* All short packets are filled with 00h to 60 bytes, and then 4 bytes crc */
+#define PADCFG_NO_ACT_3         (0<<5)                                          /* No padding for short packets */
+
+/* Bit or field definition for PHY basic status register */
+#define PHY_Linked_Status       ((uint16_t)0x0004)      /* Valid link established */
+
+#define PHY_Reset                               ((uint16_t)0x8000)      /* PHY Reset */
+
+#define PHY_AutoNego_Complete                   ((uint16_t)0x0020)      /* Auto-Negotioation process completed */
+
+//MII control
+#define  RB_ETH_MIREGADR_MIIWR  0x20                                            /* WO MII write command */
+#define  RB_ETH_MIREGADR_MIRDL  0x1f                                            /* RW PHY register address */
+
+
+#include "ch32v20x_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_adc.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_adc.h
new file mode 100644
index 0000000000..589a8f7ccf
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_adc.h
@@ -0,0 +1,218 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_adc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      ADC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_ADC_H
+#define __CH32V20x_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* ADC Init structure definition */
+typedef struct
+{
+    uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
+                          dual mode.
+                          This parameter can be a value of @ref ADC_mode */
+
+    FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
+                                         Scan (multichannels) or Single (one channel) mode.
+                                         This parameter can be set to ENABLE or DISABLE */
+
+    FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+    uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
+                                      to digital conversion of regular channels. This parameter
+                                      can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+    uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
+                               This parameter can be a value of @ref ADC_data_align */
+
+    uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
+                                   using the sequencer for regular channel group.
+                                   This parameter must range from 1 to 16. */
+
+    uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
+                                    This parameter can be a value of @ref ADC_OutputBuffer */
+
+    uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
+                           This parameter can be a value of @ref ADC_Pga */
+} ADC_InitTypeDef;
+
+/* ADC_mode */
+#define ADC_Mode_Independent                           ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                        ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig                   ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl                ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl                ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                           ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                             ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                            ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                            ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                             ((uint32_t)0x00090000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_CC1                    ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                    ((uint32_t)0x00020000)
+#define ADC_ExternalTrigConv_T2_CC2                    ((uint32_t)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO                   ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4                    ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO        ((uint32_t)0x000C0000)
+
+#define ADC_ExternalTrigConv_T1_CC3                    ((uint32_t)0x00040000)
+#define ADC_ExternalTrigConv_None                      ((uint32_t)0x000E0000)
+
+#define ADC_ExternalTrigConv_T3_CC1                    ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T2_CC3                    ((uint32_t)0x00020000)
+#define ADC_ExternalTrigConv_T8_CC1                    ((uint32_t)0x00060000)
+#define ADC_ExternalTrigConv_T8_TRGO                   ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T5_CC1                    ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_T5_CC3                    ((uint32_t)0x000C0000)
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right                            ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                             ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0                                  ((uint8_t)0x00)
+#define ADC_Channel_1                                  ((uint8_t)0x01)
+#define ADC_Channel_2                                  ((uint8_t)0x02)
+#define ADC_Channel_3                                  ((uint8_t)0x03)
+#define ADC_Channel_4                                  ((uint8_t)0x04)
+#define ADC_Channel_5                                  ((uint8_t)0x05)
+#define ADC_Channel_6                                  ((uint8_t)0x06)
+#define ADC_Channel_7                                  ((uint8_t)0x07)
+#define ADC_Channel_8                                  ((uint8_t)0x08)
+#define ADC_Channel_9                                  ((uint8_t)0x09)
+#define ADC_Channel_10                                 ((uint8_t)0x0A)
+#define ADC_Channel_11                                 ((uint8_t)0x0B)
+#define ADC_Channel_12                                 ((uint8_t)0x0C)
+#define ADC_Channel_13                                 ((uint8_t)0x0D)
+#define ADC_Channel_14                                 ((uint8_t)0x0E)
+#define ADC_Channel_15                                 ((uint8_t)0x0F)
+#define ADC_Channel_16                                 ((uint8_t)0x10)
+#define ADC_Channel_17                                 ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                         ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                            ((uint8_t)ADC_Channel_17)
+
+/*ADC_output_buffer*/
+#define ADC_OutputBuffer_Enable                        ((uint32_t)0x04000000)
+#define ADC_OutputBuffer_Disable                       ((uint32_t)0x00000000)
+
+/*ADC_pga*/
+#define ADC_Pga_1                                      ((uint32_t)0x00000000)
+#define ADC_Pga_4                                      ((uint32_t)0x08000000)
+#define ADC_Pga_16                                     ((uint32_t)0x10000000)
+#define ADC_Pga_64                                     ((uint32_t)0x18000000)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_1Cycles5                        ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                        ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                       ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                       ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                       ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                       ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                       ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                      ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T2_TRGO              ((uint32_t)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1               ((uint32_t)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4               ((uint32_t)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO              ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4    ((uint32_t)0x00006000)
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4               ((uint32_t)0x00001000)
+#define ADC_ExternalTrigInjecConv_None                 ((uint32_t)0x00007000)
+
+#define ADC_ExternalTrigInjecConv_T4_CC3               ((uint32_t)0x00002000)
+#define ADC_ExternalTrigInjecConv_T8_CC2               ((uint32_t)0x00003000)
+#define ADC_ExternalTrigInjecConv_T8_CC4               ((uint32_t)0x00004000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO              ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_T5_CC4               ((uint32_t)0x00006000)
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1                          ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                          ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                          ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                          ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable             ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable           ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable      ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable                ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable              ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable        ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                        ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC                                     ((uint16_t)0x0220)
+#define ADC_IT_AWD                                     ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                    ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD                                   ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                   ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                                  ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                                 ((uint8_t)0x08)
+#define ADC_FLAG_STRT                                  ((uint8_t)0x10)
+
+void       ADC_DeInit(ADC_TypeDef *ADCx);
+void       ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+void       ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
+void       ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void       ADC_ResetCalibration(ADC_TypeDef *ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
+void       ADC_StartCalibration(ADC_TypeDef *ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
+void       ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
+void       ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
+void       ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void       ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+uint16_t   ADC_GetConversionValue(ADC_TypeDef *ADCx);
+uint32_t   ADC_GetDualModeConversionValue(void);
+void       ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void       ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
+void       ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void       ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
+void       ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t   ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
+void       ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
+void       ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void       ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
+void       ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+void       ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+ITStatus   ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
+void       ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
+s32        TempSensor_Volt_To_Temper(s32 Value);
+void       ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+int16_t    Get_CalibrationValue(ADC_TypeDef *ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_bkp.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_bkp.h
new file mode 100644
index 0000000000..37b2b658e7
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_bkp.h
@@ -0,0 +1,91 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_bkp.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      BKP firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_BKP_H
+#define __CH32V20x_BKP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* Tamper_Pin_active_level */
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+
+/* RTC_output_source_to_output_on_the_Tamper_pin */
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+
+/* Data_Backup_Register */
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+void       BKP_DeInit(void);
+void       BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void       BKP_TamperPinCmd(FunctionalState NewState);
+void       BKP_ITConfig(FunctionalState NewState);
+void       BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void       BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void       BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t   BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void       BKP_ClearFlag(void);
+ITStatus   BKP_GetITStatus(void);
+void       BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_can.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_can.h
new file mode 100644
index 0000000000..fbf11381b2
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_can.h
@@ -0,0 +1,358 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_can.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      CAN firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_CAN_H
+#define __CH32V20x_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* CAN init structure definition */
+typedef struct
+{
+    uint16_t CAN_Prescaler; /* Specifies the length of a time quantum.
+                               It ranges from 1 to 1024. */
+
+    uint8_t CAN_Mode; /* Specifies the CAN operating mode.
+                         This parameter can be a value of
+                        @ref CAN_operating_mode */
+
+    uint8_t CAN_SJW; /* Specifies the maximum number of time quanta
+                        the CAN hardware is allowed to lengthen or
+                        shorten a bit to perform resynchronization.
+                        This parameter can be a value of
+                        @ref CAN_synchronisation_jump_width */
+
+    uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit
+                        Segment 1. This parameter can be a value of
+                        @ref CAN_time_quantum_in_bit_segment_1 */
+
+    uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit
+                        Segment 2.
+                        This parameter can be a value of
+                        @ref CAN_time_quantum_in_bit_segment_2 */
+
+    FunctionalState CAN_TTCM; /* Enable or disable the time triggered
+                                 communication mode. This parameter can be set
+                                 either to ENABLE or DISABLE. */
+
+    FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off
+                                 management. This parameter can be set either
+                                 to ENABLE or DISABLE. */
+
+    FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode.
+                                 This parameter can be set either to ENABLE or
+                                 DISABLE. */
+
+    FunctionalState CAN_NART; /* Enable or disable the no-automatic
+                                 retransmission mode. This parameter can be
+                                 set either to ENABLE or DISABLE. */
+
+    FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode.
+                                 This parameter can be set either to ENABLE
+                                 or DISABLE. */
+
+    FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority.
+                                 This parameter can be set either to ENABLE
+                                 or DISABLE. */
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+    uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit
+                                      configuration, first one for a 16-bit configuration).
+                                      This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit
+                                     configuration, second one for a 16-bit configuration).
+                                     This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number,
+                                          according to the mode (MSBs for a 32-bit configuration,
+                                          first one for a 16-bit configuration).
+                                          This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number,
+                                         according to the mode (LSBs for a 32-bit configuration,
+                                         second one for a 16-bit configuration).
+                                         This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+
+    uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+    uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized.
+                                   This parameter can be a value of @ref CAN_filter_mode */
+
+    uint8_t CAN_FilterScale; /* Specifies the filter scale.
+                                    This parameter can be a value of @ref CAN_filter_scale */
+
+    FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+    uint32_t StdId; /* Specifies the standard identifier.
+                       This parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t ExtId; /* Specifies the extended identifier.
+                       This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    uint8_t IDE; /* Specifies the type of identifier for the message that
+                    will be transmitted. This parameter can be a value
+                    of @ref CAN_identifier_type */
+
+    uint8_t RTR; /* Specifies the type of frame for the message that will
+                    be transmitted. This parameter can be a value of
+                    @ref CAN_remote_transmission_request */
+
+    uint8_t DLC; /* Specifies the length of the frame that will be
+                    transmitted. This parameter can be a value between
+                    0 to 8 */
+
+    uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0
+                         to 0xFF. */
+} CanTxMsg;
+
+/* CAN Rx message structure definition  */
+typedef struct
+{
+    uint32_t StdId; /* Specifies the standard identifier.
+                       This parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t ExtId; /* Specifies the extended identifier.
+                       This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    uint8_t IDE; /* Specifies the type of identifier for the message that
+                    will be received. This parameter can be a value of
+                    @ref CAN_identifier_type */
+
+    uint8_t RTR; /* Specifies the type of frame for the received message.
+                    This parameter can be a value of
+                    @ref CAN_remote_transmission_request */
+
+    uint8_t DLC; /* Specifies the length of the frame that will be received.
+                    This parameter can be a value between 0 to 8 */
+
+    uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to
+                        0xFF. */
+
+    uint8_t FMI; /* Specifies the index of the filter the message stored in
+                    the mailbox passes through. This parameter can be a
+                    value between 0 to 0xFF */
+} CanRxMsg;
+
+/* CAN_sleep_constants */
+#define CAN_InitStatus_Failed               ((uint8_t)0x00) /* CAN initialization failed */
+#define CAN_InitStatus_Success              ((uint8_t)0x01) /* CAN initialization OK */
+
+/* CAN_Mode */
+#define CAN_Mode_Normal                     ((uint8_t)0x00) /* normal mode */
+#define CAN_Mode_LoopBack                   ((uint8_t)0x01) /* loopback mode */
+#define CAN_Mode_Silent                     ((uint8_t)0x02) /* silent mode */
+#define CAN_Mode_Silent_LoopBack            ((uint8_t)0x03) /* loopback combined with silent mode */
+
+/* CAN_Operating_Mode */
+#define CAN_OperatingMode_Initialization    ((uint8_t)0x00) /* Initialization mode */
+#define CAN_OperatingMode_Normal            ((uint8_t)0x01) /* Normal mode */
+#define CAN_OperatingMode_Sleep             ((uint8_t)0x02) /* sleep mode */
+
+/* CAN_Mode_Status */
+#define CAN_ModeStatus_Failed               ((uint8_t)0x00)                   /* CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success              ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */
+
+/* CAN_synchronisation_jump_width */
+#define CAN_SJW_1tq                         ((uint8_t)0x00) /* 1 time quantum */
+#define CAN_SJW_2tq                         ((uint8_t)0x01) /* 2 time quantum */
+#define CAN_SJW_3tq                         ((uint8_t)0x02) /* 3 time quantum */
+#define CAN_SJW_4tq                         ((uint8_t)0x03) /* 4 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_1 */
+#define CAN_BS1_1tq                         ((uint8_t)0x00) /* 1 time quantum */
+#define CAN_BS1_2tq                         ((uint8_t)0x01) /* 2 time quantum */
+#define CAN_BS1_3tq                         ((uint8_t)0x02) /* 3 time quantum */
+#define CAN_BS1_4tq                         ((uint8_t)0x03) /* 4 time quantum */
+#define CAN_BS1_5tq                         ((uint8_t)0x04) /* 5 time quantum */
+#define CAN_BS1_6tq                         ((uint8_t)0x05) /* 6 time quantum */
+#define CAN_BS1_7tq                         ((uint8_t)0x06) /* 7 time quantum */
+#define CAN_BS1_8tq                         ((uint8_t)0x07) /* 8 time quantum */
+#define CAN_BS1_9tq                         ((uint8_t)0x08) /* 9 time quantum */
+#define CAN_BS1_10tq                        ((uint8_t)0x09) /* 10 time quantum */
+#define CAN_BS1_11tq                        ((uint8_t)0x0A) /* 11 time quantum */
+#define CAN_BS1_12tq                        ((uint8_t)0x0B) /* 12 time quantum */
+#define CAN_BS1_13tq                        ((uint8_t)0x0C) /* 13 time quantum */
+#define CAN_BS1_14tq                        ((uint8_t)0x0D) /* 14 time quantum */
+#define CAN_BS1_15tq                        ((uint8_t)0x0E) /* 15 time quantum */
+#define CAN_BS1_16tq                        ((uint8_t)0x0F) /* 16 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_2 */
+#define CAN_BS2_1tq                         ((uint8_t)0x00) /* 1 time quantum */
+#define CAN_BS2_2tq                         ((uint8_t)0x01) /* 2 time quantum */
+#define CAN_BS2_3tq                         ((uint8_t)0x02) /* 3 time quantum */
+#define CAN_BS2_4tq                         ((uint8_t)0x03) /* 4 time quantum */
+#define CAN_BS2_5tq                         ((uint8_t)0x04) /* 5 time quantum */
+#define CAN_BS2_6tq                         ((uint8_t)0x05) /* 6 time quantum */
+#define CAN_BS2_7tq                         ((uint8_t)0x06) /* 7 time quantum */
+#define CAN_BS2_8tq                         ((uint8_t)0x07) /* 8 time quantum */
+
+/* CAN_filter_mode */
+#define CAN_FilterMode_IdMask               ((uint8_t)0x00) /* identifier/mask mode */
+#define CAN_FilterMode_IdList               ((uint8_t)0x01) /* identifier list mode */
+
+/* CAN_filter_scale */
+#define CAN_FilterScale_16bit               ((uint8_t)0x00) /* Two 16-bit filters */
+#define CAN_FilterScale_32bit               ((uint8_t)0x01) /* One 32-bit filter */
+
+/* CAN_filter_FIFO */
+#define CAN_Filter_FIFO0                    ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                    ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */
+
+/* CAN_identifier_type */
+#define CAN_Id_Standard                     ((uint32_t)0x00000000) /* Standard Id */
+#define CAN_Id_Extended                     ((uint32_t)0x00000004) /* Extended Id */
+
+/* CAN_remote_transmission_request */
+#define CAN_RTR_Data                        ((uint32_t)0x00000000) /* Data frame */
+#define CAN_RTR_Remote                      ((uint32_t)0x00000002) /* Remote frame */
+
+/* CAN_transmit_constants */
+#define CAN_TxStatus_Failed                 ((uint8_t)0x00) /* CAN transmission failed */
+#define CAN_TxStatus_Ok                     ((uint8_t)0x01) /* CAN transmission succeeded */
+#define CAN_TxStatus_Pending                ((uint8_t)0x02) /* CAN transmission pending */
+#define CAN_TxStatus_NoMailBox              ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN_receive_FIFO_number_constants */
+#define CAN_FIFO0                           ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
+#define CAN_FIFO1                           ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
+
+/* CAN_sleep_constants */
+#define CAN_Sleep_Failed                    ((uint8_t)0x00) /* CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                        ((uint8_t)0x01) /* CAN entered the sleep mode */
+
+/* CAN_wake_up_constants */
+#define CAN_WakeUp_Failed                   ((uint8_t)0x00) /* CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                       ((uint8_t)0x01) /* CAN leaved the sleep mode */
+
+/* CAN_Error_Code_constants */
+#define CAN_ErrorCode_NoErr                 ((uint8_t)0x00) /* No Error */
+#define CAN_ErrorCode_StuffErr              ((uint8_t)0x10) /* Stuff Error */
+#define CAN_ErrorCode_FormErr               ((uint8_t)0x20) /* Form Error */
+#define CAN_ErrorCode_ACKErr                ((uint8_t)0x30) /* Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr       ((uint8_t)0x40) /* Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr        ((uint8_t)0x50) /* Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr                ((uint8_t)0x60) /* CRC Error  */
+#define CAN_ErrorCode_SoftwareSetErr        ((uint8_t)0x70) /* Software Set Error */
+
+/* CAN_flags */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                      ((uint32_t)0x38000001) /* Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                      ((uint32_t)0x38000100) /* Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                      ((uint32_t)0x38010000) /* Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0                       ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0                        ((uint32_t)0x32000008) /* FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0                       ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1                       ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1                        ((uint32_t)0x34000008) /* FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1                       ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU                        ((uint32_t)0x31000008) /* Wake up Flag */
+#define CAN_FLAG_SLAK                       ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG                        ((uint32_t)0x10F00001) /* Error Warning Flag   */
+#define CAN_FLAG_EPV                        ((uint32_t)0x10F00002) /* Error Passive Flag   */
+#define CAN_FLAG_BOF                        ((uint32_t)0x10F00004) /* Bus-Off Flag         */
+#define CAN_FLAG_LEC                        ((uint32_t)0x30F00070) /* Last error code Flag */
+
+/* CAN_interrupts */
+#define CAN_IT_TME                          ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                         ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                          ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                         ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                         ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                          ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                         ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                          ((uint32_t)0x00010000) /* Wake-up Interrupt*/
+#define CAN_IT_SLK                          ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                          ((uint32_t)0x00000100) /* Error warning Interrupt*/
+#define CAN_IT_EPV                          ((uint32_t)0x00000200) /* Error passive Interrupt*/
+#define CAN_IT_BOF                          ((uint32_t)0x00000400) /* Bus-off Interrupt*/
+#define CAN_IT_LEC                          ((uint32_t)0x00000800) /* Last error code Interrupt*/
+#define CAN_IT_ERR                          ((uint32_t)0x00008000) /* Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0                        CAN_IT_TME
+#define CAN_IT_RQCP1                        CAN_IT_TME
+#define CAN_IT_RQCP2                        CAN_IT_TME
+
+/* CAN_Legacy */
+#define CANINITFAILED                       CAN_InitStatus_Failed
+#define CANINITOK                           CAN_InitStatus_Success
+#define CAN_FilterFIFO0                     CAN_Filter_FIFO0
+#define CAN_FilterFIFO1                     CAN_Filter_FIFO1
+#define CAN_ID_STD                          CAN_Id_Standard
+#define CAN_ID_EXT                          CAN_Id_Extended
+#define CAN_RTR_DATA                        CAN_RTR_Data
+#define CAN_RTR_REMOTE                      CAN_RTR_Remote
+#define CANTXFAILE                          CAN_TxStatus_Failed
+#define CANTXOK                             CAN_TxStatus_Ok
+#define CANTXPENDING                        CAN_TxStatus_Pending
+#define CAN_NO_MB                           CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED                      CAN_Sleep_Failed
+#define CANSLEEPOK                          CAN_Sleep_Ok
+#define CANWAKEUPFAILED                     CAN_WakeUp_Failed
+#define CANWAKEUPOK                         CAN_WakeUp_Ok
+
+void       CAN_DeInit(CAN_TypeDef *CANx);
+uint8_t    CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct);
+void       CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct);
+void       CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct);
+void       CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void       CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState);
+void       CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState);
+uint8_t    CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage);
+uint8_t    CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox);
+void       CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox);
+void       CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage);
+void       CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber);
+uint8_t    CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber);
+uint8_t    CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode);
+uint8_t    CAN_Sleep(CAN_TypeDef *CANx);
+uint8_t    CAN_WakeUp(CAN_TypeDef *CANx);
+uint8_t    CAN_GetLastErrorCode(CAN_TypeDef *CANx);
+uint8_t    CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx);
+uint8_t    CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx);
+void       CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
+void       CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
+ITStatus   CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT);
+void       CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_crc.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_crc.h
new file mode 100644
index 0000000000..dcd9bb394e
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_crc.h
@@ -0,0 +1,31 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_crc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      CRC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_CRC_H
+#define __CH32V20x_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+void     CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void     CRC_SetIDRegister(uint8_t IDValue);
+uint8_t  CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dbgmcu.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dbgmcu.h
new file mode 100644
index 0000000000..6272c78aae
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dbgmcu.h
@@ -0,0 +1,50 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_dbgmcu.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      DBGMCU firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_DBGMCU_H
+#define __CH32V20x_DBGMCU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00000400)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00000800)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00002000)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00004000)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00008000)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00010000)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00020000)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00040000)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00080000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00400000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00800000)
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+uint32_t __get_DEBUG_CR(void);
+void __set_DEBUG_CR(uint32_t value);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dma.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dma.h
new file mode 100644
index 0000000000..29f40f21d7
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_dma.h
@@ -0,0 +1,182 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_dma.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      DMA firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_DMA_H
+#define __CH32V20x_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* DMA Init structure definition */
+typedef struct
+{
+    uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
+
+    uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
+
+    uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
+                         This parameter can be a value of @ref DMA_data_transfer_direction */
+
+    uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
+                                The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                or DMA_MemoryDataSize members depending in the transfer direction. */
+
+    uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
+                                   This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+    uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
+                               This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+    uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+    uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
+                                    This parameter can be a value of @ref DMA_memory_data_size */
+
+    uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
+                          This parameter can be a value of @ref DMA_circular_normal_mode.
+                          @note: The circular buffer mode cannot be used if the memory-to-memory
+                                data transfer is configured on the selected Channel */
+
+    uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
+                              This parameter can be a value of @ref DMA_priority_level */
+
+    uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                         This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitTypeDef;
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+#define DMA1_IT_GL8                        ((uint32_t)0x10000000)
+#define DMA1_IT_TC8                        ((uint32_t)0x20000000)
+#define DMA1_IT_HT8                        ((uint32_t)0x40000000)
+#define DMA1_IT_TE8                        ((uint32_t)0x80000000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+#define DMA1_FLAG_GL8                      ((uint32_t)0x10000000)
+#define DMA1_FLAG_TC8                      ((uint32_t)0x20000000)
+#define DMA1_FLAG_HT8                      ((uint32_t)0x40000000)
+#define DMA1_FLAG_TE8                      ((uint32_t)0x80000000)
+
+void       DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
+void       DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
+void       DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
+void       DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
+void       DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void       DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
+uint16_t   DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void       DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus   DMA_GetITStatus(uint32_t DMAy_IT);
+void       DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_exti.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_exti.h
new file mode 100644
index 0000000000..bc0f159f58
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_exti.h
@@ -0,0 +1,93 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_exti.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      EXTI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_EXTI_H
+#define __CH32V20x_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* EXTI mode enumeration */
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event = 0x04
+} EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+    EXTI_Trigger_Rising = 0x08,
+    EXTI_Trigger_Falling = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_TypeDef;
+
+/* EXTI Init Structure definition */
+typedef struct
+{
+    uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
+                           This parameter can be any combination of @ref EXTI_Lines */
+
+    EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
+                                   This parameter can be a value of @ref EXTIMode_TypeDef */
+
+    EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+    FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitTypeDef;
+
+/* EXTI_Lines */
+#define EXTI_Line0     ((uint32_t)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1     ((uint32_t)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2     ((uint32_t)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3     ((uint32_t)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4     ((uint32_t)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5     ((uint32_t)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6     ((uint32_t)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7     ((uint32_t)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8     ((uint32_t)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9     ((uint32_t)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10    ((uint32_t)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11    ((uint32_t)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12    ((uint32_t)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13    ((uint32_t)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14    ((uint32_t)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15    ((uint32_t)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16    ((uint32_t)0x10000)  /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17    ((uint32_t)0x20000)  /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18    ((uint32_t)0x40000)  /* External interrupt line 18 Connected to the USBD Device \
+                                               Wakeup from suspend event */
+#define EXTI_Line19    ((uint32_t)0x80000)  /* External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20    ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+  #define EXTI_Line21    ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */
+
+#endif
+
+void       EXTI_DeInit(void);
+void       EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
+void       EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
+void       EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void       EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus   EXTI_GetITStatus(uint32_t EXTI_Line);
+void       EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_flash.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_flash.h
new file mode 100644
index 0000000000..7a4ed15139
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_flash.h
@@ -0,0 +1,142 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_flash.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the FLASH
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_FLASH_H
+#define __CH32V20x_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* FLASH Status */
+typedef enum
+{
+    FLASH_BUSY = 1,
+    FLASH_ERROR_PG,
+    FLASH_ERROR_WRP,
+    FLASH_COMPLETE,
+    FLASH_TIMEOUT
+} FLASH_Status;
+
+/* Write Protect */
+#define FLASH_WRProt_Sectors0          ((uint32_t)0x00000001) /* Write protection of setor 0  */
+#define FLASH_WRProt_Sectors1          ((uint32_t)0x00000002) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors2          ((uint32_t)0x00000004) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors3          ((uint32_t)0x00000008) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors4          ((uint32_t)0x00000010) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors5          ((uint32_t)0x00000020) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors6          ((uint32_t)0x00000040) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors7          ((uint32_t)0x00000080) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors8          ((uint32_t)0x00000100) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors9          ((uint32_t)0x00000200) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors10         ((uint32_t)0x00000400) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors11         ((uint32_t)0x00000800) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors12         ((uint32_t)0x00001000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors13         ((uint32_t)0x00002000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors14         ((uint32_t)0x00004000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors15         ((uint32_t)0x00008000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors16         ((uint32_t)0x00010000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors17         ((uint32_t)0x00020000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors18         ((uint32_t)0x00040000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors19         ((uint32_t)0x00080000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors20         ((uint32_t)0x00100000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors21         ((uint32_t)0x00200000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors22         ((uint32_t)0x00400000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors23         ((uint32_t)0x00800000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors24         ((uint32_t)0x01000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors25         ((uint32_t)0x02000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors26         ((uint32_t)0x04000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors27         ((uint32_t)0x08000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors28         ((uint32_t)0x10000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors29         ((uint32_t)0x20000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors30         ((uint32_t)0x40000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors31to127    ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllSectors        ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW                     ((uint16_t)0x0001) /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000) /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY  */
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* FLASH_Interrupts */
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400) /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR         /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP           /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001) /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020) /* FLASH End of Operation flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010) /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY           FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP           FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_WRPRTERR      FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
+
+/* FLASH_Access_CLK */
+#define FLASH_Access_SYSTEM_HALF      ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */
+#define FLASH_Access_SYSTEM           ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */
+
+/*Functions used for all devices*/
+void         FLASH_Unlock(void);
+void         FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t     FLASH_GetUserOptionByte(void);
+uint32_t     FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus   FLASH_GetReadOutProtectionStatus(void);
+void         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void         FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+void         FLASH_Unlock_Fast(void);
+void         FLASH_Lock_Fast(void);
+void         FLASH_ErasePage_Fast(uint32_t Page_Address);
+void         FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
+void         FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
+void         FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf);
+void         FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
+void         FLASH_Enhance_Mode(FunctionalState NewState);
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+void         FLASH_GetMACAddress(uint8_t *Buffer);
+#endif
+
+/* New function used for all devices */
+void         FLASH_UnlockBank1(void);
+void         FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_gpio.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_gpio.h
new file mode 100644
index 0000000000..2767caeb17
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_gpio.h
@@ -0,0 +1,189 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_gpio.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      GPIO firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_GPIO_H
+#define __CH32V20x_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* Output Maximum frequency selection */
+typedef enum
+{
+    GPIO_Speed_10MHz = 1,
+    GPIO_Speed_2MHz,
+    GPIO_Speed_50MHz
+} GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{
+    GPIO_Mode_AIN = 0x0,
+    GPIO_Mode_IN_FLOATING = 0x04,
+    GPIO_Mode_IPD = 0x28,
+    GPIO_Mode_IPU = 0x48,
+    GPIO_Mode_Out_OD = 0x14,
+    GPIO_Mode_Out_PP = 0x10,
+    GPIO_Mode_AF_OD = 0x1C,
+    GPIO_Mode_AF_PP = 0x18
+} GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+    uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
+                          This parameter can be any value of @ref GPIO_pins_define */
+
+    GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
+                                     This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+    GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
+                                   This parameter can be a value of @ref GPIOMode_TypeDef */
+} GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                      ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1                      ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2                      ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3                      ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4                      ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5                      ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6                      ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7                      ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_8                      ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_Pin_9                      ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_Pin_10                     ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_Pin_11                     ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_Pin_12                     ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_Pin_13                     ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_Pin_14                     ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_Pin_15                     ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_Pin_All                    ((uint16_t)0xFFFF) /* All pins selected */
+
+/* GPIO_Remap_define */
+/* PCFR1 */
+#define GPIO_Remap_SPI1                 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1                 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1               ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
+#define GPIO_Remap_USART2               ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3        ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3           ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1          ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1             ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2         ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2         ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2             ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3          ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3             ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4                 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1                ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1                ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01                 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI          ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ         ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG         ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ         ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG         ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH                  ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2                 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_MII_RMII_SEL         ((uint32_t)0x00200080) /* MII or RMII selection */
+#define GPIO_Remap_SWJ_NoJTRST          ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable      ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable          ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3                 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF     ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
+                                                                  to TIM2 Internal Trigger 1 for calibration                    \
+                                                                  (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS              ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+/* PCFR2 */
+#define GPIO_Remap_TIM8                 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
+#define GPIO_PartialRemap_TIM9          ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM9             ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM10         ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM10            ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
+#define GPIO_Remap_FSMC_NADV            ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
+#define GPIO_PartialRemap_USART4        ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART4           ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART5        ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART5           ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART6        ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART6           ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART7        ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART7           ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART8        ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART8           ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
+#define GPIO_Remap_USART1_HighBit       ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA            ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB            ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC            ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD            ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE            ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF            ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG            ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0                 ((uint8_t)0x00)
+#define GPIO_PinSource1                 ((uint8_t)0x01)
+#define GPIO_PinSource2                 ((uint8_t)0x02)
+#define GPIO_PinSource3                 ((uint8_t)0x03)
+#define GPIO_PinSource4                 ((uint8_t)0x04)
+#define GPIO_PinSource5                 ((uint8_t)0x05)
+#define GPIO_PinSource6                 ((uint8_t)0x06)
+#define GPIO_PinSource7                 ((uint8_t)0x07)
+#define GPIO_PinSource8                 ((uint8_t)0x08)
+#define GPIO_PinSource9                 ((uint8_t)0x09)
+#define GPIO_PinSource10                ((uint8_t)0x0A)
+#define GPIO_PinSource11                ((uint8_t)0x0B)
+#define GPIO_PinSource12                ((uint8_t)0x0C)
+#define GPIO_PinSource13                ((uint8_t)0x0D)
+#define GPIO_PinSource14                ((uint8_t)0x0E)
+#define GPIO_PinSource15                ((uint8_t)0x0F)
+
+/* Ethernet_Media_Interface */
+#define GPIO_ETH_MediaInterface_MII     ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII    ((u32)0x00000001)
+
+void     GPIO_DeInit(GPIO_TypeDef *GPIOx);
+void     GPIO_AFIODeInit(void);
+void     GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
+void     GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
+uint8_t  GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
+uint8_t  GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
+void     GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void     GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
+void     GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void     GPIO_EventOutputCmd(FunctionalState NewState);
+void     GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void     GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void     GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_i2c.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_i2c.h
new file mode 100644
index 0000000000..2da137d0dd
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_i2c.h
@@ -0,0 +1,199 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_i2c.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      I2C firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_I2C_H
+#define __CH32V20x_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* I2C Init structure definition  */
+typedef struct
+{
+    uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
+                                This parameter must be set to a value lower than 400kHz */
+
+    uint16_t I2C_Mode; /* Specifies the I2C mode.
+                          This parameter can be a value of @ref I2C_mode */
+
+    uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
+                               This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+    uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
+                                 This parameter can be a 7-bit or 10-bit address. */
+
+    uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
+                         This parameter can be a value of @ref I2C_acknowledgement */
+
+    uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitTypeDef;
+
+/* I2C_mode */
+#define I2C_Mode_I2C                                         ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice                                 ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost                                   ((uint16_t)0x000A)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9                                   ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                                      ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable                                       ((uint16_t)0x0400)
+#define I2C_Ack_Disable                                      ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define I2C_Direction_Transmitter                            ((uint8_t)0x00)
+#define I2C_Direction_Receiver                               ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit                         ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit                        ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1                                   ((uint8_t)0x00)
+#define I2C_Register_CTLR2                                   ((uint8_t)0x04)
+#define I2C_Register_OADDR1                                  ((uint8_t)0x08)
+#define I2C_Register_OADDR2                                  ((uint8_t)0x0C)
+#define I2C_Register_DATAR                                   ((uint8_t)0x10)
+#define I2C_Register_STAR1                                   ((uint8_t)0x14)
+#define I2C_Register_STAR2                                   ((uint8_t)0x18)
+#define I2C_Register_CKCFGR                                  ((uint8_t)0x1C)
+#define I2C_Register_RTR                                     ((uint8_t)0x20)
+
+/* I2C_SMBus_alert_pin_level */
+#define I2C_SMBusAlert_Low                                   ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High                                  ((uint16_t)0xDFFF)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next                                 ((uint16_t)0x0800)
+#define I2C_PECPosition_Current                              ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next                                ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current                             ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF                                           ((uint16_t)0x0400)
+#define I2C_IT_EVT                                           ((uint16_t)0x0200)
+#define I2C_IT_ERR                                           ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_SMBALERT                                      ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                                       ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                                        ((uint32_t)0x01001000)
+#define I2C_IT_OVR                                           ((uint32_t)0x01000800)
+#define I2C_IT_AF                                            ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                                          ((uint32_t)0x01000200)
+#define I2C_IT_BERR                                          ((uint32_t)0x01000100)
+#define I2C_IT_TXE                                           ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                                          ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                                         ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                                         ((uint32_t)0x02000008)
+#define I2C_IT_BTF                                           ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                                          ((uint32_t)0x02000002)
+#define I2C_IT_SB                                            ((uint32_t)0x02000001)
+
+/* SR2 register flags  */
+#define I2C_FLAG_DUALF                                       ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                                     ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT                                  ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                                     ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                                         ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                                        ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                                         ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT                                    ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                                     ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                                      ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                                         ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                                          ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                                        ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                                        ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                                         ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                                        ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                                       ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                                       ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                                         ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                                        ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                                          ((uint32_t)0x10000001)
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+#define I2C_EVENT_MASTER_MODE_SELECT                         ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED           ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED              ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10                      ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED                       ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                   ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED                    ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED             ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED          ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED       ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED    ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED           ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED                        ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+#define I2C_EVENT_SLAVE_STOP_DETECTED                        ((uint32_t)0x00000010) /* STOPF flag */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED                     ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING                    ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_ACK_FAILURE                          ((uint32_t)0x00000400) /* AF flag */
+
+void     I2C_DeInit(I2C_TypeDef *I2Cx);
+void     I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
+void     I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
+void     I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
+void     I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void     I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
+uint8_t  I2C_ReceiveData(I2C_TypeDef *I2Cx);
+void     I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
+void     I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
+void     I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert);
+void     I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
+void     I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
+uint8_t  I2C_GetPEC(I2C_TypeDef *I2Cx);
+void     I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
+
+/****************************************************************************************
+ *                         I2C State Monitoring Functions
+ ****************************************************************************************/
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
+uint32_t    I2C_GetLastEvent(I2C_TypeDef *I2Cx);
+FlagStatus  I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+
+void     I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+void     I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_iwdg.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_iwdg.h
new file mode 100644
index 0000000000..0574536344
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_iwdg.h
@@ -0,0 +1,48 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_iwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      IWDG firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_IWDG_H
+#define __CH32V20x_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+
+void       IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void       IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void       IWDG_SetReload(uint16_t Reload);
+void       IWDG_ReloadCounter(void);
+void       IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_misc.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_misc.h
new file mode 100644
index 0000000000..39b0bb6029
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_misc.h
@@ -0,0 +1,43 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_misc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      miscellaneous firmware library functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_MISC_H
+#define __CH32V20x_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* NVIC Init Structure definition */
+typedef struct
+{
+    uint8_t         NVIC_IRQChannel;
+    uint8_t         NVIC_IRQChannelPreemptionPriority;
+    uint8_t         NVIC_IRQChannelSubPriority;
+    FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0    ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1    ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2    ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3    ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4    ((uint32_t)0x04)
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_opa.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_opa.h
new file mode 100644
index 0000000000..336870e093
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_opa.h
@@ -0,0 +1,72 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_opa.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      OPA firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_OPA_H
+#define __CH32V20x_OPA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+#define OPA_PSEL_OFFSET    3
+#define OPA_NSEL_OFFSET    2
+#define OPA_MODE_OFFSET    1
+
+/* OPA member enumeration */
+typedef enum
+{
+    OPA1 = 0,
+    OPA2,
+    OPA3,
+    OPA4
+} OPA_Num_TypeDef;
+
+/* OPA PSEL enumeration */
+typedef enum
+{
+    CHP0 = 0,
+    CHP1
+} OPA_PSEL_TypeDef;
+
+/* OPA NSEL enumeration */
+typedef enum
+{
+    CHN0 = 0,
+    CHN1
+} OPA_NSEL_TypeDef;
+
+/* OPA out channel enumeration */
+typedef enum
+{
+    OUT_IO_OUT0 = 0,
+    OUT_IO_OUT1
+} OPA_Mode_TypeDef;
+
+/* OPA Init Structure definition */
+typedef struct
+{
+    OPA_Num_TypeDef  OPA_NUM; /* Specifies the members of OPA */
+    OPA_PSEL_TypeDef PSEL;    /* Specifies the positive channel of OPA */
+    OPA_NSEL_TypeDef NSEL;    /* Specifies the negative channel of OPA */
+    OPA_Mode_TypeDef Mode;    /* Specifies the mode of OPA */
+} OPA_InitTypeDef;
+
+void OPA_DeInit(void);
+void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
+void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
+void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_pwr.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_pwr.h
new file mode 100644
index 0000000000..ae8c46607a
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_pwr.h
@@ -0,0 +1,62 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_pwr.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the PWR
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_PWR_H
+#define __CH32V20x_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* PVD_detection_level  */
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+
+/* Regulator_state_is_STOP_mode */
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+
+/* STOP_mode_entry */
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+
+/* PWR_Flag */
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+
+void       PWR_DeInit(void);
+void       PWR_BackupAccessCmd(FunctionalState NewState);
+void       PWR_PVDCmd(FunctionalState NewState);
+void       PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void       PWR_WakeUpPinCmd(FunctionalState NewState);
+void       PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void       PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void       PWR_ClearFlag(uint32_t PWR_FLAG);
+void       PWR_EnterSTANDBYMode_RAM(void);
+void       PWR_EnterSTANDBYMode_RAM_LV(void);
+void       PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
+void       PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
+void       PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rcc.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rcc.h
new file mode 100644
index 0000000000..e09d694768
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rcc.h
@@ -0,0 +1,255 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_rcc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_RCC_H
+#define __CH32V20x_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+    uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
+    uint32_t HCLK_Frequency;   /* returns HCLK clock frequency expressed in Hz */
+    uint32_t PCLK1_Frequency;  /* returns PCLK1 clock frequency expressed in Hz */
+    uint32_t PCLK2_Frequency;  /* returns PCLK2 clock frequency expressed in Hz */
+    uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
+} RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                     ((uint32_t)0x00000000)
+#define RCC_HSE_ON                      ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                  ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2          ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE_Div1          ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2          ((uint32_t)0x00030000)
+
+/* PLL_multiplication_factor for other CH32V20x  */
+#define RCC_PLLMul_2                    ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                    ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                    ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                    ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                    ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                    ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                   ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                   ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                   ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                   ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                   ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                   ((uint32_t)0x00380000)
+#define RCC_PLLMul_18                   ((uint32_t)0x003C0000)
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI            ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE            ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK         ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128               ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256               ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512               ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                   ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                   ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                   ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                   ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                  ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                   ((uint8_t)0x01)
+#define RCC_IT_LSERDY                   ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                   ((uint8_t)0x04)
+#define RCC_IT_HSERDY                   ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                   ((uint8_t)0x10)
+#define RCC_IT_CSS                      ((uint8_t)0x80)
+
+/* USB_Device_clock_source */
+#define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div2    ((uint8_t)0x01)
+#define RCC_USBCLKSource_PLLCLK_Div3    ((uint8_t)0x02)
+
+#ifdef CH32V20x_D8W
+  #define RCC_USBCLKSource_PLLCLK_Div5    ((uint8_t)0x03)
+
+#endif
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                 ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                    ((uint8_t)0x00)
+#define RCC_LSE_ON                     ((uint8_t)0x01)
+#define RCC_LSE_Bypass                 ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE           ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI           ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128    ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1             ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2             ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM             ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_CRC              ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC             ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_RNG              ((uint32_t)0x00000200)
+#define RCC_AHBPeriph_SDIO             ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHS            ((uint32_t)0x00000800)
+#define RCC_AHBPeriph_OTG_FS           ((uint32_t)0x00001000)
+
+#ifdef CH32V20x_D8W
+#define RCC_AHBPeriph_BLE_CRC          ((uint32_t)0x00030040)
+#endif
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO            ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA           ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB           ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC           ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD           ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE           ((uint32_t)0x00000040)
+#define RCC_APB2Periph_ADC1            ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2            ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1            ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1            ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8            ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1          ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9            ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10           ((uint32_t)0x00100000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2            ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3            ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4            ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5            ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6            ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7            ((uint32_t)0x00000020)
+#define RCC_APB1Periph_UART6           ((uint32_t)0x00000040)
+#define RCC_APB1Periph_UART7           ((uint32_t)0x00000080)
+#define RCC_APB1Periph_UART8           ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG            ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2            ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3            ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2          ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3          ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4           ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5           ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1            ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2            ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB             ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1            ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2            ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP             ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR             ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC             ((uint32_t)0x20000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                 ((uint8_t)0x04)
+#define RCC_MCO_HSI                    ((uint8_t)0x05)
+#define RCC_MCO_HSE                    ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2            ((uint8_t)0x07)
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST               ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST               ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST               ((uint8_t)0x7F)
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+
+/* USBFS_clock_source */
+#define RCC_USBPLL_Div1                ((uint32_t)0x00)
+#define RCC_USBPLL_Div2                ((uint32_t)0x01)
+#define RCC_USBPLL_Div3                ((uint32_t)0x02)
+#define RCC_USBPLL_Div4                ((uint32_t)0x03)
+#define RCC_USBPLL_Div5                ((uint32_t)0x04)
+#define RCC_USBPLL_Div6                ((uint32_t)0x05)
+#define RCC_USBPLL_Div7                ((uint32_t)0x06)
+#define RCC_USBPLL_Div8                ((uint32_t)0x07)
+
+/* ETH_clock_source */
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+  #define RCC_ETHCLK_Div1    ((uint32_t)0x00)
+  #define RCC_ETHCLK_Div2    ((uint32_t)0x01)
+
+#endif
+
+void        RCC_DeInit(void);
+void        RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void        RCC_HSICmd(FunctionalState NewState);
+void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void        RCC_PLLCmd(FunctionalState NewState);
+void        RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t     RCC_GetSYSCLKSource(void);
+void        RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void        RCC_PCLK1Config(uint32_t RCC_HCLK);
+void        RCC_PCLK2Config(uint32_t RCC_HCLK);
+void        RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void        RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+void        RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void        RCC_LSEConfig(uint8_t RCC_LSE);
+void        RCC_LSICmd(FunctionalState NewState);
+void        RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void        RCC_RTCCLKCmd(FunctionalState NewState);
+void        RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
+void        RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void        RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void        RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void        RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void        RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void        RCC_BackupResetCmd(FunctionalState NewState);
+void        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void        RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus  RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void        RCC_ClearFlag(void);
+ITStatus    RCC_GetITStatus(uint8_t RCC_IT);
+void        RCC_ClearITPendingBit(uint8_t RCC_IT);
+void        RCC_ADCCLKADJcmd(FunctionalState NewState);
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rtc.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rtc.h
new file mode 100644
index 0000000000..0b32654801
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_rtc.h
@@ -0,0 +1,96 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_rtc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the RTC
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_RTC_H
+#define __CH32V20x_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+typedef enum
+{
+    Level_32 = 2,
+    Level_64,
+    Level_128,
+
+} Cali_LevelTypeDef;
+
+/* RTC_interrupts_define */
+#define RTC_IT_OW         ((uint16_t)0x0004) /* Overflow interrupt */
+#define RTC_IT_ALR        ((uint16_t)0x0002) /* Alarm interrupt */
+#define RTC_IT_SEC        ((uint16_t)0x0001) /* Second interrupt */
+
+/* RTC_interrupts_flags */
+#define RTC_FLAG_RTOFF    ((uint16_t)0x0020) /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF      ((uint16_t)0x0008) /* Registers Synchronized flag */
+#define RTC_FLAG_OW       ((uint16_t)0x0004) /* Overflow flag */
+#define RTC_FLAG_ALR      ((uint16_t)0x0002) /* Alarm flag */
+#define RTC_FLAG_SEC      ((uint16_t)0x0001) /* Second flag */
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+#define RB_OSC32K_HTUNE       (0x1FE0)
+#define RB_OSC32K_LTUNE       (0x1F)
+
+#define RB_OSC_CAL_HALT       (0x80)
+#define RB_OSC_CAL_EN         (0x02)
+#define RB_OSC_CAL_INT_EN     (0x01)
+
+#define RB_OSC_CAL_OV_CNT     (0xFF)
+
+#define RB_OSC_CAL_IF_END     (1 << 15)
+#define RB_OSC_CAL_CNT_OV     (1 << 14)
+#define RB_OSC_CAL_CNT        (0x3FFF)
+
+#define RB_CAL_LP_EN          (1 << 6)
+#define RB_CAL_WKUP_EN        (1 << 5)
+#define RB_OSC_HALT_MD        (1 << 4)
+#define RB_OSC_CNT_VLU        (0x0F)
+
+
+#ifdef CLK_OSC32K
+#if ( CLK_OSC32K == 1 )
+#define CAB_LSIFQ       32000
+#else
+#define CAB_LSIFQ       32768
+#endif
+#else
+#define CAB_LSIFQ       32000
+#endif
+#endif
+
+
+void       RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void       RTC_EnterConfigMode(void);
+void       RTC_ExitConfigMode(void);
+uint32_t   RTC_GetCounter(void);
+void       RTC_SetCounter(uint32_t CounterValue);
+void       RTC_SetPrescaler(uint32_t PrescalerValue);
+void       RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t   RTC_GetDivider(void);
+void       RTC_WaitForLastTask(void);
+void       RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void       RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus   RTC_GetITStatus(uint16_t RTC_IT);
+void       RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+void Calibration_LSI(Cali_LevelTypeDef cali_Lv);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_spi.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_spi.h
new file mode 100644
index 0000000000..dfa5f9e7df
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_spi.h
@@ -0,0 +1,218 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_spi.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      SPI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_SPI_H
+#define __CH32V20x_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* SPI Init structure definition */
+typedef struct
+{
+    uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
+                               This parameter can be a value of @ref SPI_data_direction */
+
+    uint16_t SPI_Mode; /* Specifies the SPI operating mode.
+                          This parameter can be a value of @ref SPI_mode */
+
+    uint16_t SPI_DataSize; /* Specifies the SPI data size.
+                              This parameter can be a value of @ref SPI_data_size */
+
+    uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
+                          This parameter can be a value of @ref SPI_Clock_Polarity */
+
+    uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
+                          This parameter can be a value of @ref SPI_Clock_Phase */
+
+    uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
+                         hardware (NSS pin) or by software using the SSI bit.
+                         This parameter can be a value of @ref SPI_Slave_Select_management */
+
+    uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
+                                       used to configure the transmit and receive SCK clock.
+                                       This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                       @note The communication clock is derived from the master
+                                             clock. The slave clock does not need to be set. */
+
+    uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
+                              This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+    uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
+} SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+    uint16_t I2S_Mode; /* Specifies the I2S operating mode.
+                          This parameter can be a value of @ref I2S_Mode */
+
+    uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
+                              This parameter can be a value of @ref I2S_Standard */
+
+    uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
+                                This parameter can be a value of @ref I2S_Data_Format */
+
+    uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
+                                This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
+                               This parameter can be a value of @ref I2S_Audio_Frequency */
+
+    uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
+                          This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitTypeDef;
+
+/* SPI_data_direction */
+#define SPI_Direction_2Lines_FullDuplex    ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly        ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx             ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx             ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master                    ((uint16_t)0x0104)
+#define SPI_Mode_Slave                     ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b                   ((uint16_t)0x0800)
+#define SPI_DataSize_8b                    ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low                       ((uint16_t)0x0000)
+#define SPI_CPOL_High                      ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge                     ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                     ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft                       ((uint16_t)0x0200)
+#define SPI_NSS_Hard                       ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2            ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4            ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8            ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16           ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32           ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64           ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128          ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256          ((uint16_t)0x0038)
+
+/* SPI_MSB_LSB_transmission */
+#define SPI_FirstBit_MSB                   ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                   ((uint16_t)0x0080)
+
+/* I2S_Mode */
+#define I2S_Mode_SlaveTx                   ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                   ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx                  ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx                  ((uint16_t)0x0300)
+
+/* I2S_Standard */
+#define I2S_Standard_Phillips              ((uint16_t)0x0000)
+#define I2S_Standard_MSB                   ((uint16_t)0x0010)
+#define I2S_Standard_LSB                   ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort              ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong               ((uint16_t)0x00B0)
+
+/* I2S_Data_Format */
+#define I2S_DataFormat_16b                 ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended         ((uint16_t)0x0001)
+#define I2S_DataFormat_24b                 ((uint16_t)0x0003)
+#define I2S_DataFormat_32b                 ((uint16_t)0x0005)
+
+/* I2S_MCLK_Output */
+#define I2S_MCLKOutput_Enable              ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable             ((uint16_t)0x0000)
+
+/* I2S_Audio_Frequency */
+#define I2S_AudioFreq_192k                 ((uint32_t)192000)
+#define I2S_AudioFreq_96k                  ((uint32_t)96000)
+#define I2S_AudioFreq_48k                  ((uint32_t)48000)
+#define I2S_AudioFreq_44k                  ((uint32_t)44100)
+#define I2S_AudioFreq_32k                  ((uint32_t)32000)
+#define I2S_AudioFreq_22k                  ((uint32_t)22050)
+#define I2S_AudioFreq_16k                  ((uint32_t)16000)
+#define I2S_AudioFreq_11k                  ((uint32_t)11025)
+#define I2S_AudioFreq_8k                   ((uint32_t)8000)
+#define I2S_AudioFreq_Default              ((uint32_t)2)
+
+/* I2S_Clock_Polarity */
+#define I2S_CPOL_Low                       ((uint16_t)0x0000)
+#define I2S_CPOL_High                      ((uint16_t)0x0008)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx                  ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx                  ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set            ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset          ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx                         ((uint8_t)0x00)
+#define SPI_CRC_Rx                         ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx                   ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                   ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE                     ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                    ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                     ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR                     ((uint8_t)0x56)
+#define SPI_IT_MODF                        ((uint8_t)0x55)
+#define SPI_IT_CRCERR                      ((uint8_t)0x54)
+#define I2S_IT_UDR                         ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE                  ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                   ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                    ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                       ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                    ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                      ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                   ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                   ((uint16_t)0x0080)
+
+void       SPI_I2S_DeInit(SPI_TypeDef *SPIx);
+void       SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
+void       I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
+void       SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
+void       I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
+void       SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void       SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void       SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
+uint16_t   SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
+void       SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
+void       SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
+void       SPI_TransmitCRC(SPI_TypeDef *SPIx);
+void       SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
+uint16_t   SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
+uint16_t   SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
+void       SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
+void       SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus   SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
+void       SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_tim.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_tim.h
new file mode 100644
index 0000000000..64821f7a6d
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_tim.h
@@ -0,0 +1,506 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_tim.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      TIM firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_TIM_H
+#define __CH32V20x_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+    uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
+                               This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t TIM_CounterMode; /* Specifies the counter mode.
+                                 This parameter can be a value of @ref TIM_Counter_Mode */
+
+    uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
+                            Auto-Reload Register at the next update event.
+                            This parameter must be a number between 0x0000 and 0xFFFF.  */
+
+    uint16_t TIM_ClockDivision; /* Specifies the clock division.
+                                  This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+    uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
+                                      reaches zero, an update event is generated and counting restarts
+                                      from the RCR value (N).
+                                      This means in PWM mode that (N+1) corresponds to:
+                                         - the number of PWM periods in edge-aligned mode
+                                         - the number of half PWM period in center-aligned mode
+                                      This parameter must be a number between 0x00 and 0xFF.
+                                      @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+    uint16_t TIM_OCMode; /* Specifies the TIM mode.
+                            This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+    uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_state */
+
+    uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
+                                  This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                  @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
+                           This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t TIM_OCPolarity; /* Specifies the output polarity.
+                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+    uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
+                                  This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                  @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+    uint16_t TIM_Channel; /* Specifies the TIM channel.
+                             This parameter can be a value of @ref TIM_Channel */
+
+    uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
+                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+    uint16_t TIM_ICSelection; /* Specifies the input.
+                                 This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+    uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
+                                 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+    uint16_t TIM_ICFilter; /* Specifies the input capture filter.
+                              This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+    uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
+                               This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+    uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
+                               This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+    uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
+                               This parameter can be a value of @ref Lock_level */
+
+    uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
+                              switching-on of the outputs.
+                              This parameter can be a number between 0x00 and 0xFF  */
+
+    uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
+                           This parameter can be a value of @ref Break_Input_enable_disable */
+
+    uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
+                                   This parameter can be a value of @ref Break_Polarity */
+
+    uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
+                                     This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable                     ((uint16_t)0x0001)
+#define TIM_CCx_Disable                    ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable                    ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                   ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define TIM_ICPolarity_Rising              ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling             ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge            ((uint16_t)0x000A)
+
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
+                                                                 connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
+                                                                 connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer       ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers      ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers      ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers      ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers      ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers      ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers      ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers      ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers      ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers     ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers     ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers     ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers     ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers     ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers     ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers     ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers     ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers     ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
+                                                                 or the setting of UG bit, or an update generation  \
+                                                                 through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+
+void       TIM_DeInit(TIM_TypeDef *TIMx);
+void       TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+void       TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void       TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+void       TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void       TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void       TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
+void       TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void       TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void       TIM_InternalClockConfig(TIM_TypeDef *TIMx);
+void       TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
+void       TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                      uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void       TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                                   uint16_t ExtTRGFilter);
+void       TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
+                                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void       TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                         uint16_t ExtTRGFilter);
+void       TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void       TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
+void       TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
+void       TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
+                                      uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void       TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void       TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void       TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void       TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
+void       TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
+void       TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
+void       TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
+void       TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
+void       TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
+void       TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
+void       TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
+void       TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
+void       TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
+void       TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
+void       TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
+uint16_t   TIM_GetCapture1(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture2(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture3(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture4(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCounter(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetPrescaler(TIM_TypeDef *TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
+void       TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
+ITStatus   TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
+void       TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_usart.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_usart.h
new file mode 100644
index 0000000000..1211381452
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_usart.h
@@ -0,0 +1,185 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_usart.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      USART firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_USART_H
+#define __CH32V20x_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* USART Init Structure definition */
+typedef struct
+{
+    uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
+                                The baud rate is computed using the following formula:
+                                 - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                 - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+    uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
+                                  This parameter can be a value of @ref USART_Word_Length */
+
+    uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
+                                This parameter can be a value of @ref USART_Stop_Bits */
+
+    uint16_t USART_Parity; /* Specifies the parity mode.
+                              This parameter can be a value of @ref USART_Parity
+                              @note When parity is enabled, the computed parity is inserted
+                                    at the MSB position of the transmitted data (9th bit when
+                                    the word length is set to 9 data bits; 8th bit when the
+                                    word length is set to 8 data bits). */
+
+    uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                            This parameter can be a value of @ref USART_Mode */
+
+    uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */
+typedef struct
+{
+    uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+    uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
+                            This parameter can be a value of @ref USART_Clock_Polarity */
+
+    uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
+                            This parameter can be a value of @ref USART_Clock_Phase */
+
+    uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+
+/* USART_Stop_Bits */
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600)
+
+/* USART_Mode */
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                         USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+void       USART_DeInit(USART_TypeDef *USARTx);
+void       USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
+void       USART_StructInit(USART_InitTypeDef *USART_InitStruct);
+void       USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
+void       USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
+void       USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
+void       USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void       USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
+void       USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
+void       USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
+void       USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
+uint16_t   USART_ReceiveData(USART_TypeDef *USARTx);
+void       USART_SendBreak(USART_TypeDef *USARTx);
+void       USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
+void       USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
+void       USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
+void       USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+void       USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+ITStatus   USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
+void       USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_wwdg.h b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_wwdg.h
new file mode 100644
index 0000000000..5cbcbce146
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x_wwdg.h
@@ -0,0 +1,39 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_wwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the WWDG
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V20x_WWDG_H
+#define __CH32V20x_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* WWDG_Prescaler */
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+
+void       WWDG_DeInit(void);
+void       WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void       WWDG_SetWindowValue(uint8_t WindowValue);
+void       WWDG_EnableIT(void);
+void       WWDG_SetCounter(uint8_t Counter);
+void       WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void       WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_adc.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_adc.c
new file mode 100644
index 0000000000..3d794583e6
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_adc.c
@@ -0,0 +1,1208 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_adc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the ADC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_adc.h"
+#include "ch32v20x_rcc.h"
+
+/* ADC DISCNUM mask */
+#define CTLR1_DISCNUM_Reset              ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CTLR1_DISCEN_Set                 ((uint32_t)0x00000800)
+#define CTLR1_DISCEN_Reset               ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CTLR1_JAUTO_Set                  ((uint32_t)0x00000400)
+#define CTLR1_JAUTO_Reset                ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CTLR1_JDISCEN_Set                ((uint32_t)0x00001000)
+#define CTLR1_JDISCEN_Reset              ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CTLR1_AWDCH_Reset                ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTLR1_AWDMode_Reset              ((uint32_t)0xFF3FFDFF)
+
+/* CTLR1 register Mask */
+#define CTLR1_CLEAR_Mask                 ((uint32_t)0xE0F0FEFF)
+
+/* ADC ADON mask */
+#define CTLR2_ADON_Set                   ((uint32_t)0x00000001)
+#define CTLR2_ADON_Reset                 ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTLR2_DMA_Set                    ((uint32_t)0x00000100)
+#define CTLR2_DMA_Reset                  ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CTLR2_RSTCAL_Set                 ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTLR2_CAL_Set                    ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CTLR2_SWSTART_Set                ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CTLR2_EXTTRIG_Set                ((uint32_t)0x00100000)
+#define CTLR2_EXTTRIG_Reset              ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTLR2_EXTTRIG_SWSTART_Set        ((uint32_t)0x00500000)
+#define CTLR2_EXTTRIG_SWSTART_Reset      ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CTLR2_JEXTSEL_Reset              ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CTLR2_JEXTTRIG_Set               ((uint32_t)0x00008000)
+#define CTLR2_JEXTTRIG_Reset             ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CTLR2_JSWSTART_Set               ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTLR2_JEXTTRIG_JSWSTART_Set      ((uint32_t)0x00208000)
+#define CTLR2_JEXTTRIG_JSWSTART_Reset    ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTLR2_TSVREFE_Set                ((uint32_t)0x00800000)
+#define CTLR2_TSVREFE_Reset              ((uint32_t)0xFF7FFFFF)
+
+/* CTLR2 register Mask */
+#define CTLR2_CLEAR_Mask                 ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define RSQR3_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR2_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR1_SQ_Set                     ((uint32_t)0x0000001F)
+
+/* RSQR1 register Mask */
+#define RSQR1_CLEAR_Mask                 ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define ISQR_JSQ_Set                     ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define ISQR_JL_Set                      ((uint32_t)0x00300000)
+#define ISQR_JL_Reset                    ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SAMPTR1_SMP_Set                  ((uint32_t)0x00000007)
+#define SAMPTR2_SMP_Set                  ((uint32_t)0x00000007)
+
+/* ADC IDATARx registers offset */
+#define IDATAR_Offset                    ((uint8_t)0x28)
+
+/* ADC1 RDATAR register base address */
+#define RDATAR_ADDRESS                   ((uint32_t)0x4001244C)
+
+/*********************************************************************
+ * @fn      ADC_DeInit
+ *
+ * @brief   Deinitializes the ADCx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    if(ADCx == ADC1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+    }
+    else if(ADCx == ADC2)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_Init
+ *
+ * @brief   Initializes the ADCx peripheral according to the specified
+ *        parameters in the ADC_InitStruct.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    uint32_t tmpreg1 = 0;
+    uint8_t  tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer |
+                          (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+    ADCx->CTLR1 = tmpreg1;
+
+    tmpreg1 = ADCx->CTLR2;
+    tmpreg1 &= CTLR2_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+                          ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+    ADCx->CTLR2 = tmpreg1;
+
+    tmpreg1 = ADCx->RSQR1;
+    tmpreg1 &= RSQR1_CLEAR_Mask;
+    tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+    tmpreg1 |= (uint32_t)tmpreg2 << 20;
+    ADCx->RSQR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_StructInit
+ *
+ * @brief   Fills each ADC_InitStruct member with its default value.
+ *
+ * @param   ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+    ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+    ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+    ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+    ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+    ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/*********************************************************************
+ * @fn      ADC_Cmd
+ *
+ * @brief   Enables or disables the specified ADC peripheral.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_ADON_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_ADON_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_DMACmd
+ *
+ * @brief   Enables or disables the specified ADC DMA request.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_DMA_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_DMA_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ITConfig
+ *
+ * @brief   Enables or disables the specified ADC interrupts.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt sources to be enabled or disabled.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)ADC_IT;
+
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= itmask;
+    }
+    else
+    {
+        ADCx->CTLR1 &= (~(uint32_t)itmask);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ResetCalibration
+ *
+ * @brief   Resets the selected ADC calibration registers.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_ResetCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_RSTCAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetResetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC reset calibration registers status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_StartCalibration
+ *
+ * @brief   Starts the selected ADC calibration process.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  None
+ */
+void ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_CAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC calibration status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartConvCmd
+ *
+ * @brief   Enables or disables the selected ADC software start conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartConvStatus
+ *
+ * @brief   Gets the selected ADC Software start conversion Status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeChannelCountConfig
+ *
+ * @brief   Configures the discontinuous mode for the selected ADC regular
+ *        group channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          Number - specifies the discontinuous mode regular channel
+ *            count value(1-8).
+ *
+ * @return  None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_DISCNUM_Reset;
+    tmpreg2 = Number - 1;
+    tmpreg1 |= tmpreg2 << 13;
+    ADCx->CTLR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode on regular group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_DISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_DISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_RegularChannelConfig
+ *
+ * @brief   Configures for the selected ADC regular channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 16.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    if(Rank < 7)
+    {
+        tmpreg1 = ADCx->RSQR3;
+        tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR3 = tmpreg1;
+    }
+    else if(Rank < 13)
+    {
+        tmpreg1 = ADCx->RSQR2;
+        tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR2 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->RSQR1;
+        tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR1 = tmpreg1;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigConvCmd
+ *
+ * @brief   Enables or disables the ADCx conversion through external trigger.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetConversionValue
+ *
+ * @brief   Returns the last ADCx conversion result data for regular channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  ADCx->RDATAR - The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
+{
+    return (uint16_t)ADCx->RDATAR;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetDualModeConversionValue
+ *
+ * @brief   Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ *
+ * @return  RDATAR_ADDRESS - The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+    return (*(__IO uint32_t *)RDATAR_ADDRESS);
+}
+
+/*********************************************************************
+ * @fn      ADC_AutoInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC automatic injected group
+ *        conversion after regular one.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JAUTO_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JAUTO_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedDiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode for injected group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JDISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JDISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvConfig
+ *
+ * @brief   Configures the ADCx external trigger for injected channels conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_ExternalTrigInjecConv - specifies the ADC trigger to start
+ *        injected conversion.
+ *            ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected.
+ *            ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt
+ *        line 15 event selected.
+ *            ADC_ExternalTrigInjecConv_None: Injected conversion started
+ *        by software and not by external trigger.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR2;
+    tmpreg &= CTLR2_JEXTSEL_Reset;
+    tmpreg |= ADC_ExternalTrigInjecConv;
+    ADCx->CTLR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvCmd
+ *
+ * @brief   Enables or disables the ADCx injected channels conversion through
+ *        external trigger.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC start of the injected
+ *        channels conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartInjectedConvCmdStatus
+ *
+ * @brief   Gets the selected ADC Software start injected conversion Status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedChannelConfig
+ *
+ * @brief   Configures for the selected ADC injected channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 4.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20;
+    tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 &= ~tmpreg2;
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 |= tmpreg2;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedSequencerLengthConfig
+ *
+ * @brief   Configures the sequencer length for injected channels.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          Length - The sequencer length.
+ *            This parameter must be a number between 1 to 4.
+ *
+ * @return  None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg1 &= ISQR_JL_Reset;
+    tmpreg2 = Length - 1;
+    tmpreg1 |= tmpreg2 << 20;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_SetInjectedOffset
+ *
+ * @brief   Set the injected channels conversion value offset.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InjectedChannel: the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *          Offset - the offset value for the selected ADC injected channel.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel;
+
+    *(__IO uint32_t *)tmp = (uint32_t)Offset;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetInjectedConversionValue
+ *
+ * @brief   Returns the ADC injected channel conversion result.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InjectedChannel - the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *
+ * @return  tmp - The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel + IDATAR_Offset;
+
+    return (uint16_t)(*(__IO uint32_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogCmd
+ *
+ * @brief   Enables or disables the analog watchdog on single/all regular
+ *        or injected channels.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_AnalogWatchdog - the ADC analog watchdog configuration.
+ *            ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a
+ *        single regular channel.
+ *            ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a
+ *        single injected channel.
+ *            ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog
+ *        on a single regular or injected channel.
+ *            ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on  all
+ *        regular channel.
+ *            ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on  all
+ *        injected channel.
+ *            ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on
+ *        all regular and injected channels.
+ *            ADC_AnalogWatchdog_None - No channel guarded by the analog
+ *        watchdog.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDMode_Reset;
+    tmpreg |= ADC_AnalogWatchdog;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogThresholdsConfig
+ *
+ * @brief   Configures the high and low thresholds of the analog watchdog.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          HighThreshold - the ADC analog watchdog High threshold value.
+ *            This parameter must be a 12bit value.
+ *          LowThreshold - the ADC analog watchdog Low threshold value.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+    ADCx->WDHTR = HighThreshold;
+    ADCx->WDLTR = LowThreshold;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogSingleChannelConfig
+ *
+ * @brief   Configures the analog watchdog guarded single channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *
+ * @return  None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDCH_Reset;
+    tmpreg |= ADC_Channel;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_TempSensorVrefintCmd
+ *
+ * @brief   Enables or disables the temperature sensor and Vrefint channel.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADC1->CTLR2 |= CTLR2_TSVREFE_Set;
+    }
+    else
+    {
+        ADC1->CTLR2 &= CTLR2_TSVREFE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified ADC flag is set or not.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to check.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearFlag
+ *
+ * @brief   Clears the ADCx's pending flags.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to clear.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  none
+ */
+void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    ADCx->STATR = ~(uint32_t)ADC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetITStatus
+ *
+ * @brief   Checks whether the specified ADC interrupt has occurred or not.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt source to check.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t itmask = 0, enablestatus = 0;
+
+    itmask = ADC_IT >> 8;
+    enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT);
+
+    if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearITPendingBit
+ *
+ * @brief   Clears the ADCx's interrupt pending bits.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt pending bit to clear.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  none
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)(ADC_IT >> 8);
+    ADCx->STATR = ~(uint32_t)itmask;
+}
+
+/*********************************************************************
+ * @fn      TempSensor_Volt_To_Temper
+ *
+ * @brief   Internal Temperature Sensor Voltage to temperature.
+ *
+ * @param   Value - Voltage Value(mv).
+ *
+ * @return  Temper - Temperature Value.
+ */
+s32 TempSensor_Volt_To_Temper(s32 Value)
+{
+    s32 Temper, Refer_Volt, Refer_Temper;
+    s32 k = 43;
+
+    Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF);
+    Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF);
+
+    Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k;
+
+    return Temper;
+}
+
+/*********************************************************************
+ * @fn      ADC_BufferCmd
+ *
+ * @brief   Enables or disables the ADCx buffer.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= (1 << 26);
+    }
+    else
+    {
+        ADCx->CTLR1 &= ~(1 << 26);
+    }
+}
+
+/*********************************************************************
+ * @fn      Get_CalibrationValue
+ *
+ * @brief   Get ADCx Calibration Value.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  CalibrationValue
+ */
+int16_t Get_CalibrationValue(ADC_TypeDef *ADCx)
+{
+    __IO uint8_t  i, j;
+    uint16_t      buf[10];
+    __IO uint16_t t;
+#if defined (CH32V20x_D6)
+    __IO uint16_t p;
+#endif
+
+    for(i = 0; i < 10; i++){
+        ADC_ResetCalibration(ADCx);
+        while(ADC_GetResetCalibrationStatus(ADCx));
+        ADC_StartCalibration(ADCx);
+        while(ADC_GetCalibrationStatus(ADCx));
+        buf[i] = ADCx->RDATAR;
+    }
+
+    for(i = 0; i < 10; i++){
+        for(j = 0; j < 9; j++){
+            if(buf[j] > buf[j + 1])
+            {
+                t = buf[j];
+                buf[j] = buf[j + 1];
+                buf[j + 1] = t;
+            }
+        }
+    }
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    t = 0;
+    for( i = 0; i < 6; i++ ) {
+        t += buf[i + 2];
+    }
+
+    t = ( t / 6 ) + ( ( t % 6 ) / 3 );
+
+    return ( int16_t )( 2048 - ( int16_t )t );
+#else
+    t = 0;
+    p = 0;
+    /* 1024 */
+    for(i = 0; i < 6; i++ ){
+            if(buf[i+2] > 1536) break;
+            t += buf[i+2];
+    }
+
+    if(i > 0){
+            t = ( t / i ) + ( (( t % i )*2) / i );
+    }
+    else t = 1024;
+
+    /* 2048 */
+    j = 6-i;
+    if(j > 0){
+        for(; i < 6; i++ ){
+                p += buf[i+2];
+        }
+
+        p = ( p / j ) + ( (( p % j )*2) / j );
+    }
+    else p = 2048;
+
+    return ( int16_t )(((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))/2) + ((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))%2));
+
+
+#endif
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_bkp.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_bkp.c
new file mode 100644
index 0000000000..c21e23e39b
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_bkp.c
@@ -0,0 +1,242 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_bkp.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the BKP firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_rcc.h"
+
+/* BKP registers bit mask */
+
+/* OCTLR register bit mask */
+#define OCTLR_CAL_MASK    ((uint16_t)0xFF80)
+#define OCTLR_MASK        ((uint16_t)0xFC7F)
+
+/*********************************************************************
+ * @fn      BKP_DeInit
+ *
+ * @brief   Deinitializes the BKP peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinLevelConfig
+ *
+ * @brief   Configures the Tamper Pin active level.
+ *
+ * @param   BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ *            BKP_TamperPinLevel_High - Tamper pin active on high level.
+ *            BKP_TamperPinLevel_Low - Tamper pin active on low level.
+ *
+ * @return  none
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+    if(BKP_TamperPinLevel)
+    {
+        BKP->TPCTLR |= (1 << 1);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 1);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinCmd
+ *
+ * @brief   Enables or disables the Tamper Pin activation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCTLR |= (1 << 0);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ITConfig
+ *
+ * @brief   Enables or disables the Tamper Pin Interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCSR |= (1 << 2);
+    }
+    else
+    {
+        BKP->TPCSR &= ~(1 << 2);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_RTCOutputConfig
+ *
+ * @brief   Select the RTC output source to output on the Tamper pin.
+ *
+ * @param   BKP_RTCOutputSource - specifies the RTC output source.
+ *            BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
+ *            BKP_RTCOutputSource_CalibClock - output the RTC clock with
+ *        frequency divided by 64 on the Tamper pin.
+ *            BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
+ *        on the Tamper pin.
+ *            BKP_RTCOutputSource_Second - output the RTC Second pulse
+ *        signal on the Tamper pin.
+ *
+ * @return  none
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_MASK;
+    tmpreg |= BKP_RTCOutputSource;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_SetRTCCalibrationValue
+ *
+ * @brief   Sets RTC Clock Calibration value.
+ *
+ * @param   CalibrationValue - specifies the RTC Clock Calibration value.
+ *            This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_CAL_MASK;
+    tmpreg |= CalibrationValue;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_WriteBackupRegister
+ *
+ * @brief   Writes user data to the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *          Data - data to write.
+ *
+ * @return  none
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      BKP_ReadBackupRegister
+ *
+ * @brief   Reads data from the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *            This parameter can be BKP_DRx where x=[1, 42].
+ *
+ * @return  none
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      BKP_GetFlagStatus
+ *
+ * @brief   Checks whether the Tamper Pin Event flag is set or not.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+    if(BKP->TPCSR & (1 << 8))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearFlag
+ *
+ * @brief   Clears Tamper Pin Event pending flag.
+ *
+ * @return  none
+ */
+void BKP_ClearFlag(void)
+{
+    BKP->TPCSR |= BKP_CTE;
+}
+
+/*********************************************************************
+ * @fn      BKP_GetITStatus
+ *
+ * @brief   Checks whether the Tamper Pin Interrupt has occurred or not.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus BKP_GetITStatus(void)
+{
+    if(BKP->TPCSR & (1 << 9))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearITPendingBit
+ *
+ * @brief   Clears Tamper Pin Interrupt pending bit.
+ *
+ * @return  none
+ */
+void BKP_ClearITPendingBit(void)
+{
+    BKP->TPCSR |= BKP_CTI;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_can.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_can.c
new file mode 100644
index 0000000000..b255de13b7
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_can.c
@@ -0,0 +1,1228 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_can.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the CAN firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_can.h"
+#include "ch32v20x_rcc.h"
+
+/* CAN CTLR Register bits */
+#define CTLR_DBF                     ((uint32_t)0x00010000) 
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ                  ((uint32_t)0x00000001) 
+
+/* CAN FCTLR Register bits */
+#define FCTLR_FINIT                  ((uint32_t)0x00000001) 
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT                 ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT                 ((uint32_t)0x0000FFFF)
+
+
+/* Flags in TSTATR register */
+#define CAN_FLAGS_TSTATR             ((uint32_t)0x08000000) 
+/* Flags in RFIFO1 register */
+#define CAN_FLAGS_RFIFO1             ((uint32_t)0x04000000) 
+/* Flags in RFIFO0 register */
+#define CAN_FLAGS_RFIFO0             ((uint32_t)0x02000000) 
+/* Flags in STATR register */
+#define CAN_FLAGS_STATR              ((uint32_t)0x01000000) 
+/* Flags in ERRSR register */
+#define CAN_FLAGS_ERRSR              ((uint32_t)0x00F00000) 
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0              ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1              ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2              ((uint8_t)0x02) 
+
+
+#define CAN_MODE_MASK                ((uint32_t) 0x00000003)
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+
+/*********************************************************************
+ * @fn      CAN_DeInit
+ *
+ * @brief   Deinitializes the CAN peripheral registers to their default reset
+ *        values.
+ *
+ * @param   CANx - where x can be 1 or 2 to select the CAN peripheral.
+ *
+ * @return  none
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+  if (CANx == CAN1)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+  }
+  else
+  {  
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_Init
+ *
+ * @brief   Initializes the CAN peripheral according to the specified
+ *        parameters in the CAN_InitStruct.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_InitStruct - pointer to a CAN_InitTypeDef structure that
+ *        contains the configuration information for the CAN peripheral.
+ *
+ * @return  InitStatus - CAN InitStatus state.
+*             CAN_InitStatus_Failed.
+*             CAN_InitStatus_Success.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+
+  CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP);
+  CANx->CTLR |= CAN_CTLR_INRQ ;
+
+  while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else 
+  {
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_TTCM;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM;
+    }
+
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_ABOM;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM;
+    }
+
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_AWUM;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM;
+    }
+
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_NART;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART;
+    }
+
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_RFLM;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM;
+    }
+
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CANx->CTLR |= CAN_CTLR_TXFP;
+    }
+    else
+    {
+      CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP;
+    }
+
+    CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+                ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+    CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ;
+    wait_ack = 0;
+
+    while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT))
+    {
+      wait_ack++;
+    }
+
+    if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  return InitStatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_FilterInit
+ *
+ * @brief   Initializes the CAN peripheral according to the specified
+ *        parameters in the CAN_FilterInitStruct.
+ *
+ * @param   CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef
+ *        structure that contains the configuration information.
+ *
+ * @return  none
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+  CAN1->FCTLR |= FCTLR_FINIT;
+  CAN1->FWR &= ~(uint32_t)filter_number_bit_pos;
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos;
+		
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+		
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    CAN1->FSCFGR |= filter_number_bit_pos;
+    
+		CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    
+		CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+  }
+
+#if defined (CH32V20x_D6)
+  if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0)
+  {
+    uint32_t i;
+
+    for(i = 0; i < 64; i++){
+        *(__IO uint16_t *)(0x40006000 + 512 + 4 * i) = *(__IO uint16_t *)(0x40006000 + 768 + 4 * i);
+    }
+  }
+
+#endif
+
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else 
+  {
+    CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos;
+  }
+  
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN1->FWR |= filter_number_bit_pos;
+  }
+
+  CAN1->FCTLR &= ~FCTLR_FINIT;
+}
+
+/*********************************************************************
+ * @fn      CAN_StructInit
+ *
+ * @brief   Fills each CAN_InitStruct member with its default value.
+ *
+ * @param   CAN_InitStruct - pointer to a CAN_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+  CAN_InitStruct->CAN_NART = DISABLE;
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/*********************************************************************
+ * @fn      CAN_SlaveStartBank
+ *
+ * @brief   This function applies only to CH32 Connectivity line devices.
+ *
+ * @param   CAN_BankNumber - Select the start slave bank filter from 1..27.
+ *
+ * @return  none
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
+  CAN1->FCTLR |= FCTLR_FINIT;
+  CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ;
+  CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8;
+  CAN1->FCTLR &= ~FCTLR_FINIT;
+}
+
+/*********************************************************************
+ * @fn      CAN_DBGFreeze
+ *
+ * @brief   Enables or disables the DBG Freeze for CAN.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    CANx->CTLR |= CTLR_DBF;
+  }
+  else
+  {
+    CANx->CTLR &= ~CTLR_DBF;
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_TTComModeCmd
+ *
+ * @brief   Enables or disabes the CAN Time TriggerOperation communication mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    CANx->CTLR |= CAN_CTLR_TTCM;
+
+    CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT);
+    CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT);
+    CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT);
+  }
+  else
+  {
+    CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM);
+
+    CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT);
+    CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT);
+    CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT);
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_Transmit
+ *
+ * @brief   Initiates the transmission of a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          TxMessage - pointer to a structure which contains CAN Id, CAN
+ *        DLC and CAN data.
+ *
+ * @return  transmit_mailbox - The number of the mailbox that is used for
+ *        transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+
+  if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ;
+    if (TxMessage->IDE == CAN_Id_Standard)
+    {
+      CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \
+                                                  TxMessage->RTR);
+    }
+    else
+    {
+      CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \
+                                                  TxMessage->IDE | \
+                                                  TxMessage->RTR);
+    }
+    
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0;
+    CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC;
+
+    CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
+    CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
+                                             ((uint32_t)TxMessage->Data[4]));
+    CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ;
+  }
+	
+  return transmit_mailbox;
+}
+
+/*********************************************************************
+ * @fn      CAN_TransmitStatus
+ *
+ * @brief   Checks the transmission of a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          TransmitMailbox - the number of the mailbox that is used for
+ *        transmission.
+ *
+ * @return  state -
+ *            CAN_TxStatus_Ok.
+ *            CAN_TxStatus_Failed.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  switch (TransmitMailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSTATR &  (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0);
+      break;
+		
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSTATR &  (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1);
+      break;
+		
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSTATR &  (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2);
+      break;
+		
+    default:
+      state = CAN_TxStatus_Failed;
+      break;
+  }
+	
+  switch (state)
+  {
+    case (0x0): 
+			state = CAN_TxStatus_Pending;
+      break;
+		
+     case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): 
+			state = CAN_TxStatus_Failed;
+      break;
+		
+     case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): 
+			state = CAN_TxStatus_Failed;
+      break;
+		
+     case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2):
+			state = CAN_TxStatus_Failed;
+      break;
+		
+    case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0):
+			state = CAN_TxStatus_Ok;
+      break;
+		
+    case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1):
+			state = CAN_TxStatus_Ok;
+      break;
+		
+    case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2):
+			state = CAN_TxStatus_Ok;
+      break;
+		
+    default: 
+			state = CAN_TxStatus_Failed;
+      break;
+  }
+	
+  return (uint8_t) state;
+}
+
+/*********************************************************************
+ * @fn      CAN_CancelTransmit
+ *
+ * @brief   Cancels a transmit request.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          Mailbox -  Mailbox number.
+ *            CAN_TXMAILBOX_0.
+ *            CAN_TXMAILBOX_1.
+ *            CAN_TXMAILBOX_2.
+ *
+ * @return  none
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+  switch (Mailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+			CANx->TSTATR |= CAN_TSTATR_ABRQ0;
+      break;
+		
+    case (CAN_TXMAILBOX_1): 
+			CANx->TSTATR |= CAN_TSTATR_ABRQ1;
+      break;
+		
+    case (CAN_TXMAILBOX_2): 
+			CANx->TSTATR |= CAN_TSTATR_ABRQ2;
+      break;
+		
+    default:
+      break;
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_Receive
+ *
+ * @brief   Receives a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *          RxMessage -  pointer to a structure receive message which contains
+ *        CAN Id, CAN DLC, CAN datas and FMI number.
+ *
+ * @return  none
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR;
+	
+  if (RxMessage->IDE == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3);
+  }
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR;
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR;
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8);
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24);
+
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RFIFO0 |= CAN_RFIFO0_RFOM0;
+  }
+  else 
+  {
+    CANx->RFIFO1 |= CAN_RFIFO1_RFOM1;
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_FIFORelease
+ *
+ * @brief   Releases the specified FIFO.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *
+ * @return  none
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RFIFO0 |= CAN_RFIFO0_RFOM0;
+  }
+  else 
+  {
+    CANx->RFIFO1 |= CAN_RFIFO1_RFOM1;
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_MessagePending
+ *
+ * @brief   Returns the number of pending messages.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *
+ * @return  message_pending: which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending=0;
+
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+	
+  return message_pending;
+}
+
+/*********************************************************************
+ * @fn      CAN_OperatingModeRequest
+ *
+ * @brief   Select the CAN Operation mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_OperatingMode - CAN Operating Mode.
+ *            CAN_OperatingMode_Initialization.
+ *            CAN_OperatingMode_Normal.
+ *            CAN_OperatingMode_Sleep.
+ *
+ * @return  status -
+ *          CAN_ModeStatus_Failed - CAN failed entering the specific mode.
+ *          CAN_ModeStatus_Success - CAN Succeed entering the specific mode.
+ */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+  uint32_t timeout = INAK_TIMEOUT; 
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ);
+
+    while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+    if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ));
+
+    while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->STATR & CAN_MODE_MASK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP);
+
+    while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/*********************************************************************
+ * @fn      CAN_Sleep
+ *
+ * @brief   Enters the low power mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  sleepstatus -
+ *            CAN_Sleep_Ok.
+ *            CAN_Sleep_Failed.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+
+  CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP);
+   
+  if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK)
+  {
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+	
+  return (uint8_t)sleepstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_WakeUp
+ *
+ * @brief   Wakes the CAN up.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  wakeupstatus -
+ *            CAN_WakeUp_Ok.
+ *            CAN_WakeUp_Failed.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+  uint32_t wait_slak = SLAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+    
+  CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP;
+    
+  while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00))
+  {
+   wait_slak--;
+  }
+  if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK)
+  {
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+
+  return (uint8_t)wakeupstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetLastErrorCode
+ *
+ * @brief   Returns the CANx's last error code (LEC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  errorcode - specifies the Error code.
+ *            CAN_ErrorCode_NoErr - No Error.
+ *            CAN_ErrorCode_StuffErr - Stuff Error.
+ *            CAN_ErrorCode_FormErr - Form Error.
+ *            CAN_ErrorCode_ACKErr - Acknowledgment Error.
+ *            CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error.
+ *            CAN_ErrorCode_BitDominantErr - Bit Dominant Error.
+ *            CAN_ErrorCode_CRCErr - CRC Error.
+ *            CAN_ErrorCode_SoftwareSetErr - Software Set Error.
+ */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+  uint8_t errorcode=0;
+  
+  errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC);
+  
+  return errorcode;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetReceiveErrorCounter
+ *
+ * @brief   Returns the CANx Receive Error Counter (REC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  counter - CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+   
+  counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24);
+  
+  return counter;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetLSBTransmitErrorCounter
+ *
+ * @brief   Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  counter - LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16);
+  
+  return counter;
+}
+
+/*********************************************************************
+ * @fn      CAN_ITConfig
+ *
+ * @brief   Enables or disables the specified CANx interrupts.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT - specifies the CAN interrupt sources to be enabled or disabled.
+ *            CAN_IT_TME.
+ *            CAN_IT_FMP0.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FMP1.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  counter - LSB of the 9-bit CAN Transmit Error Counter.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    CANx->INTENR |= CAN_IT;
+  }
+  else
+  {
+    CANx->INTENR &= ~CAN_IT;
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_GetFlagStatus
+ *
+ * @brief   Checks whether the specified CAN flag is set or not.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_FLAG - specifies the flag to check.
+ *            CAN_FLAG_EWG.
+ *            CAN_FLAG_EPV.
+ *            CAN_FLAG_BOF.
+ *            CAN_FLAG_RQCP0.
+ *            CAN_FLAG_RQCP1.
+ *            CAN_FLAG_RQCP2.
+ *            CAN_FLAG_FMP1.
+ *            CAN_FLAG_FF1.
+ *            CAN_FLAG_FOV1.
+ *            CAN_FLAG_FMP0.
+ *            CAN_FLAG_FF0.
+ *            CAN_FLAG_FOV0.
+ *            CAN_FLAG_WKU.
+ *            CAN_FLAG_SLAK.
+ *            CAN_FLAG_LEC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET)
+  { 
+    if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      bitstatus = SET;
+    }
+    else
+    { 
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET)
+  { 
+    if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      bitstatus = SET;
+    }
+    else
+    { 
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET)
+  { 
+    if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      bitstatus = SET;
+    }
+    else
+    { 
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET)
+  { 
+    if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      bitstatus = SET;
+    }
+    else
+    { 
+      bitstatus = RESET;
+    }
+  }
+  else 
+  { 
+    if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      bitstatus = SET;
+    }
+    else
+    { 
+      bitstatus = RESET;
+    }
+  }
+
+  return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_ClearFlag
+ *
+ * @brief   Clears the CAN's pending flags.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_FLAG - specifies the flag to clear.
+ *            CAN_FLAG_RQCP0.
+ *            CAN_FLAG_RQCP1.
+ *            CAN_FLAG_RQCP2.
+ *            CAN_FLAG_FF1.
+ *            CAN_FLAG_FOV1.
+ *            CAN_FLAG_FF0.
+ *            CAN_FLAG_FOV0.
+ *            CAN_FLAG_WKU.
+ *            CAN_FLAG_SLAK.
+ *            CAN_FLAG_LEC.
+ *
+ * @return  none
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp=0;
+  
+	if (CAN_FLAG == CAN_FLAG_LEC)
+  {
+    CANx->ERRSR = (uint32_t)RESET;
+  }
+  else 
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET)
+    {
+      CANx->RFIFO0 = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET)
+    {
+      CANx->RFIFO1 = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET)
+    {
+      CANx->TSTATR = (uint32_t)(flagtmp);
+    }
+    else 
+    {
+      CANx->STATR = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/*********************************************************************
+ * @fn      CAN_GetITStatus
+ *
+ * @brief   Checks whether the specified CANx interrupt has occurred or not.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT -  specifies the CAN interrupt source to check.
+ *            CAN_IT_TME.
+ *            CAN_IT_FMP0.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FMP1.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_BOF.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+	ITStatus itstatus = RESET;
+  
+  if((CANx->INTENR & CAN_IT) != RESET)
+  {
+    switch (CAN_IT)
+    {
+      case CAN_IT_TME:
+	      itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2);  
+	      break;
+			
+      case CAN_IT_FMP0:
+			  itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0);  
+	      break;
+			
+      case CAN_IT_FF0:
+        itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0);  
+	      break;
+			
+      case CAN_IT_FOV0:
+        itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0);  
+	      break;
+			
+      case CAN_IT_FMP1:
+        itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1);  
+	      break;
+			
+      case CAN_IT_FF1:
+	      itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1);  
+	      break;
+			
+      case CAN_IT_FOV1:
+	      itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1);  
+	      break;
+			
+      case CAN_IT_WKU:
+        itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI);  
+	      break;
+			
+      case CAN_IT_SLK:
+	      itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI);  
+	      break;
+			
+      case CAN_IT_EWG:
+	      itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF);  
+	      break;
+			
+      case CAN_IT_EPV:
+	      itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF);  
+	      break;
+			
+      case CAN_IT_BOF:
+	      itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF);  
+	      break;
+			
+      case CAN_IT_LEC:
+	      itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC);  
+	      break;
+			
+      case CAN_IT_ERR:
+        itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); 
+	      break;
+			
+      default :
+        itstatus = RESET;
+        break;
+    }
+	}
+  else
+  {
+    itstatus  = RESET;
+  }
+  
+  return  itstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_ClearITPendingBit
+ *
+ * @brief   Clears the CANx's interrupt pending bits.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT - specifies the interrupt pending bit to clear.
+ *            CAN_IT_TME.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_BOF.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *
+ * @return  none
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+	switch (CAN_IT)
+	{
+		case CAN_IT_TME:
+			CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2;  
+			break;
+
+		case CAN_IT_FF0:
+			CANx->RFIFO0 = CAN_RFIFO0_FULL0; 
+			break;
+
+		case CAN_IT_FOV0:
+			CANx->RFIFO0 = CAN_RFIFO0_FOVR0; 
+			break;
+
+		case CAN_IT_FF1:
+			CANx->RFIFO1 = CAN_RFIFO1_FULL1;  
+			break;
+
+		case CAN_IT_FOV1:
+			CANx->RFIFO1 = CAN_RFIFO1_FOVR1; 
+			break;
+
+		case CAN_IT_WKU:
+			CANx->STATR = CAN_STATR_WKUI;  
+			break;
+
+		case CAN_IT_SLK:
+			CANx->STATR = CAN_STATR_SLAKI;   
+			break;
+
+		case CAN_IT_EWG:
+			CANx->STATR = CAN_STATR_ERRI;
+			break;
+
+		case CAN_IT_EPV:
+			CANx->STATR = CAN_STATR_ERRI; 
+			break;
+
+		case CAN_IT_BOF:
+			CANx->STATR = CAN_STATR_ERRI; 
+			break;
+
+		case CAN_IT_LEC:
+			CANx->ERRSR = RESET; 
+			CANx->STATR = CAN_STATR_ERRI; 
+			break;
+
+		case CAN_IT_ERR:
+			CANx->ERRSR = RESET; 
+			CANx->STATR = CAN_STATR_ERRI; 
+			break;
+
+		default :
+			break;
+	}
+}
+
+/*********************************************************************
+ * @fn      CheckITStatus
+ *
+ * @brief   Checks whether the CAN interrupt has occurred or not.
+ *
+ * @param   CAN_Reg - specifies the CAN interrupt register to check
+ *          It_Bit - specifies the interrupt source bit to check.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    pendingbitstatus = RESET;
+  }
+	
+  return pendingbitstatus;
+}
+
+
+
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_crc.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_crc.c
new file mode 100644
index 0000000000..0839ad0109
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_crc.c
@@ -0,0 +1,97 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_crc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the CRC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_crc.h"
+
+/*********************************************************************
+ * @fn      CRC_ResetDR
+ *
+ * @brief   Resets the CRC Data register (DR).
+ *
+ * @return  none
+ */
+void CRC_ResetDR(void)
+{
+    CRC->CTLR = CRC_CTLR_RESET;
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given data word(32-bit).
+ *
+ * @param   Data - data word(32-bit) to compute its CRC.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+    CRC->DATAR = Data;
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcBlockCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ *
+ * @param   pBuffer - pointer to the buffer containing the data to be computed.
+ *          BufferLength - length of the buffer to be computed.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for(index = 0; index < BufferLength; index++){
+        CRC->DATAR = pBuffer[index];
+    }
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_GetCRC
+ *
+ * @brief   Returns the current CRC value.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_GetCRC(void)
+{
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_SetIDRegister
+ *
+ * @brief   Stores a 8-bit data in the Independent Data(ID) register.
+ *
+ * @param   IDValue - 8-bit value to be stored in the ID register.
+ *
+ * @return  none
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+    CRC->IDATAR = IDValue;
+}
+
+/*********************************************************************
+ * @fn      CRC_GetIDRegister
+ *
+ * @brief   Returns the 8-bit data stored in the Independent Data(ID) register.
+ *
+ * @return  8-bit value of the ID register.
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+    return (CRC->IDATAR);
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dbgmcu.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dbgmcu.c
new file mode 100644
index 0000000000..2bdef2d604
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dbgmcu.c
@@ -0,0 +1,98 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_dbgmcu.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the DBGMCU firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ****************************************************************************************/
+#include "ch32v20x_dbgmcu.h"
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x0000FFFF)
+
+/*********************************************************************
+ * @fn      DBGMCU_GetREVID
+ *
+ * @brief   Returns the device revision identifier.
+ *
+ * @return  Revision identifier.
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) >> 16);
+}
+
+/*********************************************************************
+ * @fn      DBGMCU_GetDEVID
+ *
+ * @brief   Returns the device identifier.
+ *
+ * @return  Device identifier.
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
+}
+
+/*********************************************************************
+ * @fn      __get_DEBUG_CR
+ *
+ * @brief   Return the DEBUGE Control Register
+ *
+ * @return  DEBUGE Control value
+ */
+uint32_t __get_DEBUG_CR(void)
+{
+    uint32_t result;
+
+    __asm volatile("csrr %0,""0x7C0" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_DEBUG_CR
+ *
+ * @brief   Set the DEBUGE Control Register
+ *
+ * @param   value  - set DEBUGE Control value
+ *
+ * @return  none
+ */
+void __set_DEBUG_CR(uint32_t value)
+{
+    __asm volatile("csrw 0x7C0, %0" : : "r"(value));
+}
+
+
+/*********************************************************************
+ * @fn      DBGMCU_Config
+ *
+ * @brief   Configures the specified peripheral and low power mode behavior
+ *        when the MCU under Debug mode.
+ *
+ * @param   DBGMCU_Periph - specifies the peripheral and low power mode.
+ *            DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
+ *            DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
+ *            DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
+ *            DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+    uint32_t val;
+
+    if(NewState != DISABLE)
+    {
+        __set_DEBUG_CR(DBGMCU_Periph);
+    }
+    else
+    {
+        val = __get_DEBUG_CR();
+        val &= ~(uint32_t)DBGMCU_Periph;
+        __set_DEBUG_CR(val);
+    }
+
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dma.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dma.c
new file mode 100644
index 0000000000..44a4662c59
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_dma.c
@@ -0,0 +1,430 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_dma.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the DMA firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_dma.h"
+#include "ch32v20x_rcc.h"
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+#define DMA1_Channel8_IT_Mask    ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask          ((uint32_t)0xFFFF800F)
+
+/*********************************************************************
+ * @fn      DMA_DeInit
+ *
+ * @brief   Deinitializes the DMAy Channelx registers to their default
+ *        reset values.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    DMAy_Channelx->CFGR = 0;
+    DMAy_Channelx->CNTR = 0;
+    DMAy_Channelx->PADDR = 0;
+    DMAy_Channelx->MADDR = 0;
+    if(DMAy_Channelx == DMA1_Channel1)
+    {
+        DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel2)
+    {
+        DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel3)
+    {
+        DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel4)
+    {
+        DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel5)
+    {
+        DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel6)
+    {
+        DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel7)
+    {
+        DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel8)
+    {
+        DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_Init
+ *
+ * @brief   Initializes the DMAy Channelx according to the specified
+ *        parameters in the DMA_InitStruct.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMAy_Channelx->CFGR;
+    tmpreg &= CFGR_CLEAR_Mask;
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+    DMAy_Channelx->CFGR = tmpreg;
+    DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
+    DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*********************************************************************
+ * @fn      DMA_StructInit
+ *
+ * @brief   Fills each DMA_InitStruct member with its default value.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
+{
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStruct->DMA_BufferSize = 0;
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*********************************************************************
+ * @fn      DMA_Cmd
+ *
+ * @brief   Enables or disables the specified DMAy Channelx.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_ITConfig
+ *
+ * @brief   Enables or disables the specified DMAy Channelx interrupts.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_IT - specifies the DMA interrupts sources to be enabled
+ *        or disabled.
+ *           DMA_IT_TC - Transfer complete interrupt mask
+ *           DMA_IT_HT - Half transfer interrupt mask
+ *           DMA_IT_TE -  Transfer error interrupt mask
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_IT;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ~DMA_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_SetCurrDataCounter
+ *
+ * @brief   Sets the number of data units in the current DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DataNumber - The number of data units in the current DMAy Channelx
+ *        transfer.
+ *
+ * @return  none
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
+{
+    DMAy_Channelx->CNTR = DataNumber;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetCurrDataCounter
+ *
+ * @brief   Returns the number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  DataNumber - The number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    return ((uint16_t)(DMAy_Channelx->CNTR));
+}
+
+/*********************************************************************
+ * @fn      DMA_GetFlagStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx flag is set or not.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+
+ * @return  The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t   tmpreg = 0;
+
+    tmpreg = DMA1->INTFR;
+
+    if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearFlag
+ *
+ * @brief   Clears the DMAy Channelx's pending flags.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ * @return  none
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+    DMA1->INTFCR = DMAy_FLAG;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetITStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx interrupt has
+ *        occurred or not.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ * @return  The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMA1->INTFR;
+
+    if((tmpreg & DMAy_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearITPendingBit
+ *
+ * @brief   Clears the DMAy Channelx's interrupt pending bits.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ * @return  none
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+    DMA1->INTFCR = DMAy_IT;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_exti.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_exti.c
new file mode 100644
index 0000000000..9d56c58dc3
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_exti.c
@@ -0,0 +1,180 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_exti.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the EXTI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32v20x_exti.h"
+
+/* No interrupt selected */
+#define EXTI_LINENONE    ((uint32_t)0x00000)
+
+/*********************************************************************
+ * @fn      EXTI_DeInit
+ *
+ * @brief   Deinitializes the EXTI peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none.
+ */
+void EXTI_DeInit(void)
+{
+    EXTI->INTENR = 0x00000000;
+    EXTI->EVENR = 0x00000000;
+    EXTI->RTENR = 0x00000000;
+    EXTI->FTENR = 0x00000000;
+    EXTI->INTFR = 0x000FFFFF;
+}
+
+/*********************************************************************
+ * @fn      EXTI_Init
+ *
+ * @brief   Initializes the EXTI peripheral according to the specified
+ *        parameters in the EXTI_InitStruct.
+ *
+ * @param   EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    uint32_t tmp = 0;
+
+    tmp = (uint32_t)EXTI_BASE;
+    if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
+        if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = (uint32_t)EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+            *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/*********************************************************************
+ * @fn      EXTI_StructInit
+ *
+ * @brief   Fills each EXTI_InitStruct member with its reset value.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GenerateSWInterrupt
+ *
+ * @brief   Generates a Software interrupt.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none.
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+    EXTI->SWIEVR |= EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetFlagStatus
+ *
+ * @brief   Checks whether the specified EXTI line flag is set or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearFlag
+ *
+ * @brief   Clears the EXTI's line pending flags.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetITStatus
+ *
+ * @brief   Checks whether the specified EXTI line is asserted or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = EXTI->INTENR & EXTI_Line;
+    if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearITPendingBit
+ *
+ * @brief   Clears the EXTI's line pending bits.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_flash.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_flash.c
new file mode 100644
index 0000000000..e6b430f9ef
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_flash.c
@@ -0,0 +1,965 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_flash.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the FLASH firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32v20x_flash.h"
+
+/* Flash Control Register bits */
+#define CR_PG_Set                  ((uint32_t)0x00000001)
+#define CR_PG_Reset                ((uint32_t)0xFFFFFFFE)
+#define CR_PER_Set                 ((uint32_t)0x00000002)
+#define CR_PER_Reset               ((uint32_t)0xFFFFFFFD)
+#define CR_MER_Set                 ((uint32_t)0x00000004)
+#define CR_MER_Reset               ((uint32_t)0xFFFFFFFB)
+#define CR_OPTPG_Set               ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset             ((uint32_t)0xFFFFFFEF)
+#define CR_OPTER_Set               ((uint32_t)0x00000020)
+#define CR_OPTER_Reset             ((uint32_t)0xFFFFFFDF)
+#define CR_STRT_Set                ((uint32_t)0x00000040)
+#define CR_LOCK_Set                ((uint32_t)0x00000080)
+#define CR_FAST_LOCK_Set           ((uint32_t)0x00008000)
+#define CR_PAGE_PG                 ((uint32_t)0x00010000)
+#define CR_PAGE_ER                 ((uint32_t)0x00020000)
+#define CR_BER32                   ((uint32_t)0x00040000)
+#define CR_BER64                   ((uint32_t)0x00080000)
+#define CR_PG_STRT                 ((uint32_t)0x00200000)
+
+/* FLASH Status Register bits */
+#define SR_BSY                     ((uint32_t)0x00000001)
+#define SR_WR_BSY                  ((uint32_t)0x00000002)
+#define SR_WRPRTERR                ((uint32_t)0x00000010)
+#define SR_EOP                     ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask                 ((uint32_t)0x00000002)
+#define WRP0_Mask                  ((uint32_t)0x000000FF)
+#define WRP1_Mask                  ((uint32_t)0x0000FF00)
+#define WRP2_Mask                  ((uint32_t)0x00FF0000)
+#define WRP3_Mask                  ((uint32_t)0xFF000000)
+#define OB_USER_BFB2               ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                    ((uint16_t)0x00A5)
+#define FLASH_KEY1                 ((uint32_t)0x45670123)
+#define FLASH_KEY2                 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS    ((uint32_t)0x807FFFF)
+
+/* EEPROM address */
+#define EEPROM_ADDRESS             ((uint32_t)0x8070000)
+
+/* Delay definition */
+#define EraseTimeout               ((uint32_t)0x000B0000)
+#define ProgramTimeout             ((uint32_t)0x00005000)
+
+/*********************************************************************
+ * @fn      FLASH_Unlock
+ *
+ * @brief   Unlocks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Unlock(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UnlockBank1
+ *
+ * @brief   Unlocks the FLASH Bank1 Program Erase Controller.
+ *          equivalent to FLASH_Unlock function.
+ *
+ * @return  none
+ */
+void FLASH_UnlockBank1(void)
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock
+ *
+ * @brief   Locks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Lock(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_LockBank1
+ *
+ * @brief   Locks the FLASH Bank1 Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_LockBank1(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage
+ *
+ * @brief   Erases a specified FLASH page(page size 4KB).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PER_Set;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_PER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllPages
+ *
+ * @brief   Erases all FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllBank1Pages
+ *
+ * @brief   Erases all Bank1 FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseOptionBytes
+ *
+ * @brief   Erases the FLASH option bytes.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+    uint16_t     rdptmp = RDP_Key;
+    uint32_t     Address = 0x1FFFF800;
+    __IO uint8_t i;
+
+    FLASH_Status status = FLASH_COMPLETE;
+    if(FLASH_GetReadOutProtectionStatus() != RESET)
+    {
+        rdptmp = 0x00;
+    }
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            OB->RDPR = (uint16_t)rdptmp;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+
+        /* Write 0xFF */
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++){
+            *(uint16_t *)(Address + 2 * i) = 0x00FF;
+            while(FLASH->STATR & SR_BSY);
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramWord
+ *
+ * @brief   Programs a word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_Status  status = FLASH_COMPLETE;
+    __IO uint32_t tmp = 0;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+
+        *(__IO uint16_t *)Address = (uint16_t)Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            tmp = Address + 2;
+            *(__IO uint16_t *)tmp = Data >> 16;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+        else
+        {
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramHalfWord
+ *
+ * @brief   Programs a half word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+        *(__IO uint16_t *)Address = Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        FLASH->CTLR &= CR_PG_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramOptionByteData
+ *
+ * @brief   Programs a half word at a specified Option Byte Data address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++){
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY);
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++){
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY) ;
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EnableWriteProtection
+ *
+ * @brief   Write protects the desired sectors
+ *
+ * @param   FLASH_Sectors - specifies the address of the pages to be write protected.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors)
+{
+    uint16_t     WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH_Sectors = (uint32_t)(~FLASH_Sectors);
+    WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask);
+    WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8);
+    WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16);
+    WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24);
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++){
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY);
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[4] = WRP0_Data;
+        pbuf[5] = WRP1_Data;
+        pbuf[6] = WRP2_Data;
+        pbuf[7] = WRP3_Data;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++){
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY);
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ReadOutProtection
+ *
+ * @brief   Enables or disables the read out protection.
+ *
+ * @param   Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++){
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY);
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        if(NewState == DISABLE)
+            pbuf[0] = 0x5AA5;
+        else
+            pbuf[0] = 0x00FF;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++){
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY);
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UserOptionByteConfig
+ *
+ * @brief   Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
+ *
+ * @param   OB_IWDG - Selects the IWDG mode
+ *            OB_IWDG_SW - Software IWDG selected
+ *            OB_IWDG_HW - Hardware IWDG selected
+ *          OB_STOP - Reset event when entering STOP mode.
+ *            OB_STOP_NoRST - No reset generated when entering in STOP
+ *            OB_STOP_RST - Reset generated when entering in STOP
+ *          OB_STDBY - Reset event when entering Standby mode.
+ *            OB_STDBY_NoRST - No reset generated when entering in STANDBY
+ *            OB_STDBY_RST - Reset generated when entering in STANDBY
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH->OBKEYR = FLASH_KEY1;
+    FLASH->OBKEYR = FLASH_KEY2;
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++){
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY);
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++){
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY);
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetUserOptionByte
+ *
+ * @brief   Returns the FLASH User Option Bytes values.
+ *
+ * @return  The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *        and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+    return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetWriteProtectionOptionByte
+ *
+ * @brief   Returns the FLASH Write Protection Option Bytes Register value.
+ *
+ * @return  The FLASH Write Protection Option Bytes Register value.
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+    return (uint32_t)(FLASH->WPR);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetReadOutProtectionStatus
+ *
+ * @brief   Checks whether the FLASH Read Out Protection Status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ITConfig
+ *
+ * @brief   Enables or disables the specified FLASH interrupts.
+ *
+ * @param   FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
+ *            FLASH_IT_ERROR - FLASH Error Interrupt
+ *            FLASH_IT_EOP - FLASH end of operation Interrupt
+ *          NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
+ *
+ * @return  FLASH Prefetch Buffer Status (SET or RESET).
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        FLASH->CTLR |= FLASH_IT;
+    }
+    else
+    {
+        FLASH->CTLR &= ~(uint32_t)FLASH_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FLASH flag is set or not.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flag to check.
+ *            FLASH_FLAG_BSY - FLASH Busy flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
+ *
+ * @return  The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+    {
+        if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ClearFlag
+ *
+ * @brief   Clears the FLASH's pending flags.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flags to clear.
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *
+ * @return  none
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+    FLASH->STATR = FLASH_FLAG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetStatus
+ *
+ * @brief   Returns the FLASH Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_WRP;
+        }
+        else
+        {
+            flashstatus = FLASH_COMPLETE;
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetBank1Status
+ *
+ * @brief   Returns the FLASH Bank1 Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_WRP;
+        }
+        else
+        {
+            flashstatus = FLASH_COMPLETE;
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastOperation
+ *
+ * @brief   Waits for a Flash operation to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastBank1Operation
+ *
+ * @brief   Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Unlock_Fast(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock_Fast
+ *
+ * @brief   Locks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Lock_Fast(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage_Fast
+ *
+ * @brief   Erases a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_ErasePage_Fast(uint32_t Page_Address)
+{
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_ER;
+    FLASH->ADDR = Page_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY);
+    FLASH->CTLR &= ~CR_PAGE_ER;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_32K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 32KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF8000;
+
+    FLASH->CTLR |= CR_BER32;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY);
+    FLASH->CTLR &= ~CR_BER32;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_64K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 64KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF0000;
+
+    FLASH->CTLR |= CR_BER64;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY);
+    FLASH->CTLR &= ~CR_BER64;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramPage_Fast
+ *
+ * @brief   Program a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be programed.
+ *
+ * @return  none
+ */
+void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf)
+{
+    uint8_t size = 64;
+
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_PG;
+    while(FLASH->STATR & SR_BSY);
+    while(FLASH->STATR & SR_WR_BSY);
+
+    while(size)
+    {
+        *(uint32_t *)Page_Address = *(uint32_t *)pbuf;
+        Page_Address += 4;
+        pbuf += 1;
+        size -= 1;
+        while(FLASH->STATR & SR_WR_BSY);
+    }
+
+    FLASH->CTLR |= CR_PG_STRT;
+    while(FLASH->STATR & SR_BSY);
+    FLASH->CTLR &= ~CR_PAGE_PG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Access_Clock_Cfg
+ *
+ * @brief   Config FLASH Access Clock(Need to unlock )
+ *
+ * @param   FLASH_Access_CLK -
+ *            FLASH_Access_SYSTEM_HALF - System clock/2
+ *            FLASH_Access_SYSTEM - System clock
+ *
+ * @return  none
+ */
+void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK)
+{
+    FLASH->CTLR &= ~(1 << 25);
+    FLASH->CTLR |= FLASH_Access_CLK;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Enhance_Mode
+ *
+ * @brief   Read FLASH Enhance Mode
+ *
+ * @param
+ *          Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void FLASH_Enhance_Mode(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        FLASH->CTLR |= (1 << 24);
+    }
+    else
+    {
+        FLASH->CTLR &= ~(1 << 24);
+        FLASH->CTLR |= (1 << 22);
+    }
+}
+
+/********************************************************************************
+ * @fn        FLASH_GetMACAddress
+ *
+ * @brief     Get MAC address
+ *
+ * @param     *Buffer: Mac address
+ *
+ * @return    None
+ */
+void FLASH_GetMACAddress(uint8_t *Buffer)
+{
+    uint32_t value;
+
+    value = *(uint32_t *)(0x1FFFF7E8);
+    Buffer[0] = value & 0xFF;
+    Buffer[1] = (value >> 8) & 0xFF;
+    Buffer[2] = (value >> 16) & 0xFF;
+    Buffer[3] = (value >> 24) & 0xFF;
+    value = *(uint32_t *)(0x1FFFF7EC);
+    Buffer[4] = value & 0xFF;
+    Buffer[5] = (value >> 8) & 0xFF;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_gpio.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_gpio.c
new file mode 100644
index 0000000000..c7f3805f06
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_gpio.c
@@ -0,0 +1,671 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_gpio.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the GPIO firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_rcc.h"
+
+/* MASK */
+#define ECR_PORTPINCONFIG_MASK    ((uint16_t)0xFF80)
+#define LSB_MASK                  ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK      ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK        ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK      ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK       ((uint32_t)0x00100000)
+
+#if defined (CH32V20x_D6)
+uint8_t MCU_Version = 0;
+#endif
+
+/*********************************************************************
+ * @fn      GPIO_DeInit
+ *
+ * @brief   Deinitializes the GPIOx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+    if(GPIOx == GPIOA)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+    }
+    else if(GPIOx == GPIOB)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+    }
+    else if(GPIOx == GPIOC)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+    }
+    else if(GPIOx == GPIOD)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+    }
+    else if(GPIOx == GPIOE)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_AFIODeInit
+ *
+ * @brief   Deinitializes the Alternate Functions (remap, event control
+ *        and EXTI configuration) registers to their default reset values.
+ *
+ * @return  none
+ */
+void GPIO_AFIODeInit(void)
+{
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      GPIO_Init
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
+ *        contains the configuration information for the specified GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+    uint32_t tmpreg = 0x00, pinmask = 0x00;
+
+    currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+
+    if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+    {
+        currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+    }
+#if defined (CH32V20x_D6)
+    if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0)
+    {
+        MCU_Version = 1;
+    }
+
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin >> 13;
+    }
+
+#endif
+    if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+    {
+        tmpreg = GPIOx->CFGLR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = ((uint32_t)0x01) << pinpos;
+            currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << pinpos);
+                }
+                else
+                {
+                    if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                    {
+                        GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
+                    }
+                }
+            }
+        }
+        GPIOx->CFGLR = tmpreg;
+    }
+
+    if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
+    {
+        tmpreg = GPIOx->CFGHR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = (((uint32_t)0x01) << (pinpos + 0x08));
+            currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                {
+                    GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+            }
+        }
+        GPIOx->CFGHR = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_StructInit
+ *
+ * @brief   Fills each GPIO_InitStruct member with its default
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
+ *      which will be initialized.
+ *
+ * @return  none
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputDataBit
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param    GPIO_Pin - specifies the port bit to read.
+ *             This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputData
+ *
+ * @brief   Reads the specified GPIO input data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  The output port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
+{
+    uint16_t val;
+
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        val = ( uint16_t )(GPIOx->INDR << 13);
+    }
+    else{
+        val = ( uint16_t )GPIOx->INDR;
+    }
+
+#else
+    val = ( uint16_t )GPIOx->INDR;
+#endif
+
+return ( val );
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputDataBit
+ *
+ * @brief   Reads the specified output data port bit.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to read.
+ *            This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputData
+ *
+ * @brief   Reads the specified GPIO output data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  GPIO output port pin value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
+{
+    uint16_t val;
+
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        val = ( uint16_t )(GPIOx->OUTDR << 13);
+    }
+    else{
+        val = ( uint16_t )GPIOx->OUTDR;
+    }
+
+#else
+    val = ( uint16_t )GPIOx->OUTDR;
+#endif
+
+    return ( val );
+}
+
+/*********************************************************************
+ * @fn      GPIO_SetBits
+ *
+ * @brief   Sets the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    GPIOx->BSHR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ResetBits
+ *
+ * @brief   Clears the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    GPIOx->BCR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_WriteBit
+ *
+ * @brief   Sets or clears the selected data port bit.
+ *
+ * @param   GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ *          BitVal - specifies the value to be written to the selected bit.
+ *            Bit_SetL - to clear the port pin.
+ *            Bit_SetH - to set the port pin.
+ *
+ * @return  none
+ */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    if(BitVal != Bit_RESET)
+    {
+        GPIOx->BSHR = GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->BCR = GPIO_Pin;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_Write
+ *
+ * @brief   Writes data to the specified GPIO data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          PortVal - specifies the value to be written to the port output data register.
+ *
+ * @return  none
+ */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
+{
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        PortVal = PortVal >> 13;
+    }
+
+#endif
+
+    GPIOx->OUTDR = PortVal;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinLockConfig
+ *
+ * @brief   Locks GPIO Pins configuration registers.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint32_t tmp = 0x00010000;
+
+#if defined (CH32V20x_D6)
+    if((GPIOx == GPIOC) && MCU_Version){
+        GPIO_Pin = GPIO_Pin >> 13;
+    }
+
+#endif
+
+    tmp |= GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    GPIOx->LCKR = GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    tmp = GPIOx->LCKR;
+    tmp = GPIOx->LCKR;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputConfig
+ *
+ * @brief   Selects the GPIO pin used as Event output.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source
+ *        for Event output.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ *          GPIO_PinSource - specifies the pin for the Event output.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = AFIO->ECR;
+    tmpreg &= ECR_PORTPINCONFIG_MASK;
+    tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+    tmpreg |= GPIO_PinSource;
+    AFIO->ECR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputCmd
+ *
+ * @brief   Enables or disables the Event Output.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        AFIO->ECR |= (1 << 7);
+    }
+    else
+    {
+        AFIO->ECR &= ~(1 << 7);
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinRemapConfig
+ *
+ * @brief   Changes the mapping of the specified pin.
+ *
+ * @param   GPIO_Remap - selects the pin to remap.
+ *            GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
+ *            GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
+ *            GPIO_Remap_USART1 - USART1 Alternate Function mapping
+ *            GPIO_Remap_USART2 - USART2 Alternate Function mapping
+ *            GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
+ *            GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
+ *            GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
+ *            GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
+ *            GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
+ *            GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap_PD01 - PD01 Alternate Function mapping
+ *            GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ETH - Ethernet remapping
+ *            GPIO_Remap_CAN2 - CAN2 remapping
+ *            GPIO_Remap_MII_RMII_SEL - MII or RMII selection
+ *            GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *            GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
+ *            GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ *        to TIM2 Internal Trigger 1 for calibration
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
+ *            GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
+ *            GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
+ *            GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
+ *            GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
+ *            GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+    uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        tmpreg = AFIO->PCFR2;
+    }
+    else
+    {
+        tmpreg = AFIO->PCFR1;
+
+#if defined (CH32V20x_D6) || defined (CH32V20x_D8)
+    if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){
+        tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF);
+    }
+
+#endif
+    }
+
+    tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+    tmp = GPIO_Remap & LSB_MASK;
+
+    /* Clear bit */
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {                                                                                                                   /* PCFR2 */
+        if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
+            tmpreg &= ~tmp1;
+        }
+        else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << tmpmask;
+            tmpreg &= ~tmp1;
+        }
+        else /* [31:0] 1bit */
+        {
+            tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+        }
+    }
+    else
+    {                                                                                                                   /* PCFR1 */
+        if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
+        {
+            tmpreg &= DBGAFR_SWJCFG_MASK;
+            AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
+        }
+        else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << tmpmask;
+            tmpreg &= ~tmp1;
+            tmpreg |= ~DBGAFR_SWJCFG_MASK;
+        }
+        else /* [31:0] 1bit */
+        {
+            tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+            tmpreg |= ~DBGAFR_SWJCFG_MASK;
+        }
+    }
+
+    /* Set bit */
+    if(NewState != DISABLE)
+    {
+        tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
+    }
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        AFIO->PCFR2 = tmpreg;
+    }
+    else
+    {
+        AFIO->PCFR1 = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_EXTILineConfig
+ *
+ * @brief   Selects the GPIO pin used as EXTI Line.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ *          GPIO_PinSource - specifies the EXTI line to be configured.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmp = 0x00;
+
+#if defined (CH32V20x_D6)
+        if((GPIO_PortSource == GPIO_PortSourceGPIOC) && MCU_Version){
+            GPIO_PinSource -= 13;
+        }
+
+#endif
+
+    tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/*********************************************************************
+ * @fn      GPIO_ETH_MediaInterfaceConfig
+ *
+ * @brief   Selects the Ethernet media interface.
+ *
+ * @param   GPIO_ETH_MediaInterface - specifies the Media Interface mode.
+ *            GPIO_ETH_MediaInterface_MII - MII mode
+ *            GPIO_ETH_MediaInterface_RMII - RMII mode
+ *
+ * @return  none
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+    if(GPIO_ETH_MediaInterface)
+    {
+        AFIO->PCFR1 |= (1 << 23);
+    }
+    else
+    {
+        AFIO->PCFR1 &= ~(1 << 23);
+    }
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_i2c.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_i2c.c
new file mode 100644
index 0000000000..3040b1f2c4
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_i2c.c
@@ -0,0 +1,972 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_i2c.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the I2C firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_rcc.h"
+
+/* I2C SPE mask */
+#define CTLR1_PE_Set             ((uint16_t)0x0001)
+#define CTLR1_PE_Reset           ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTLR1_START_Set          ((uint16_t)0x0100)
+#define CTLR1_START_Reset        ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTLR1_STOP_Set           ((uint16_t)0x0200)
+#define CTLR1_STOP_Reset         ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTLR1_ACK_Set            ((uint16_t)0x0400)
+#define CTLR1_ACK_Reset          ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTLR1_ENGC_Set           ((uint16_t)0x0040)
+#define CTLR1_ENGC_Reset         ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTLR1_SWRST_Set          ((uint16_t)0x8000)
+#define CTLR1_SWRST_Reset        ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTLR1_PEC_Set            ((uint16_t)0x1000)
+#define CTLR1_PEC_Reset          ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTLR1_ENPEC_Set          ((uint16_t)0x0020)
+#define CTLR1_ENPEC_Reset        ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTLR1_ENARP_Set          ((uint16_t)0x0010)
+#define CTLR1_ENARP_Reset        ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTLR1_NOSTRETCH_Set      ((uint16_t)0x0080)
+#define CTLR1_NOSTRETCH_Reset    ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTLR1_CLEAR_Mask         ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTLR2_DMAEN_Set          ((uint16_t)0x0800)
+#define CTLR2_DMAEN_Reset        ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTLR2_LAST_Set           ((uint16_t)0x1000)
+#define CTLR2_LAST_Reset         ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTLR2_FREQ_Reset         ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADD0_Set          ((uint16_t)0x0001)
+#define OADDR1_ADD0_Reset        ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_ENDUAL_Set        ((uint16_t)0x0001)
+#define OADDR2_ENDUAL_Reset      ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADD2_Reset        ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CKCFGR_FS_Set            ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CKCFGR_CCR_Set           ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask                ((uint32_t)0x07000000)
+
+/*********************************************************************
+ * @fn      I2C_DeInit
+ *
+ * @brief   Deinitializes the I2Cx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    if(I2Cx == I2C1)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+    }
+    else
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_Init
+ *
+ * @brief   Initializes the I2Cx peripheral according to the specified
+ *        parameters in the I2C_InitStruct.
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
+ *        contains the configuration information for the specified I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    uint16_t tmpreg = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1 = 8000000;
+
+    RCC_ClocksTypeDef rcc_clocks;
+
+    tmpreg = I2Cx->CTLR2;
+    tmpreg &= CTLR2_FREQ_Reset;
+    RCC_GetClocksFreq(&rcc_clocks);
+    pclk1 = rcc_clocks.PCLK1_Frequency;
+    freqrange = (uint16_t)(pclk1 / 1000000);
+    tmpreg |= freqrange;
+    I2Cx->CTLR2 = tmpreg;
+
+    I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    tmpreg = 0;
+
+    if(I2C_InitStruct->I2C_ClockSpeed <= 100000)
+    {
+        result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+
+        if(result < 0x04)
+        {
+            result = 0x04;
+        }
+
+        tmpreg |= result;
+        I2Cx->RTR = freqrange + 1;
+    }
+    else
+    {
+        if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+        }
+        else
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+            result |= I2C_DutyCycle_16_9;
+        }
+
+        if((result & CKCFGR_CCR_Set) == 0)
+        {
+            result |= (uint16_t)0x0001;
+        }
+
+        tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
+        I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+    }
+
+    I2Cx->CKCFGR = tmpreg;
+    I2Cx->CTLR1 |= CTLR1_PE_Set;
+
+    tmpreg = I2Cx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+    I2Cx->CTLR1 = tmpreg;
+
+    I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/*********************************************************************
+ * @fn      I2C_StructInit
+ *
+ * @brief   Fills each I2C_InitStruct member with its default value.
+ *
+ * @param   I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    I2C_InitStruct->I2C_ClockSpeed = 5000;
+    I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+    I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+    I2C_InitStruct->I2C_OwnAddress1 = 0;
+    I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+    I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/*********************************************************************
+ * @fn      I2C_Cmd
+ *
+ * @brief   Enables or disables the specified I2C peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PE_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMACmd
+ *
+ * @brief   Enables or disables the specified I2C DMA requests.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMALastTransferCmd
+ *
+ * @brief   Specifies if the next DMA transfer will be the last one.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_LAST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_LAST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTART
+ *
+ * @brief   Generates I2Cx communication START condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_START_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_START_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTOP
+ *
+ * @brief   Generates I2Cx communication STOP condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_STOP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_STOP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_AcknowledgeConfig
+ *
+ * @brief   Enables or disables the specified I2C acknowledge feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ACK_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_OwnAddress2Config
+ *
+ * @brief   Configures the specified I2C own address2.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the 7bit I2C own address2.
+ *
+ * @return  none
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = I2Cx->OADDR2;
+    tmpreg &= OADDR2_ADD2_Reset;
+    tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+    I2Cx->OADDR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      I2C_DualAddressCmd
+ *
+ * @brief   Enables or disables the specified I2C dual addressing mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
+    }
+    else
+    {
+        I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GeneralCallCmd
+ *
+ * @brief   Enables or disables the specified I2C general call feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENGC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_ITConfig
+ *
+ * @brief   Enables or disables the specified I2C interrupts.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
+ *            I2C_IT_BUF - Buffer interrupt mask.
+ *            I2C_IT_EVT - Event interrupt mask.
+ *            I2C_IT_ERR - Error interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= I2C_IT;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SendData
+ *
+ * @brief   Sends a data byte through the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Data - Byte to be transmitted.
+ *
+ * @return  none
+ */
+void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+    I2Cx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    return (uint8_t)I2Cx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      I2C_Send7bitAddress
+ *
+ * @brief   Transmits the address byte to select the slave device.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the slave address which will be transmitted.
+ *          I2C_Direction - specifies whether the I2C device will be a
+ *        Transmitter or a Receiver.
+ *            I2C_Direction_Transmitter - Transmitter mode.
+ *            I2C_Direction_Receiver - Receiver mode.
+ *
+ * @return  none
+ */
+void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+    if(I2C_Direction != I2C_Direction_Transmitter)
+    {
+        Address |= OADDR1_ADD0_Set;
+    }
+    else
+    {
+        Address &= OADDR1_ADD0_Reset;
+    }
+
+    I2Cx->DATAR = Address;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReadRegister
+ *
+ * @brief   Reads the specified I2C register and returns its value.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_Register - specifies the register to read.
+ *            I2C_Register_CTLR1.
+ *            I2C_Register_CTLR2.
+ *            I2C_Register_OADDR1.
+ *            I2C_Register_OADDR2.
+ *            I2C_Register_DATAR.
+ *            I2C_Register_STAR1.
+ *            I2C_Register_STAR2.
+ *            I2C_Register_CKCFGR.
+ *            I2C_Register_RTR.
+ *
+ * @return  none
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)I2Cx;
+    tmp += I2C_Register;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      I2C_SoftwareResetCmd
+ *
+ * @brief   Enables or disables the specified I2C software reset.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_SWRST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_NACKPositionConfig
+ *
+ * @brief   Selects the specified I2C NACK position in master receiver mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_NACKPosition - specifies the NACK position.
+ *            I2C_NACKPosition_Next - indicates that the next byte will be
+ *        the last received byte.
+ *            I2C_NACKPosition_Current - indicates that current byte is the
+ *        last received byte.
+ *
+ * @return  none
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
+{
+    if(I2C_NACKPosition == I2C_NACKPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_NACKPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_NACKPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SMBusAlertConfig
+ *
+ * @brief   Drives the SMBusAlert pin high or low for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_SMBusAlert - specifies SMBAlert pin level.
+ *            I2C_SMBusAlert_Low - SMBAlert pin driven low.
+ *            I2C_SMBusAlert_High - SMBAlert pin driven high.
+ *
+ * @return  none
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
+{
+    if(I2C_SMBusAlert == I2C_SMBusAlert_Low)
+    {
+        I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_SMBusAlert_High;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_TransmitPEC
+ *
+ * @brief   Enables or disables the specified I2C PEC transfer.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_PECPositionConfig
+ *
+ * @brief   Selects the specified I2C PEC position.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_PECPosition - specifies the PEC position.
+ *            I2C_PECPosition_Next - indicates that the next byte is PEC.
+ *            I2C_PECPosition_Current - indicates that current byte is PEC.
+ *
+ * @return  none
+ */
+void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
+{
+    if(I2C_PECPosition == I2C_PECPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_PECPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_PECPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CalculatePEC
+ *
+ * @brief   Enables or disables the PEC value calculation of the transferred bytes.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GetPEC
+ *
+ * @brief   Returns the PEC value for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
+{
+    return ((I2Cx->STAR2) >> 8);
+}
+
+/*********************************************************************
+ * @fn      I2C_ARPCmd
+ *
+ * @brief   Enables or disables the specified I2C ARP.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  The PEC value.
+ */
+void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENARP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_StretchClockCmd
+ *
+ * @brief   Enables or disables the specified I2C Clock stretching.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState == DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_FastModeDutyCycleConfig
+ *
+ * @brief   Selects the specified I2C fast mode duty cycle.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_DutyCycle - specifies the fast mode duty cycle.
+ *            I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
+ *            I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
+ *
+ * @return  none
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
+{
+    if(I2C_DutyCycle != I2C_DutyCycle_16_9)
+    {
+        I2Cx->CKCFGR &= I2C_DutyCycle_2;
+    }
+    else
+    {
+        I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CheckEvent
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_EVENT: specifies the event to be checked.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
+ *             I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
+ *             I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
+ *             I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
+ *             I2C_EVENT_MASTER_MODE_SELECT - EV5.
+ *             I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
+ *             I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
+ *
+ * @return  none
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    uint32_t    lastevent = 0;
+    uint32_t    flag1 = 0, flag2 = 0;
+    ErrorStatus status = NoREADY;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    if((lastevent & I2C_EVENT) == I2C_EVENT)
+    {
+        status = READY;
+    }
+    else
+    {
+        status = NoREADY;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetLastEvent
+ *
+ * @brief   Returns the last I2Cx Event.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    return lastevent;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetFlagStatus
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to check.
+ *            I2C_FLAG_DUALF - Dual flag (Slave mode).
+ *            I2C_FLAG_SMBHOST - SMBus host header (Slave mode).
+ *            I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode).
+ *            I2C_FLAG_GENCALL - General call header flag (Slave mode).
+ *            I2C_FLAG_TRA - Transmitter/Receiver flag.
+ *            I2C_FLAG_BUSY - Bus busy flag.
+ *            I2C_FLAG_MSL - Master/Slave flag.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *            I2C_FLAG_TXE - Data register empty flag (Transmitter).
+ *            I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
+ *            I2C_FLAG_STOPF - Stop detection flag (Slave mode).
+ *            I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_FLAG_BTF - Byte transfer finished flag.
+ *            I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
+ *        Address matched flag (Slave mode)"ENDA".
+ *            I2C_FLAG_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus    bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+    i2cxbase = (uint32_t)I2Cx;
+    i2creg = I2C_FLAG >> 28;
+    I2C_FLAG &= FLAG_Mask;
+
+    if(i2creg != 0)
+    {
+        i2cxbase += 0x14;
+    }
+    else
+    {
+        I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+        i2cxbase += 0x18;
+    }
+
+    if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearFlag
+ *
+ * @brief   Clears the I2Cx's pending flags.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to clear.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *
+ * @return  none
+ */
+void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_FLAG & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetITStatus
+ *
+ * @brief   Checks whether the specified I2C interrupt has occurred or not.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          II2C_IT - specifies the interrupt source to check.
+ *            I2C_IT_SMBALERT - SMBus Alert flag.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_IT_PECERR - PEC error in reception flag.
+ *            I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure flag.
+ *            I2C_IT_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_IT_BERR - Bus error flag.
+ *            I2C_IT_TXE - Data register empty flag (Transmitter).
+ *            I2C_IT_RXNE - Data register not empty (Receiver) flag.
+ *            I2C_IT_STOPF - Stop detection flag (Slave mode).
+ *            I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_IT_BTF - Byte transfer finished flag.
+ *            I2C_IT_ADDR - Address sent flag (Master mode) "ADSL"  Address matched
+ *        flag (Slave mode)"ENDAD".
+ *            I2C_IT_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
+    I2C_IT &= FLAG_Mask;
+
+    if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearITPendingBit
+ *
+ * @brief   Clears the I2Cx interrupt pending bits.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the interrupt pending bit to clear.
+ *            I2C_IT_SMBALERT - SMBus Alert interrupt.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error interrupt.
+ *            I2C_IT_PECERR - PEC error in reception  interrupt.
+ *            I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure interrupt.
+ *            I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
+ *            I2C_IT_BERR - Bus error interrupt.
+ *
+ * @return  none
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_IT & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_iwdg.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_iwdg.c
new file mode 100644
index 0000000000..cae190cc15
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_iwdg.c
@@ -0,0 +1,120 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_iwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the IWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_iwdg.h"
+
+/* CTLR register bit mask */
+#define CTLR_KEY_Reload    ((uint16_t)0xAAAA)
+#define CTLR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/*********************************************************************
+ * @fn      IWDG_WriteAccessCmd
+ *
+ * @brief   Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
+ *
+ * @param   WDG_WriteAccess - new state of write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
+ *        and IWDG_RLDR registers.
+ *
+ * @return  none
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+    IWDG->CTLR = IWDG_WriteAccess;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetPrescaler
+ *
+ * @brief   Sets IWDG Prescaler value.
+ *
+ * @param   IWDG_Prescaler - specifies the IWDG Prescaler value.
+ *             IWDG_Prescaler_4 - IWDG prescaler set to 4.
+ *             IWDG_Prescaler_8 - IWDG prescaler set to 8.
+ *             IWDG_Prescaler_16 - IWDG prescaler set to 16.
+ *             IWDG_Prescaler_32 - IWDG prescaler set to 32.
+ *             IWDG_Prescaler_64 - IWDG prescaler set to 64.
+ *             IWDG_Prescaler_128 - IWDG prescaler set to 128.
+ *             IWDG_Prescaler_256 - IWDG prescaler set to 256.
+ *
+ * @return  none
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+    IWDG->PSCR = IWDG_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetReload
+ *
+ * @brief   Sets IWDG Reload value.
+ *
+ * @param   Reload - specifies the IWDG Reload value.
+ *            This parameter must be a number between 0 and 0x0FFF.
+ *
+ * @return  none
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+    IWDG->RLDR = Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_ReloadCounter
+ *
+ * @brief   Reloads IWDG counter with value defined in the reload register.
+ *
+ * @return  none
+ */
+void IWDG_ReloadCounter(void)
+{
+    IWDG->CTLR = CTLR_KEY_Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_Enable
+ *
+ * @brief   Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
+ *
+ * @return  none
+ */
+void IWDG_Enable(void)
+{
+    IWDG->CTLR = CTLR_KEY_Enable;
+}
+
+/*********************************************************************
+ * @fn      IWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified IWDG flag is set or not.
+ *
+ * @param   IWDG_FLAG - specifies the flag to check.
+ *            IWDG_FLAG_PVU - Prescaler Value Update on going.
+ *            IWDG_FLAG_RVU - Reload Value Update on going.
+ *
+ * @return  none
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_misc.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_misc.c
new file mode 100644
index 0000000000..3001affafe
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_misc.c
@@ -0,0 +1,107 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_misc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the miscellaneous firmware functions .
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v20x_misc.h"
+
+__IO uint32_t NVIC_Priority_Group = 0;
+
+/*********************************************************************
+ * @fn      NVIC_PriorityGroupConfig
+ *
+ * @brief   Configures the priority grouping - pre-emption priority and subpriority.
+ *
+ * @param   NVIC_PriorityGroup - specifies the priority grouping bits length.
+ *            NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
+ *                                   4 bits for subpriority
+ *            NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
+ *                                   3 bits for subpriority
+ *            NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
+ *                                   2 bits for subpriority
+ *            NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
+ *                                   1 bits for subpriority
+ *            NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
+ *                                   0 bits for subpriority
+ *
+ * @return  none
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+    NVIC_Priority_Group = NVIC_PriorityGroup;
+}
+
+/*********************************************************************
+ * @fn      NVIC_Init
+ *
+ * @brief   Initializes the NVIC peripheral according to the specified parameters in
+ *        the NVIC_InitStruct.
+ *
+ * @param   NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
+ *        configuration information for the specified NVIC peripheral.
+ *
+ * @return  none
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    uint8_t tmppre = 0;
+
+    if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+        else
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
+    }
+
+    if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_opa.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_opa.c
new file mode 100644
index 0000000000..36aa3f2db5
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_opa.c
@@ -0,0 +1,84 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_opa.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the OPA firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32v20x_opa.h"
+
+#define OPA_MASK         ((uint32_t)0x000F)
+#define OPA_Total_NUM    4
+
+/*********************************************************************
+ * @fn      OPA_DeInit
+ *
+ * @brief   Deinitializes the OPA peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void OPA_DeInit(void)
+{
+    OPA->CR = 0;
+}
+
+/*********************************************************************
+ * @fn      OPA_Init
+ *
+ * @brief   Initializes the OPA peripheral according to the specified
+ *        parameters in the OPA_InitStruct.
+ *
+ * @param   OPA_InitStruct - pointer to a OPA_InitTypeDef structure
+ *
+ * @return  none
+ */
+void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
+{
+    uint32_t tmp = 0;
+    tmp = OPA->CR;
+    tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
+    tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
+    OPA->CR = tmp;
+}
+
+/*********************************************************************
+ * @fn      OPA_StructInit
+ *
+ * @brief   Fills each OPA_StructInit member with its reset value.
+ *
+ * @param   OPA_StructInit - pointer to a OPA_InitTypeDef structure
+ *
+ * @return  none
+ */
+void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
+{
+    OPA_InitStruct->Mode = OUT_IO_OUT1;
+    OPA_InitStruct->PSEL = CHP0;
+    OPA_InitStruct->NSEL = CHN0;
+    OPA_InitStruct->OPA_NUM = OPA1;
+}
+
+/*********************************************************************
+ * @fn      OPA_Cmd
+ *
+ * @brief   Enables or disables the specified OPA peripheral.
+ *
+ * @param   OPA_NUM - Select OPA
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
+{
+    if(NewState == ENABLE)
+    {
+        OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
+    }
+    else
+    {
+        OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
+    }
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_pwr.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_pwr.c
new file mode 100644
index 0000000000..e17fdbe43a
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_pwr.c
@@ -0,0 +1,400 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_pwr.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the PWR firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+
+/* PWR registers bit mask */
+/* CTLR register bit mask */
+#define CTLR_DS_MASK     ((uint32_t)0xFFFFFFFC)
+#define CTLR_PLS_MASK    ((uint32_t)0xFFFFFF1F)
+
+/*********************************************************************
+ * @fn      PWR_DeInit
+ *
+ * @brief   Deinitializes the PWR peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void PWR_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      PWR_BackupAccessCmd
+ *
+ * @brief   Enables or disables access to the RTC and backup registers.
+ *
+ * @param   NewState - new state of the access to the RTC and backup registers,
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDCmd
+ *
+ * @brief   Enables or disables the Power Voltage Detector(PVD).
+ *
+ * @param   NewState - new state of the PVD(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 4);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 4);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDLevelConfig
+ *
+ * @brief   Configures the voltage threshold detected by the Power Voltage
+ *        Detector(PVD).
+ *
+ * @param   PWR_PVDLevel - specifies the PVD detection level
+ *            PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
+ *            PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
+ *            PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
+ *            PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
+ *            PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
+ *            PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
+ *            PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
+ *            PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
+ *
+ * @return  none
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_PLS_MASK;
+    tmpreg |= PWR_PVDLevel;
+    PWR->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      PWR_WakeUpPinCmd
+ *
+ * @brief   Enables or disables the WakeUp Pin functionality.
+ *
+ * @param   NewState - new state of the WakeUp Pin functionality
+ *        (ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CSR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CSR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode
+ *
+ * @brief   Enters STOP mode.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    NVIC->SCTLR &= ~(1 << 2);
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode
+ *
+ * @brief   Enters STANDBY mode.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+    PWR->CTLR |= PWR_CTLR_CWUF;
+    PWR->CTLR |= PWR_CTLR_PDDS;
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_GetFlagStatus
+ *
+ * @brief   Checks whether the specified PWR flag is set or not.
+ *
+ * @param   PWR_FLAG - specifies the flag to check.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *            PWR_FLAG_PVDO - PVD Output
+ *
+ * @return  none
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      PWR_ClearFlag
+ *
+ * @brief   Clears the PWR's pending flags.
+ *
+ * @param   PWR_FLAG - specifies the flag to clear.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *
+ * @return  none
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+    PWR->CTLR |= PWR_FLAG << 2;
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function on.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    //2K+30K in standby w power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+#else
+    //RAM in standby power.
+    tmpreg |= ( ( uint32_t )1 << 16 );
+
+#endif
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_LV
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function and LV mode on.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_LV(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    //2K+30K in standby power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+#else
+    //RAM in standby power.
+    tmpreg |= ( ( uint32_t )1 << 16 );
+    //RAM in standby LV .
+    tmpreg |= ( ( uint32_t )1 << 20 );
+
+#endif
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_VBAT_EN
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function on (VBAT Enable).
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    //2K+30K in standby power (VBAT Enable).
+    tmpreg |= (0x1 << 18) | (0x1 << 19);
+#else
+      //RAM in standby w power.
+    tmpreg |= ( ( uint32_t )1 << 18 );
+
+#endif
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    //2K+30K in standby power (VBAT Enable).
+    tmpreg |= (0x1 << 18) | (0x1 << 19);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+#else
+      //RAM in standby w power.
+    tmpreg |= ( ( uint32_t )1 << 18 );
+    //RAM in standby LV .
+    tmpreg |= ( ( uint32_t )1 << 20 );
+
+#endif
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode_RAM_LV
+ *
+ * @brief   Enters STOP mode with RAM data retention function and LV mode on.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+    //2K+30K in standby power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+#else
+    //RAM in standby power.
+    tmpreg |= ( ( uint32_t )1 << 16 );
+    //RAM in standby LV .
+    tmpreg |= ( ( uint32_t )1 << 20 );
+
+#endif
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    NVIC->SCTLR &= ~(1 << 2);
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rcc.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rcc.c
new file mode 100644
index 0000000000..261c9082c1
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rcc.c
@@ -0,0 +1,1018 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_rcc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/ 
+#include "ch32v20x_rcc.h"
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* BDCTLR Register */
+#define BDCTLR_OFFSET             (RCC_OFFSET + 0x20)
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set             ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set              ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask              ((uint32_t)0xFFC0FFFF) 
+
+#define CFGR0_PLLMull_Mask          ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask           ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask         ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask              ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask               ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask       ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask         ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask      ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask        ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask      ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask        ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask     ((uint32_t)0xFFFF3FFF)
+#define CFGR0_ADCPRE_Set_Mask       ((uint32_t)0x0000C000)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set            ((uint32_t)0x01000000)
+
+/* CFGR2 register bit mask */
+#define CFGR2_PREDIV1SRC            ((uint32_t)0x00010000)
+#define CFGR2_PREDIV1               ((uint32_t)0x0000000F)
+#define CFGR2_PREDIV2               ((uint32_t)0x000000F0)
+#define CFGR2_PLL2MUL               ((uint32_t)0x00000F00)
+#define CFGR2_PLL3MUL               ((uint32_t)0x0000F000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                   ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS          ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS          ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS         ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS              (PERIPH_BASE + BDCTLR_OFFSET)
+
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/*********************************************************************
+ * @fn      RCC_DeInit
+ *
+ * @brief   Resets the RCC clock configuration to the default reset state.
+ *
+ * @return  none
+ */
+void RCC_DeInit(void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;  
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSEConfig
+ *
+ * @brief   Configures the External High Speed oscillator (HSE).
+ *
+ * @param   RCC_HSE -
+ *            RCC_HSE_OFF - HSE oscillator OFF.
+ *            RCC_HSE_ON - HSE oscillator ON.
+ *            RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+  RCC->CTLR &= CTLR_HSEON_Reset;
+  RCC->CTLR &= CTLR_HSEBYP_Reset;
+
+  switch(RCC_HSE)
+  {
+    case RCC_HSE_ON:
+      RCC->CTLR |= CTLR_HSEON_Set;
+      break;
+      
+    case RCC_HSE_Bypass:
+      RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
+      break;
+      
+    default:
+      break;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_WaitForHSEStartUp
+ *
+ * @brief   Waits for HSE start-up.
+ *
+ * @return  SUCCESS - HSE oscillator is stable and ready to use.
+ *                  ERROR - HSE oscillator not yet ready.
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+	
+  ErrorStatus status = NoREADY;
+  FlagStatus HSEStatus = RESET;
+  
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;  
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = READY;
+  }
+  else
+  {
+    status = NoREADY;
+  }  
+	
+  return (status);
+}
+
+/*********************************************************************
+ * @fn      RCC_AdjustHSICalibrationValue
+ *
+ * @brief   Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ *
+ * @param   HSICalibrationValue - specifies the calibration trimming value.
+ *                    This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CTLR;
+  tmpreg &= CTLR_HSITRIM_Mask;
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+  RCC->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSICmd
+ *
+ * @brief   Enables or disables the Internal High Speed oscillator (HSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<0);
+	}
+	else{
+		RCC->CTLR &= ~(1<<0);		
+	}
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLConfig
+ *
+ * @brief   Configures the PLL clock source and multiplication factor.
+ *
+ * @param   RCC_PLLSource - specifies the PLL entry clock source.
+ *            RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *            RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock
+ *        entry.
+ *          RCC_PLLMul - specifies the PLL multiplication factor.
+ *            This parameter can be RCC_PLLMul_x where x:[2,16].
+ *              RCC_PLLMul_2
+ *              RCC_PLLMul_3
+ *              RCC_PLLMul_4
+ *              RCC_PLLMul_5
+ *              RCC_PLLMul_6
+ *              RCC_PLLMul_7
+ *              RCC_PLLMul_8
+ *              RCC_PLLMul_9
+ *              RCC_PLLMul_10
+ *              RCC_PLLMul_11
+ *              RCC_PLLMul_12
+ *              RCC_PLLMul_13
+ *              RCC_PLLMul_14
+ *              RCC_PLLMul_15
+ *              RCC_PLLMul_16
+ *              RCC_PLLMul_18
+ *
+ * @return  none
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+
+  tmpreg &= CFGR0_PLL_Mask;
+  tmpreg |= RCC_PLLSource | RCC_PLLMul;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLCmd
+ *
+ * @brief   Enables or disables the PLL.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<24);
+	}
+	else{
+		RCC->CTLR &= ~(1<<24);		
+	}
+}
+
+/*********************************************************************
+ * @fn      RCC_SYSCLKConfig
+ *
+ * @brief   Configures the system clock (SYSCLK).
+ *
+ * @param   RCC_SYSCLKSource - specifies the clock source used as system clock.
+ *            RCC_SYSCLKSource_HSI - HSI selected as system clock.
+ *            RCC_SYSCLKSource_HSE - HSE selected as system clock.
+ *            RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
+ *
+ * @return  none
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_SW_Mask;
+  tmpreg |= RCC_SYSCLKSource;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetSYSCLKSource
+ *
+ * @brief   Returns the clock source used as system clock.
+ *
+ * @return  0x00 - HSI used as system clock.
+ *          0x04 - HSE used as system clock.
+ *          0x08 - PLL used as system clock.
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
+}
+
+/*********************************************************************
+ * @fn      RCC_HCLKConfig
+ *
+ * @brief   Configures the AHB clock (HCLK).
+ *
+ * @param   RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
+ *        the system clock (SYSCLK).
+ *            RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
+ *            RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
+ *            RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
+ *            RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
+ *            RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
+ *            RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
+ *            RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
+ *            RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
+ *            RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
+ *
+ * @return  none
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_HPRE_Reset_Mask;
+  tmpreg |= RCC_SYSCLK;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK1Config
+ *
+ * @brief   Configures the Low Speed APB clock (PCLK1).
+ *
+ * @param   RCC_HCLK - defines the APB1 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_PPRE1_Reset_Mask;
+  tmpreg |= RCC_HCLK;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK2Config
+ *
+ * @brief   Configures the High Speed APB clock (PCLK2).
+ *
+ * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_PCLK2_Div2 - APB2 clock = HCLK.
+ *            RCC_PCLK2_Div4 - APB2 clock = HCLK/2.
+ *            RCC_PCLK2_Div6 - APB2 clock = HCLK/4.
+ *            RCC_PCLK2_Div8 - APB2 clock = HCLK/8.
+ *
+ * @return  none
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_PPRE2_Reset_Mask;
+  tmpreg |= RCC_HCLK << 3;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_ITConfig
+ *
+ * @brief   Enables or disables the specified RCC interrupts.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBCLKConfig
+ *
+ * @brief   Configures the USB clock (USBCLK).
+ *
+ * @param    RCC_USBCLKSource: specifies the USB clock source. This clock is
+ *        derived from the PLL output.
+ *             RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz).
+ *             RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz).
+ *             RCC_USBCLKSource_PLLCLK_Div3 - PLL clock selected as USB clock source(144MHz).
+ *             RCC_USBCLKSource_PLLCLK_Div5 - PLL clock selected as USB clock source(240MHz).
+ *
+ * @return  none
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+    RCC->CFGR0 &= ~((uint32_t)3<<22);
+    RCC->CFGR0 |= RCC_USBCLKSource<<22;
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKConfig
+ *
+ * @brief   Configures the ADC clock (ADCCLK).
+ *
+ * @param   RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
+ *        the APB2 clock (PCLK2).
+ *          RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
+ *          RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
+ *          RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
+ *          RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_ADCPRE_Reset_Mask;
+  tmpreg |= RCC_PCLK2;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_LSEConfig
+ *
+ * @brief   Configures the External Low Speed oscillator (LSE).
+ *
+ * @param   RCC_LSE - specifies the new state of the LSE.
+ *            RCC_LSE_OFF - LSE oscillator OFF.
+ *            RCC_LSE_ON - LSE oscillator ON.
+ *            RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+  *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
+  *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
+	
+  switch(RCC_LSE)
+  {
+    case RCC_LSE_ON:
+      *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON;
+      break;
+      
+    case RCC_LSE_Bypass:
+      *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+      break;            
+      
+    default:
+      break;      
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_LSICmd
+ *
+ * @brief   Enables or disables the Internal Low Speed oscillator (LSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->RSTSCKR |= (1<<0);
+	}
+	else{
+		RCC->RSTSCKR &= ~(1<<0);		
+	}	
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKConfig
+ *
+ * @brief   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ *
+ * @param   RCC_RTCCLKSource - specifies the RTC clock source.
+ *            RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
+ *            RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
+ *            RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  RCC->BDCTLR |= RCC_RTCCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKCmd
+ *
+ * @brief   This function must be used only after the RTC clock was selected
+ *        using the RCC_RTCCLKConfig function.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->BDCTLR |= (1<<15);
+	}
+	else{
+		RCC->BDCTLR &= ~(1<<15);		
+	}	
+}
+
+/*********************************************************************
+ * @fn      RCC_GetClocksFreq
+ *
+ * @brief   The result of this function could be not correct when using
+ *        fractional value for HSE crystal.
+ *
+ * @param   RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
+ *        the clocks frequencies.
+ *
+ * @return  none
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+    tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
+
+    switch (tmp)
+    {
+      case 0x00:
+        RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+        break;
+
+      case 0x04:
+        RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+        break;
+
+      case 0x08:
+        pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
+        pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
+
+        pllmull = ( pllmull >> 18) + 2;
+
+        if(pllmull == 17) pllmull = 18;
+
+
+        if (pllsource == 0x00)
+        {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull;
+          }
+          else{
+              RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull;
+          }
+        }
+        else
+        {
+#if defined (CH32V20x_D8W)
+          if((RCC->CFGR0 & (3<<22)) == (3<<22))
+          {
+              RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>1)) * pllmull;
+          }
+          else
+#endif
+          if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
+          {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+              RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+            RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+#endif
+          }
+          else
+          {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+              RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE>>2) * pllmull;
+#else
+            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+#endif
+
+          }
+        }
+
+        break;
+
+      default:
+        RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+        break;
+    }
+
+    tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphClockCmd
+ *
+ * @brief   Enables or disables the AHB peripheral clock.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
+ *            RCC_AHBPeriph_DMA1.
+ *            RCC_AHBPeriph_DMA2.
+ *            RCC_AHBPeriph_SRAM.
+ *            RCC_AHBPeriph_CRC.
+ *            RCC_AHBPeriph_OTG_FS
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->AHBPCENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBPCENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphClockCmd
+ *
+ * @brief   Enables or disables the High Speed APB (APB2) peripheral clock.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB2PCENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2PCENR &= ~RCC_APB2Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphClockCmd
+ *
+ * @brief   Enables or disables the Low Speed APB (APB1) peripheral clock.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB1PCENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1PCENR &= ~RCC_APB1Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphResetCmd
+ *
+ * @brief   Forces or releases High Speed APB (APB2) peripheral reset.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to reset.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB2PRSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2PRSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphResetCmd
+ *
+ * @brief   Forces or releases Low Speed APB (APB1) peripheral reset.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to reset.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB1PRSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1PRSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_BackupResetCmd
+ *
+ * @brief   Forces or releases the Backup domain reset.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->BDCTLR |= (1<<16);
+	}
+	else{
+		RCC->BDCTLR &= ~(1<<16);		
+	}		
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ClockSecuritySystemCmd
+* Description    : Enables or disables the Clock Security System.
+* Input          : NewState: ENABLE or DISABLE.
+* Return         : None
+*******************************************************************************/	
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<19);
+	}
+	else{
+		RCC->CTLR &= ~(1<<19);		
+	}		
+}
+
+/*********************************************************************
+ * @fn      RCC_MCOConfig
+ *
+ * @brief   Selects the clock source to output on MCO pin.
+ *
+ * @param   RCC_MCO - specifies the clock source to output.
+ *            RCC_MCO_NoClock - No clock selected.
+ *            RCC_MCO_SYSCLK - System clock selected.
+ *            RCC_MCO_HSI - HSI oscillator clock selected.
+ *            RCC_MCO_HSE - HSE oscillator clock selected.
+ *            RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
+ *
+ * @return  none
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+  *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RCC flag is set or not.
+ *
+ * @param   RCC_FLAG - specifies the flag to check.
+ *            RCC_FLAG_HSIRDY - HSI oscillator clock ready.
+ *            RCC_FLAG_HSERDY - HSE oscillator clock ready.
+ *            RCC_FLAG_PLLRDY - PLL clock ready.
+ *            RCC_FLAG_PLL2RDY - PLL2 clock ready.
+ *            RCC_FLAG_PLL3RDY - PLL3 clock ready.
+ *            RCC_FLAG_LSERDY - LSE oscillator clock ready.
+ *            RCC_FLAG_LSIRDY - LSI oscillator clock ready.
+ *            RCC_FLAG_PINRST - Pin reset.
+ *            RCC_FLAG_PORRST - POR/PDR reset.
+ *            RCC_FLAG_SFTRST - Software reset.
+ *            RCC_FLAG_IWDGRST - Independent Watchdog reset.
+ *            RCC_FLAG_WWDGRST - Window Watchdog reset.
+ *            RCC_FLAG_LPWRRST - Low Power reset.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+	
+  FlagStatus bitstatus = RESET;
+  tmp = RCC_FLAG >> 5;
+	
+  if (tmp == 1)            
+  {
+    statusreg = RCC->CTLR;
+  }
+  else if (tmp == 2)       
+  {
+    statusreg = RCC->BDCTLR;
+  }
+  else                    
+  {
+    statusreg = RCC->RSTSCKR;
+  }
+
+  tmp = RCC_FLAG & FLAG_Mask;
+	
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearFlag
+ *
+ * @brief   Clears the RCC reset flags.
+ *
+ * @return  none
+ */
+void RCC_ClearFlag(void)
+{
+  RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetITStatus
+ *
+ * @brief   Checks whether the specified RCC interrupt has occurred or not.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt source to check.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  if ((RCC->INTR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearITPendingBit
+ *
+ * @brief   Clears the RCC's interrupt pending bits.
+ *
+ * @param   RCC_IT - specifies the interrupt pending bit to clear.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  none
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKADJcmd
+ *
+ * @brief   Enable ADC clock duty cycle adjustment.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKADJcmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->CFGR0 |= (1<<31);
+  }
+  else
+  {
+    RCC->CFGR0 &= ~(1<<31);
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_ETHDIVConfig
+ *
+ * @brief   Configures the ETH clock.
+ *
+ * @param   RCC_ETHPRE_Div - defines the USBHS clock divider.
+ *            RCC_ETHCLK_Div1 - ETH clock = AHB/1.
+ *            RCC_ETHCLK_Div2 - ETH clock = AHB/2.
+ *
+ * @return  none
+ */
+void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div)
+{
+    RCC->CFGR0 &= ~((uint32_t)1<<28);
+    RCC->CFGR0 |= RCC_ETHPRE_Div<<28;
+}
+
+
+
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rtc.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rtc.c
new file mode 100644
index 0000000000..816d48781f
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_rtc.c
@@ -0,0 +1,373 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_rtc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the RTC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+#include "ch32v20x_rtc.h"
+
+/* RTC_Private_Defines */
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
+
+/*********************************************************************
+ * @fn      RTC_ITConfig
+ *
+ * @brief   Enables or disables the specified RTC interrupts.
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
+ *            RTC_IT_OW - Overflow interrupt
+ *            RTC_IT_ALR - Alarm interrupt
+ *            RTC_IT_SEC - Second interrupt
+ *
+ * @return  NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RTC->CTLRH |= RTC_IT;
+    }
+    else
+    {
+        RTC->CTLRH &= (uint16_t)~RTC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_EnterConfigMode
+ *
+ * @brief   Enters the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_EnterConfigMode(void)
+{
+    RTC->CTLRL |= RTC_CTLRL_CNF;
+}
+
+/*********************************************************************
+ * @fn      RTC_ExitConfigMode
+ *
+ * @brief   Exits from the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_ExitConfigMode(void)
+{
+    RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
+}
+
+/*********************************************************************
+ * @fn      RTC_GetCounter
+ *
+ * @brief   Gets the RTC counter value
+ *
+ * @return  RTC counter value
+ */
+uint32_t RTC_GetCounter(void)
+{
+    uint16_t high1 = 0, high2 = 0, low = 0;
+
+    high1 = RTC->CNTH;
+    low = RTC->CNTL;
+    high2 = RTC->CNTH;
+
+    if(high1 != high2)
+    {
+        return (((uint32_t)high2 << 16) | RTC->CNTL);
+    }
+    else
+    {
+        return (((uint32_t)high1 << 16) | low);
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_SetCounter
+ *
+ * @brief   Sets the RTC counter value.
+ *
+ * @param   CounterValue - RTC counter new value.
+ *
+ * @return  RTC counter value
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+    RTC_EnterConfigMode();
+    RTC->CNTH = CounterValue >> 16;
+    RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetPrescaler
+ *
+ * @brief   Sets the RTC prescaler value
+ *
+ * @param   PrescalerValue - RTC prescaler new value
+ *
+ * @return  none
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+    RTC_EnterConfigMode();
+    RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+    RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetAlarm
+ *
+ * @brief   Sets the RTC alarm value
+ *
+ * @param   AlarmValue - RTC alarm new value
+ *
+ * @return  none
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+    RTC_EnterConfigMode();
+    RTC->ALRMH = AlarmValue >> 16;
+    RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_GetDivider
+ *
+ * @brief   Gets the RTC divider value
+ *
+ * @return  RTC Divider value
+ */
+uint32_t RTC_GetDivider(void)
+{
+    uint32_t tmp = 0x00;
+    tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+    tmp |= RTC->DIVL;
+    return tmp;
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForLastTask
+ *
+ * @brief   Waits until last write operation on RTC registers has finished
+ *
+ * @return  none
+ */
+void RTC_WaitForLastTask(void)
+{
+    while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForSynchro
+ *
+ * @brief   Waits until the RTC registers are synchronized with RTC APB clock
+ *
+ * @return  none
+ */
+void RTC_WaitForSynchro(void)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
+    while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RTC flag is set or not
+ *
+ * @param   RTC_FLAG- specifies the flag to check
+ *            RTC_FLAG_RTOFF - RTC Operation OFF flag
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearFlag
+ *
+ * @brief   Clears the RTC's pending flags
+ *
+ * @param   RTC_FLAG - specifies the flag to clear
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      RTC_GetITStatus
+ *
+ * @brief   Checks whether the specified RTC interrupt has occurred or not
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to check
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  The new state of the RTC_IT (SET or RESET)
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
+    if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearITPendingBit
+ *
+ * @brief   Clears the RTC's interrupt pending bits
+ *
+ * @param   RTC_IT - specifies the interrupt pending bit to clear
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  none
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_IT;
+}
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+/*******************************************************************************
+ * @fn            Calibration_LSI
+ *
+ * @brief         LSI calibration
+ *
+ * @param         cali_Lv : calibration level
+ *                Level_32  -   1.2ms 1100ppm
+ *                Level_64  -   2.2ms 1000ppm
+ *                Level_128 -   4.2ms 800ppm
+ *
+ * @return        None
+ */
+void Calibration_LSI(Cali_LevelTypeDef cali_Lv)
+{
+    uint32_t i;
+    int32_t  cnt_offset;
+    int32_t  Freq = 0;
+    uint8_t  retry = 0;
+    uint32_t cnt_32k = 0;
+    Freq = SystemCoreClock;
+    // Coarse tuning
+    OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
+    OSC->LSI32K_CAL_CFG |= 0;
+    while(1)
+    {
+        OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+        OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+        OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+        while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+        i = OSC->LSI32K_CAL_STATR;
+        OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+        OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+        OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+        OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+        cnt_32k = RTC_GetCounter();
+        while(RTC_GetCounter() == cnt_32k);
+        OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+        while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
+        while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+        i = OSC->LSI32K_CAL_STATR;
+        cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ;
+        if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2)
+            break;
+        retry++;
+        cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2;
+        OSC->LSI32K_TUNE += cnt_offset;
+    }
+    OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
+    OSC->LSI32K_CAL_CFG |= 2;
+    OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+
+    // Fine tuning
+    // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
+    while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+    i = OSC->LSI32K_CAL_STATR;
+    OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+    cnt_32k = RTC_GetCounter();
+    while(RTC_GetCounter() == cnt_32k);
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+    while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
+    while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+    i = OSC->LSI32K_CAL_STATR;
+    cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
+    cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5;
+    OSC->LSI32K_TUNE += cnt_offset;
+    OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
+    OSC->LSI32K_CAL_CFG |= cali_Lv;
+    OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+    // Fine tuning
+    // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
+    while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+    i = OSC->LSI32K_CAL_STATR;
+    OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+    cnt_32k = RTC_GetCounter();
+    while(RTC_GetCounter() == cnt_32k);
+    OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
+    while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
+    while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
+    OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
+    i = OSC->LSI32K_CAL_STATR;
+    cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
+    cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5;
+    OSC->LSI32K_TUNE += cnt_offset;
+}
+
+#endif
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_spi.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_spi.c
new file mode 100644
index 0000000000..1f3f3f0b99
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_spi.c
@@ -0,0 +1,638 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_spi.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the SPI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v20x_spi.h"
+#include "ch32v20x_rcc.h"
+
+/* SPI SPE mask */
+#define CTLR1_SPE_Set         ((uint16_t)0x0040)
+#define CTLR1_SPE_Reset       ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set      ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset    ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTLR1_CRCNext_Set     ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTLR1_CRCEN_Set       ((uint16_t)0x2000)
+#define CTLR1_CRCEN_Reset     ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTLR2_SSOE_Set        ((uint16_t)0x0004)
+#define CTLR2_SSOE_Reset      ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTLR1_CLEAR_Mask      ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask    ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select       ((uint16_t)0xF7FF)
+#define I2S_Mode_Select       ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC        ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC        ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK          ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK          ((uint32_t)(0x000000F0))
+
+/*********************************************************************
+ * @fn      SPI_I2S_DeInit
+ *
+ * @brief   Deinitializes the SPIx peripheral registers to their default
+ *        reset values (Affects also the I2Ss).
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+    if(SPIx == SPI1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+    }
+    else if(SPIx == SPI2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the SPI_InitStruct.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = SPIx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                         SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+                         SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+                         SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+
+    SPIx->CTLR1 = tmpreg;
+    SPIx->I2SCFGR &= SPI_Mode_Select;
+    SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/*********************************************************************
+ * @fn      I2S_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the I2S_InitStruct.
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *        (configured in I2S mode).
+ *          I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral
+ *        configured in I2S mode.
+ * @return  none
+ */
+void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    uint16_t          tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+    uint32_t          tmp = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+    uint32_t          sourceclock = 0;
+
+    SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+    SPIx->I2SPR = 0x0002;
+    tmpreg = SPIx->I2SCFGR;
+
+    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+    {
+        i2sodd = (uint16_t)0;
+        i2sdiv = (uint16_t)2;
+    }
+    else
+    {
+        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+        {
+            packetlength = 1;
+        }
+        else
+        {
+            packetlength = 2;
+        }
+
+        if(((uint32_t)SPIx) == SPI2_BASE)
+        {
+            tmp = I2S2_CLOCK_SRC;
+        }
+        else
+        {
+            tmp = I2S3_CLOCK_SRC;
+        }
+
+        RCC_GetClocksFreq(&RCC_Clocks);
+
+        sourceclock = RCC_Clocks.SYSCLK_Frequency;
+
+        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+        {
+            tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+        else
+        {
+            tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+
+        tmp = tmp / 10;
+        i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+        i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+        i2sodd = (uint16_t)(i2sodd << 8);
+    }
+
+    if((i2sdiv < 2) || (i2sdiv > 0xFF))
+    {
+        i2sdiv = 2;
+        i2sodd = 0;
+    }
+
+    SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+    tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
+                                                      (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
+                                                                                                           (uint16_t)I2S_InitStruct->I2S_CPOL))));
+    SPIx->I2SCFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_StructInit
+ *
+ * @brief   Fills each SPI_InitStruct member with its default value.
+ *
+ * @param   SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+    SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/*********************************************************************
+ * @fn      I2S_StructInit
+ *
+ * @brief   Fills each I2S_InitStruct member with its default value.
+ *
+ * @param   I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+    I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+    I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/*********************************************************************
+ * @fn      SPI_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_SPE_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_SPE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2S_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral (in I2S mode).
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+    }
+    else
+    {
+        SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ITConfig
+ *
+ * @brief   Enables or disables the specified SPI/I2S interrupts.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
+ *        enabled or disabled.
+ *            SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
+ *            SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
+ *            SPI_I2S_IT_ERR - Error interrupt mask.
+ *          NewState: ENABLE or DISABLE.
+ * @return  none
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+    uint16_t itpos = 0, itmask = 0;
+
+    itpos = SPI_I2S_IT >> 4;
+    itmask = (uint16_t)1 << (uint16_t)itpos;
+
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= itmask;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_DMACmd
+ *
+ * @brief   Enables or disables the SPIx/I2Sx DMA interface.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
+ *        be enabled or disabled.
+ *            SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
+ *            SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= SPI_I2S_DMAReq;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_SendData
+ *
+ * @brief   Transmits a Data through the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  none
+ */
+void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
+{
+    SPIx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  SPIx->DATAR - The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
+{
+    return SPIx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      SPI_NSSInternalSoftwareConfig
+ *
+ * @brief   Configures internally by software the NSS pin for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_NSSInternalSoft -
+ *            SPI_NSSInternalSoft_Set - Set NSS pin internally.
+ *            SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
+ *
+ * @return  none
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
+{
+    if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+    {
+        SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_SSOutputCmd
+ *
+ * @brief   Enables or disables the SS output for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx SS output.
+ *
+ * @return  none
+ */
+void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= CTLR2_SSOE_Set;
+    }
+    else
+    {
+        SPIx->CTLR2 &= CTLR2_SSOE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_DataSizeConfig
+ *
+ * @brief   Configures the data size for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_DataSize - specifies the SPI data size.
+ *            SPI_DataSize_16b - Set data frame format to 16bit.
+ *            SPI_DataSize_8b - Set data frame format to 8bit.
+ *
+ * @return  none
+ */
+void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
+{
+    SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
+    SPIx->CTLR1 |= SPI_DataSize;
+}
+
+/*********************************************************************
+ * @fn      SPI_TransmitCRC
+ *
+ * @brief   Transmit the SPIx CRC value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_TransmitCRC(SPI_TypeDef *SPIx)
+{
+    SPIx->CTLR1 |= CTLR1_CRCNext_Set;
+}
+
+/*********************************************************************
+ * @fn      SPI_CalculateCRC
+ *
+ * @brief   Enables or disables the CRC value calculation of the transferred bytes.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx CRC value calculation.
+ *
+ * @return  none
+ */
+void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_CRCEN_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRC
+ *
+ * @brief   Returns the transmit or the receive CRC register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_CRC - specifies the CRC register to be read.
+ *            SPI_CRC_Tx - Selects Tx CRC register.
+ *            SPI_CRC_Rx - Selects Rx CRC register.
+ *
+ * @return  crcreg: The selected CRC register value.
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
+{
+    uint16_t crcreg = 0;
+
+    if(SPI_CRC != SPI_CRC_Rx)
+    {
+        crcreg = SPIx->TCRCR;
+    }
+    else
+    {
+        crcreg = SPIx->RCRCR;
+    }
+
+    return crcreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRCPolynomial
+ *
+ * @brief   Returns the CRC Polynomial register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  SPIx->CRCR - The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+    return SPIx->CRCR;
+}
+
+/*********************************************************************
+ * @fn      SPI_BiDirectionalLineConfig
+ *
+ * @brief   Selects the data transfer direction in bi-directional mode
+ *      for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_Direction - specifies the data transfer direction in
+ *        bi-directional mode.
+ *            SPI_Direction_Tx - Selects Tx transmission direction.
+ *            SPI_Direction_Rx - Selects Rx receive direction.
+ *
+ * @return  none
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
+{
+    if(SPI_Direction == SPI_Direction_Tx)
+    {
+        SPIx->CTLR1 |= SPI_Direction_Tx;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_Direction_Rx;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetFlagStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S flag is set or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
+ *            SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
+ *            SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
+ *            SPI_I2S_FLAG_BSY - Busy flag.
+ *            SPI_I2S_FLAG_OVR - Overrun flag.
+ *            SPI_FLAG_MODF - Mode Fault flag.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *            I2S_FLAG_UDR - Underrun Error flag.
+ *            I2S_FLAG_CHSIDE - Channel Side flag.
+ *
+ * @return  none
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearFlag
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) flag.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI flag to clear.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetITStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S interrupt has occurred or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
+ *            SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
+ *            SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
+ *            SPI_I2S_IT_OVR - Overrun interrupt.
+ *            SPI_IT_MODF - Mode Fault interrupt.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *            I2S_IT_UDR - Underrun Error interrupt.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    itmask = SPI_I2S_IT >> 4;
+    itmask = 0x01 << itmask;
+    enablestatus = (SPIx->CTLR2 & itmask);
+
+    if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearITPendingBit
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *          SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    uint16_t itpos = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    SPIx->STATR = (uint16_t)~itpos;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_tim.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_tim.c
new file mode 100644
index 0000000000..523bac5b4f
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_tim.c
@@ -0,0 +1,2351 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_tim.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the TIM firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_tim.h"
+#include "ch32v20x_rcc.h"
+
+/* TIM registers bit mask */
+#define SMCFGR_ETR_Mask    ((uint16_t)0x00FF)
+#define CHCTLR_Offset      ((uint16_t)0x0018)
+#define CCER_CCE_Set       ((uint16_t)0x0001)
+#define CCER_CCNE_Set      ((uint16_t)0x0004)
+
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+
+/*********************************************************************
+ * @fn      TIM_DeInit
+ *
+ * @brief   Deinitializes the TIMx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_DeInit(TIM_TypeDef *TIMx)
+{
+    if(TIMx == TIM1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+    }
+    else if(TIMx == TIM2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+    }
+    else if(TIMx == TIM3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+    }
+    else if(TIMx == TIM4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+    }
+    else if(TIMx == TIM5)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseInit
+ *
+ * @brief   Initializes the TIMx Time Base Unit peripheral according to
+ *        the specified parameters in the TIM_TimeBaseInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef
+ *        structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+    {
+        tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+    }
+
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+
+    TIMx->CTLR1 = tmpcr1;
+    TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period;
+    TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+    if((TIMx == TIM1))
+    {
+        TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+    }
+
+    TIMx->SWEVGR = TIM_PSCReloadMode_Immediate;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1Init
+ *
+ * @brief   Initializes the TIMx Channel1 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E);
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P));
+    tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+    tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+    if((TIMx == TIM1))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP));
+        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE));
+        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N));
+
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2Init
+ *
+ * @brief   Initializes the TIMx Channel2 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+    if((TIMx == TIM1))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3Init
+ *
+ * @brief   Initializes the TIMx Channel3 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+    if((TIMx == TIM1))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4Init
+ *
+ * @brief   Initializes the TIMx Channel4 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+    if((TIMx == TIM1))
+    {
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICInit
+ *
+ * @brief   IInitializes the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct.
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+    {
+        TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_PWMIConfig
+ *
+ * @brief   Configures the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct to measure an external
+ *        PWM signal.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+    uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+    if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+    {
+        icoppositepolarity = TIM_ICPolarity_Falling;
+    }
+    else
+    {
+        icoppositepolarity = TIM_ICPolarity_Rising;
+    }
+
+    if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+    {
+        icoppositeselection = TIM_ICSelection_IndirectTI;
+    }
+    else
+    {
+        icoppositeselection = TIM_ICSelection_DirectTI;
+    }
+
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRConfig
+ *
+ * @brief   Configures the: Break feature, dead time, Lock level, the OSSI,
+ *      the OSSR State and the AOE(automatic output enable).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseStructInit
+ *
+ * @brief   Fills each TIM_TimeBaseInitStruct member with its default value.
+ *
+ * @param   TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+    TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+    TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+    TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+    TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/*********************************************************************
+ * @fn      TIM_OCStructInit
+ *
+ * @brief   Fills each TIM_OCInitStruct member with its default value.
+ *
+ * @param   TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+    TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+    TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+    TIM_OCInitStruct->TIM_Pulse = 0x0000;
+    TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+    TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICStructInit
+ *
+ * @brief   Fills each TIM_ICInitStruct member with its default value.
+ *
+ * @param   TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+    TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+    TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+    TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+    TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRStructInit
+ *
+ * @brief   Fills each TIM_BDTRInitStruct member with its default value.
+ *
+ * @param   TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+    TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+    TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+    TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+    TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+    TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+    TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/*********************************************************************
+ * @fn      TIM_Cmd
+ *
+ * @brief   Enables or disables the specified TIM peripheral.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_CEN;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CtrlPWMOutputs
+ *
+ * @brief   Enables or disables the TIM peripheral Main Outputs.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->BDTR |= TIM_MOE;
+    }
+    else
+    {
+        TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_ITConfig
+ *
+ * @brief   Enables or disables the specified TIM interrupts.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupts sources to be enabled or disabled.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_IT;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_IT;
+    }
+}
+
+/*******************************************************************************
+ * @fn             TIM_GenerateEvent
+ *
+ * @brief          Configures the TIMx event to be generate by software.
+ *
+ * @param          TIMx: where x can be 1 to 4 to select the TIM peripheral.
+ *                 TIM_EventSource: specifies the event source.
+ *                 TIM_EventSource_Update: Timer update Event source.
+ *                 TIM_EventSource_CC1: Timer Capture Compare 1 Event source.
+ *                 TIM_EventSource_CC2: Timer Capture Compare 2 Event source.
+ *                 TIM_EventSource_CC3: Timer Capture Compare 3 Event source.
+ *                 TIM_EventSource_CC4: Timer Capture Compare 4 Event source.
+ *                 TIM_EventSource_COM: Timer COM event source.
+ *                 TIM_EventSource_Trigger: Timer Trigger Event source.
+ *                 TIM_EventSource_Break: Timer Break event source.
+ *
+ * @return None
+ */
+void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
+{
+    TIMx->SWEVGR = TIM_EventSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMAConfig
+ *
+ * @brief   Configures the TIMx's DMA interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMABase: DMA Base address.
+ *            TIM_DMABase_CR.
+ *            TIM_DMABase_CR2.
+ *            TIM_DMABase_SMCR.
+ *            TIM_DMABase_DIER.
+ *            TIM1_DMABase_SR.
+ *            TIM_DMABase_EGR.
+ *            TIM_DMABase_CCMR1.
+ *            TIM_DMABase_CCMR2.
+ *            TIM_DMABase_CCER.
+ *            TIM_DMABase_CNT.
+ *            TIM_DMABase_PSC.
+ *            TIM_DMABase_CCR1.
+ *            TIM_DMABase_CCR2.
+ *            TIM_DMABase_CCR3.
+ *            TIM_DMABase_CCR4.
+ *            TIM_DMABase_BDTR.
+ *            TIM_DMABase_DCR.
+ *          TIM_DMABurstLength - DMA Burst length.
+ *            TIM_DMABurstLength_1Transfer.
+ *            TIM_DMABurstLength_18Transfers.
+ *
+ * @return  none
+ */
+void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+    TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMACmd
+ *
+ * @brief   Enables or disables the TIMx's DMA Requests.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMASource - specifies the DMA Request sources.
+ *            TIM_DMA_Update - TIM update Interrupt source.
+ *            TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.
+ *            TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.
+ *            TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.
+ *            TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.
+ *            TIM_DMA_COM - TIM Commutation DMA source.
+ *            TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_DMASource;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource;
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_InternalClockConfig
+ *
+ * @brief   Configures the TIMx internal Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
+{
+    TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS));
+}
+
+/*********************************************************************
+ * @fn      TIM_ITRxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Internal Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource: Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *
+ * @return  none
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_TIxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TIxExternalCLKSource - Trigger source.
+ *            TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector.
+ *            TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1.
+ *            TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2.
+ *          TIM_ICPolarity - specifies the TIx Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *             TIM_DMA_COM - TIM Commutation DMA source.
+ *             TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          ICFilter - specifies the filter value.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+    if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+    {
+        TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+    else
+    {
+        TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+
+    TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode1Config
+ *
+ * @brief   Configures the External clock Mode1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_SlaveMode_External1;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_TS_ETRF;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode2Config
+ *
+ * @brief   Configures the External clock Mode2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    TIMx->SMCFGR |= TIM_ECE;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRConfig
+ *
+ * @brief   Configures the TIMx External Trigger (ETR).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= SMCFGR_ETR_Mask;
+    tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_PrescalerConfig
+ *
+ * @brief   Configures the TIMx Prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          Prescaler - specifies the Prescaler Register value.
+ *          TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event.
+ *            TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately.
+ *
+ * @return  none
+ */
+void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+    TIMx->PSC = Prescaler;
+    TIMx->SWEVGR = TIM_PSCReloadMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_CounterModeConfig
+ *
+ * @brief   Specifies the TIMx Counter Mode to be used.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_CounterMode - specifies the Counter Mode to be used.
+ *            TIM_CounterMode_Up - TIM Up Counting Mode.
+ *            TIM_CounterMode_Down - TIM Down Counting Mode.
+ *            TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1.
+ *            TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2.
+ *            TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3.
+ *
+ * @return  none
+ */
+void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+    tmpcr1 |= TIM_CounterMode;
+    TIMx->CTLR1 = tmpcr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectInputTrigger
+ *
+ * @brief   Selects the Input Trigger source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource - The Input Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *            TIM_TS_TI1F_ED - TI1 Edge Detector.
+ *            TIM_TS_TI1FP1 - Filtered Timer Input 1.
+ *            TIM_TS_TI2FP2 - Filtered Timer Input 2.
+ *            TIM_TS_ETRF - External Trigger input.
+ *
+ * @return  none
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_InputTriggerSource;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_EncoderInterfaceConfig
+ *
+ * @brief   Configures the TIMx Encoder Interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_EncoderMode - specifies the TIMx Encoder Mode.
+ *            TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending
+ *        on TI2FP2 level.
+ *            TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending
+ *        on TI1FP1 level.
+ *            TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and
+ *        TI2FP2 edges depending.
+ *          TIM_IC1Polarity - specifies the IC1 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TTIM_ICPolarity_Rising - IC Rising edge.
+ *          TIM_IC2Polarity - specifies the IC2 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TIM_ICPolarity_Rising - IC Rising edge.
+ *
+ * @return  none
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+    uint16_t tmpsmcr = 0;
+    uint16_t tmpccmr1 = 0;
+    uint16_t tmpccer = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_EncoderMode;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S)));
+    tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0;
+    tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P)));
+    tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+    TIMx->SMCFGR = tmpsmcr;
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC1Config
+ *
+ * @brief   Forces the TIMx output 1 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC1REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC1REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M);
+    tmpccmr1 |= TIM_ForcedAction;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC2Config
+ *
+ * @brief   Forces the TIMx output 2 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC2REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC2REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M);
+    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC3Config
+ *
+ * @brief   Forces the TIMx output 3 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC3REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC3REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M);
+    tmpccmr2 |= TIM_ForcedAction;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC4Config
+ *
+ * @brief   Forces the TIMx output 4 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC4REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC4REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M);
+    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ARRPreloadConfig
+ *
+ * @brief   Enables or disables TIMx peripheral Preload register on ARR.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_ARPE;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCOM
+ *
+ * @brief   Selects the TIM peripheral Commutation event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCUS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCCDMA
+ *
+ * @brief   Selects the TIMx peripheral Capture Compare DMA source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCDS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CCPreloadControl
+ *
+ * @brief   DSets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ *        reset values (Affects also the I2Ss).
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCPC;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE);
+    tmpccmr1 |= TIM_OCPreload;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE);
+    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR3.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE);
+    tmpccmr2 |= TIM_OCPreload;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR4.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE);
+    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 1 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE);
+    tmpccmr1 |= TIM_OCFast;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 2 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE);
+    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 3 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE);
+    tmpccmr2 |= TIM_OCFast;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 4 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE);
+    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC1Ref
+ *
+ * @brief   Clears or safeguards the OCREF1 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE);
+    tmpccmr1 |= TIM_OCClear;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC2Ref
+ *
+ * @brief   Clears or safeguards the OCREF2 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE);
+    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC3Ref
+ *
+ * @brief   Clears or safeguards the OCREF3 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE);
+    tmpccmr2 |= TIM_OCClear;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC4Ref
+ *
+ * @brief   Clears or safeguards the OCREF4 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE);
+    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC1 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P);
+    tmpccer |= TIM_OCPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP);
+    tmpccer |= TIM_OCNPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC2 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3NPolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3N polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC2N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 4 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel x.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_CCx - specifies the TIM Channel CCxE bit new state.
+ *            TIM_CCx_Enable.
+ *            TIM_CCx_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxNCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel xN.
+ *
+ * @param   TIMx - where x can be 1 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *          TIM_CCxN - specifies the TIM Channel CCxNE bit new state.
+ *            TIM_CCxN_Enable.
+ *            TIM_CCxN_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCNE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOCxM
+ *
+ * @brief   Selects the TIM Output Compare Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_OCMode - specifies the TIM Output Compare Mode.
+ *            TIM_OCMode_Timing.
+ *            TIM_OCMode_Active.
+ *            TIM_OCMode_Toggle.
+ *            TIM_OCMode_PWM1.
+ *            TIM_OCMode_PWM2.
+ *            TIM_ForcedAction_Active.
+ *            TIM_ForcedAction_InActive.
+ *
+ * @return  none
+ */
+void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+    uint32_t tmp = 0;
+    uint16_t tmp1 = 0;
+
+    tmp = (uint32_t)TIMx;
+    tmp += CHCTLR_Offset;
+    tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp1;
+
+    if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3))
+    {
+        tmp += (TIM_Channel >> 1);
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M);
+        *(__IO uint32_t *)tmp |= TIM_OCMode;
+    }
+    else
+    {
+        tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1;
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M);
+        *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateDisableConfig
+ *
+ * @brief   Enables or Disables the TIMx Update event.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_UDIS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateRequestConfig
+ *
+ * @brief   Configures the TIMx Update Request Interrupt source.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_UpdateSource - specifies the Update source.
+ *            TIM_UpdateSource_Regular.
+ *            TIM_UpdateSource_Global.
+ *
+ * @return  none
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
+{
+    if(TIM_UpdateSource != TIM_UpdateSource_Global)
+    {
+        TIMx->CTLR1 |= TIM_URS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectHallSensor
+ *
+ * @brief   Enables or disables the TIMx's Hall sensor interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_TI1S;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOnePulseMode
+ *
+ * @brief   Selects the TIMx's One Pulse Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OPMode - specifies the OPM Mode to be used.
+ *            TIM_OPMode_Single.
+ *            TIM_OPMode_Repetitive.
+ *
+ * @return  none
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
+    TIMx->CTLR1 |= TIM_OPMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOutputTrigger
+ *
+ * @brief   Selects the TIMx Trigger Output Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_TRGOSource - specifies the Trigger Output source.
+ *            TIM_TRGOSource_Reset -  The UG bit in the TIM_EGR register is
+ *        used as the trigger output (TRGO).
+ *            TIM_TRGOSource_Enable - The Counter Enable CEN is used as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_Update - The update event is selected as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_OC1 - The trigger output sends a positive pulse
+ *        when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
+ *            TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @return  none
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
+{
+    TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS);
+    TIMx->CTLR2 |= TIM_TRGOSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectSlaveMode
+ *
+ * @brief   Selects the TIMx Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_SlaveMode - specifies the Timer Slave Mode.
+ *            TIM_SlaveMode_Reset - Rising edge of the selected trigger
+ *        signal (TRGI) re-initializes.
+ *            TIM_SlaveMode_Gated - The counter clock is enabled when the
+ *        trigger signal (TRGI) is high.
+ *            TIM_SlaveMode_Trigger - The counter starts at a rising edge
+ *        of the trigger TRGI.
+ *            TIM_SlaveMode_External1 - Rising edges of the selected trigger
+ *        (TRGI) clock the counter.
+ *
+ * @return  none
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS);
+    TIMx->SMCFGR |= TIM_SlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectMasterSlaveMode
+ *
+ * @brief   Sets or Resets the TIMx Master/Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_MasterSlaveMode - specifies the Timer Master Slave Mode.
+ *            TIM_MasterSlaveMode_Enable - synchronization between the current
+ *        timer and its slaves (through TRGO).
+ *            TIM_MasterSlaveMode_Disable - No action.
+ *
+ * @return  none
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM);
+    TIMx->SMCFGR |= TIM_MasterSlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCounter
+ *
+ * @brief   Sets the TIMx Counter Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Counter - specifies the Counter register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter)
+{
+    TIMx->CNT = Counter;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetAutoreload
+ *
+ * @brief   Sets the TIMx Autoreload Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Autoreload - specifies the Autoreload register new value.
+ *
+ * @return  none
+ */
+void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
+{
+    TIMx->ATRLR = Autoreload;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare1
+ *
+ * @brief   Sets the TIMx Capture Compare1 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1)
+{
+    TIMx->CH1CVR = Compare1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare2
+ *
+ * @brief   Sets the TIMx Capture Compare2 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2)
+{
+    TIMx->CH2CVR = Compare2;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare3
+ *
+ * @brief   Sets the TIMx Capture Compare3 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3)
+{
+    TIMx->CH3CVR = Compare3;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare4
+ *
+ * @brief   Sets the TIMx Capture Compare4 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4)
+{
+    TIMx->CH4CVR = Compare4;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC1Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 1 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC);
+    TIMx->CHCTLR1 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC2Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 2 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC);
+    TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC3Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 3 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC);
+    TIMx->CHCTLR2 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC4Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 4 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC);
+    TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetClockDivision
+ *
+ * @brief   Sets the TIMx Clock Division value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_CKD - specifies the clock division value.
+ *            TIM_CKD_DIV1 - TDTS = Tck_tim.
+ *            TIM_CKD_DIV2 - TDTS = 2*Tck_tim.
+ *            TIM_CKD_DIV4 - TDTS = 4*Tck_tim.
+ *
+ * @return  none
+ */
+void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD);
+    TIMx->CTLR1 |= TIM_CKD;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture1
+ *
+ * @brief   Gets the TIMx Input Capture 1 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH1CVR - Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH1CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture2
+ *
+ * @brief   Gets the TIMx Input Capture 2 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH2CVR - Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH2CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture3
+ *
+ * @brief   Gets the TIMx Input Capture 3 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH3CVR - Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH3CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture4
+ *
+ * @brief   Gets the TIMx Input Capture 4 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH4CVR - Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH4CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCounter
+ *
+ * @brief   Gets the TIMx Counter value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CNT - Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+    return TIMx->CNT;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetPrescaler
+ *
+ * @brief   Gets the TIMx Prescaler value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->PSC - Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+    return TIMx->PSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetFlagStatus
+ *
+ * @brief   Checks whether the specified TIM flag is set or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  none
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    ITStatus bitstatus = RESET;
+
+    if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearFlag
+ *
+ * @brief   Clears the TIMx's pending flags.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  none
+ */
+void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    TIMx->INTFR = (uint16_t)~TIM_FLAG;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetITStatus
+ *
+ * @brief   Checks whether the TIM interrupt has occurred or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itstatus = 0x0, itenable = 0x0;
+
+    itstatus = TIMx->INTFR & TIM_IT;
+
+    itenable = TIMx->DMAINTENR & TIM_IT;
+    if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearITPendingBit
+ *
+ * @brief   Clears the TIMx's interrupt pending bits.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    TIMx->INTFR = (uint16_t)~TIM_IT;
+}
+
+/*********************************************************************
+ * @fn      TI1_Config
+ *
+ * @brief   Configure the TI1 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F)));
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI2_Config
+ *
+ * @brief   Configure the TI2 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 4);
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F)));
+    tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI3_Config
+ *
+ * @brief   Configure the TI3 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 8);
+    tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F)));
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI4_Config
+ *
+ * @brief   Configure the TI4 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 12);
+    tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F)));
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+    tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_usart.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_usart.c
new file mode 100644
index 0000000000..4985fefda6
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_usart.c
@@ -0,0 +1,806 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_usart.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the USART firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v20x_usart.h"
+#include "ch32v20x_rcc.h"
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set              ((uint16_t)0x2000) /* USART Enable Mask */
+#define CTLR1_UE_Reset            ((uint16_t)0xDFFF) /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask           ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set             ((uint16_t)0x0002) /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset           ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set             ((uint16_t)0x0001) /* USART Break Character send Mask */
+#define CTLR1_CLEAR_Mask          ((uint16_t)0xE9F3) /* USART CR1 Mask */
+#define CTLR2_Address_Mask        ((uint16_t)0xFFF0) /* USART address Mask */
+
+#define CTLR2_LINEN_Set           ((uint16_t)0x4000) /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset         ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask           ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask     ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask    ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set            ((uint16_t)0x0020) /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset          ((uint16_t)0xFFDF) /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set            ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset          ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set           ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset         ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask           ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask          ((uint16_t)0xFCFF) /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set            ((uint16_t)0x0002) /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset          ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask              ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask              ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
+#define IT_Mask                   ((uint16_t)0x001F) /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set           ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset         ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set         ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset       ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/*********************************************************************
+ * @fn      USART_DeInit
+ *
+ * @brief   Deinitializes the USARTx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *
+ * @return  none
+ */
+void USART_DeInit(USART_TypeDef *USARTx)
+{
+    if(USARTx == USART1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+    }
+    else if(USARTx == USART2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+    }
+    else if(USARTx == USART3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+    }
+    else if(USARTx == UART4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_Init
+ *
+ * @brief   Initializes the USARTx peripheral according to the specified
+ *        parameters in the USART_InitStruct.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *          USART_InitStruct - pointer to a USART_InitTypeDef structure
+ *        that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
+{
+    uint32_t          tmpreg = 0x00, apbclock = 0x00;
+    uint32_t          integerdivider = 0x00;
+    uint32_t          fractionaldivider = 0x00;
+    uint32_t          usartxbase = 0;
+    RCC_ClocksTypeDef RCC_ClocksStatus;
+
+    if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_STOP_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+    tmpreg = USARTx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+              USART_InitStruct->USART_Mode;
+    USARTx->CTLR1 = (uint16_t)tmpreg;
+
+    tmpreg = USARTx->CTLR3;
+    tmpreg &= CTLR3_CLEAR_Mask;
+    tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+    USARTx->CTLR3 = (uint16_t)tmpreg;
+
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+    if(usartxbase == USART1_BASE)
+    {
+        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+    }
+    else
+    {
+        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+    }
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+    }
+    else
+    {
+        integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+    }
+    tmpreg = (integerdivider / 100) << 4;
+
+    fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+    }
+    else
+    {
+        tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+    }
+
+    USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_StructInit
+ *
+ * @brief   Fills each USART_InitStruct member with its default value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
+{
+    USART_InitStruct->USART_BaudRate = 9600;
+    USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+    USART_InitStruct->USART_StopBits = USART_StopBits_1;
+    USART_InitStruct->USART_Parity = USART_Parity_No;
+    USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockInit
+ *
+ * @brief   Initializes the USARTx peripheral Clock according to the
+ *        specified parameters in the USART_ClockInitStruct .
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+              USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockStructInit
+ *
+ * @brief   Fills each USART_ClockStructInit member with its default value.
+ *
+ * @param   USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+    USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+    USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+    USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*********************************************************************
+ * @fn      USART_Cmd
+ *
+ * @brief   Enables or disables the specified USART peripheral.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_UE_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_UE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_ITConfig
+ *
+ * @brief   Enables or disables the specified USART interrupts.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Transmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *            USART_IT_ERR - Error interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+    uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+    uint32_t usartxbase = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itpos = USART_IT & IT_Mask;
+    itmask = (((uint32_t)0x01) << itpos);
+
+    if(usartreg == 0x01)
+    {
+        usartxbase += 0x0C;
+    }
+    else if(usartreg == 0x02)
+    {
+        usartxbase += 0x10;
+    }
+    else
+    {
+        usartxbase += 0x14;
+    }
+
+    if(NewState != DISABLE)
+    {
+        *(__IO uint32_t *)usartxbase |= itmask;
+    }
+    else
+    {
+        *(__IO uint32_t *)usartxbase &= ~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_DMACmd
+ *
+ * @brief   Enables or disables the USART DMA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_DMAReq - specifies the DMA request.
+ *            USART_DMAReq_Tx - USART DMA transmit request.
+ *            USART_DMAReq_Rx - USART DMA receive request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= USART_DMAReq;
+    }
+    else
+    {
+        USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SetAddress
+ *
+ * @brief   Sets the address of the USART node.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Address - Indicates the address of the USART node.
+ *
+ * @return  none
+ */
+void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
+{
+    USARTx->CTLR2 &= CTLR2_Address_Mask;
+    USARTx->CTLR2 |= USART_Address;
+}
+
+/*********************************************************************
+ * @fn      USART_WakeUpConfig
+ *
+ * @brief   Selects the USART WakeUp method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_WakeUp - specifies the USART wakeup method.
+ *            USART_WakeUp_IdleLine - WakeUp by an idle line detection.
+ *            USART_WakeUp_AddressMark - WakeUp by an address mark.
+ *
+ * @return  none
+ */
+void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
+{
+    USARTx->CTLR1 &= CTLR1_WAKE_Mask;
+    USARTx->CTLR1 |= USART_WakeUp;
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiverWakeUpCmd
+ *
+ * @brief   Determines if the USART is in mute mode or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_RWU_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_RWU_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_LINBreakDetectLengthConfig
+ *
+ * @brief   Sets the USART LIN Break detection length.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_LINBreakDetectLength - specifies the LIN break detection length.
+ *            USART_LINBreakDetectLength_10b - 10-bit break detection.
+ *            USART_LINBreakDetectLength_11b - 11-bit break detection.
+ *
+ * @return  none
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
+{
+    USARTx->CTLR2 &= CTLR2_LBDL_Mask;
+    USARTx->CTLR2 |= USART_LINBreakDetectLength;
+}
+
+/*********************************************************************
+ * @fn      USART_LINCmd
+ *
+ * @brief   Enables or disables the USART LIN mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR2 |= CTLR2_LINEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR2 &= CTLR2_LINEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SendData
+ *
+ * @brief   Transmits single data through the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          Data - the data to transmit.
+ *
+ * @return  none
+ */
+void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
+{
+    USARTx->DATAR = (Data & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
+{
+    return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_SendBreak
+ *
+ * @brief   Transmits break characters.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  none
+ */
+void USART_SendBreak(USART_TypeDef *USARTx)
+{
+    USARTx->CTLR1 |= CTLR1_SBK_Set;
+}
+
+/*********************************************************************
+ * @fn      USART_SetGuardTime
+ *
+ * @brief   Sets the specified USART guard time.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_GuardTime - specifies the guard time.
+ *
+ * @return  none
+ */
+void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
+{
+    USARTx->GPR &= GPR_LSB_Mask;
+    USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/*********************************************************************
+ * @fn      USART_SetPrescaler
+ *
+ * @brief   Sets the system clock prescaler.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Prescaler - specifies the prescaler clock.
+ *
+ * @return  none
+ */
+void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
+{
+    USARTx->GPR &= GPR_MSB_Mask;
+    USARTx->GPR |= USART_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardCmd
+ *
+ * @brief   Enables or disables the USART Smart Card mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_SCEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_SCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardNACKCmd
+ *
+ * @brief   Enables or disables NACK transmission.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_NACK_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_NACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_HalfDuplexCmd
+ *
+ * @brief   Enables or disables the USART Half Duplex communication.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *                  NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_HDSEL_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OverSampling8Cmd
+ *
+ * @brief   Enables or disables the USART's 8x oversampling mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_OVER8_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_OVER8_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OneBitMethodCmd
+ *
+ * @brief   Enables or disables the USART's one bit sampling method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_IrDAConfig
+ *
+ * @brief   Configures the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IrDAMode - specifies the IrDA mode.
+ *            USART_IrDAMode_LowPower.
+ *            USART_IrDAMode_Normal.
+ *
+ * @return  none
+ */
+void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
+{
+    USARTx->CTLR3 &= CTLR3_IRLP_Mask;
+    USARTx->CTLR3 |= USART_IrDAMode;
+}
+
+/*********************************************************************
+ * @fn      USART_IrDACmd
+ *
+ * @brief   Enables or disables the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_IREN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_IREN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_GetFlagStatus
+ *
+ * @brief   Checks whether the specified USART flag is set or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to check.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TXE - Transmit data register empty flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *            USART_FLAG_IDLE - Idle Line detection flag.
+ *            USART_FLAG_ORE - OverRun Error flag.
+ *            USART_FLAG_NE - Noise Error flag.
+ *            USART_FLAG_FE - Framing Error flag.
+ *            USART_FLAG_PE - Parity Error flag.
+ *
+ * @return  none
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(USART_FLAG == USART_FLAG_CTS)
+    {
+    }
+
+    if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearFlag
+ *
+ * @brief   Clears the USARTx's pending flags.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to clear.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *
+ * @return  none
+ */
+void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+    {
+    }
+
+    USARTx->STATR = (uint16_t)~USART_FLAG;
+}
+
+/*********************************************************************
+ * @fn      USART_GetITStatus
+ *
+ * @brief   Checks whether the specified USART interrupt has occurred or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt source to check.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Tansmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
+ *            USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
+ *            USART_IT_NE - Noise Error interrupt.
+ *            USART_IT_FE - Framing Error interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *
+ * @return  none
+ */
+ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+    ITStatus bitstatus = RESET;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itmask = USART_IT & IT_Mask;
+    itmask = (uint32_t)0x01 << itmask;
+
+    if(usartreg == 0x01)
+    {
+        itmask &= USARTx->CTLR1;
+    }
+    else if(usartreg == 0x02)
+    {
+        itmask &= USARTx->CTLR2;
+    }
+    else
+    {
+        itmask &= USARTx->CTLR3;
+    }
+
+    bitpos = USART_IT >> 0x08;
+    bitpos = (uint32_t)0x01 << bitpos;
+    bitpos &= USARTx->STATR;
+
+    if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearITPendingBit
+ *
+ * @brief   Clears the USARTx's interrupt pending bits.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the interrupt pending bit to clear.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *
+ * @return  none
+ */
+void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint16_t bitpos = 0x00, itmask = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    bitpos = USART_IT >> 0x08;
+    itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+    USARTx->STATR = (uint16_t)~itmask;
+}
diff --git a/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_wwdg.c b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_wwdg.c
new file mode 100644
index 0000000000..522a871a9a
--- /dev/null
+++ b/bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/source/ch32v20x_wwdg.c
@@ -0,0 +1,139 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_wwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file provides all the WWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ **********************************************************************************/
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_rcc.h"
+
+/* CTLR register bit mask */
+#define CTLR_WDGA_Set      ((uint32_t)0x00000080)
+
+/* CFGR register bit mask */
+#define CFGR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFGR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask           ((uint8_t)0x7F)
+
+/*********************************************************************
+ * @fn      WWDG_DeInit
+ *
+ * @brief   Deinitializes the WWDG peripheral registers to their default reset values
+ *
+ * @return  none
+ */
+void WWDG_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetPrescaler
+ *
+ * @brief   Sets the WWDG Prescaler
+ *
+ * @param   WWDG_Prescaler - specifies the WWDG Prescaler
+ *            WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
+ *            WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
+ *            WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
+ *            WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
+ *
+ * @return  none
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
+    tmpreg |= WWDG_Prescaler;
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetWindowValue
+ *
+ * @brief   Sets the WWDG window value
+ *
+ * @param   WindowValue - specifies the window value to be compared to the
+ *        downcounter,which must be lower than 0x80
+ *
+ * @return  none
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+    __IO uint32_t tmpreg = 0;
+
+    tmpreg = WWDG->CFGR & CFGR_W_Mask;
+
+    tmpreg |= WindowValue & (uint32_t)BIT_Mask;
+
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_EnableIT
+ *
+ * @brief   Enables the WWDG Early Wakeup interrupt(EWI)
+ *
+ * @return  none
+ */
+void WWDG_EnableIT(void)
+{
+    WWDG->CFGR |= (1 << 9);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetCounter
+ *
+ * @brief   Sets the WWDG counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ *
+ * @return  none
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+    WWDG->CTLR = Counter & BIT_Mask;
+}
+
+/*********************************************************************
+ * @fn      WWDG_Enable
+ *
+ * @brief   Enables WWDG and load the counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ * @return  none
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+    WWDG->CTLR = CTLR_WDGA_Set | Counter;
+}
+
+/*********************************************************************
+ * @fn      WWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the Early Wakeup interrupt flag is set or not
+ *
+ * @return  The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+    return (FlagStatus)(WWDG->STATR);
+}
+
+/*********************************************************************
+ * @fn      WWDG_ClearFlag
+ *
+ * @brief   Clears Early Wakeup interrupt flag
+ *
+ * @return  none
+ */
+void WWDG_ClearFlag(void)
+{
+    WWDG->STATR = (uint32_t)RESET;
+}
diff --git a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.py b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.py
index d95c6af7ae..3901f63416 100644
--- a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.py
+++ b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.py
@@ -1,6 +1,6 @@
 import os
 ARCH     = 'risc-v'
-CPU      = 'ch32v1'
+CPU      = 'ch32'
 # toolchains options
 CROSS_TOOL  = 'gcc'
 
@@ -10,13 +10,13 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'D:/Softwares/RT_ThreadStudio/repo/Extract/ToolChain_Support_Packages/WCH/RISC-V-GCC-WCH/8.2.0/bin'
+    EXEC_PATH   = r'D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\WCH\RISC-V-GCC-WCH\8.2.0\bin'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)
 
 # if os.getenv('RTT_EXEC_PATH'):
-    # EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+#     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
 
 BUILD = 'debug'
 #BUILD = 'release'
@@ -53,7 +53,7 @@ if PLATFORM == 'gcc':
     LPATH = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -g3'
+        CFLAGS += ' -O1 -g3'
         AFLAGS += ' -g3'
     else:
         CFLAGS += ' -O2'
diff --git a/bsp/wch/risc-v/ch32v208v-r0/.config b/bsp/wch/risc-v/ch32v208v-r0/.config
new file mode 100644
index 0000000000..30fd17be0e
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/.config
@@ -0,0 +1,980 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=2048
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_RISCV_FAMILY_CH32=y
+CONFIG_SOC_RISCV_SERIES_CH32V2=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_CH32V208WBU6=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART7 is not set
+# CONFIG_BSP_USING_UART8 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_RTC is not set
+CONFIG_LSI_VALUE=40000
+# CONFIG_BSP_USING_IWDT is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_TIM is not set
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/wch/risc-v/ch32v208v-r0/Kconfig b/bsp/wch/risc-v/ch32v208v-r0/Kconfig
new file mode 100644
index 0000000000..c80a8958fd
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../Libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/wch/risc-v/ch32v208v-r0/README_zh.md b/bsp/wch/risc-v/ch32v208v-r0/README_zh.md
new file mode 100644
index 0000000000..18eb07552b
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/README_zh.md
@@ -0,0 +1,108 @@
+# CH32V208W-R0 BSP 说明
+
+**中文**
+
+## 1 开发板简介
+
+CH32V208W-R0 是 WCH 推出的一款基于 RISC-V 内核的开发板，最高主频为 144Mhz。比较适合入门学习 RISC-V 架构。
+
+![board](./figures/ch32v208.png)
+
+**基本特性：**
+
+- MCU：CH32V208WBU6，主频 144MHz，FLASH和RAM可配置
+- LED：2个。
+- 按键：3个 Download  ,Reset， User 。
+- USB：2个，Tpye-C。
+- 网口：1个，内置 10M PHY。
+- 板上无 WCH-Link 下载调试工具，需外接。
+
+## 2 编译说明
+
+板级包支持 RISC-V GCC 开发环境，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本           |
+| ---------- | -------------------- |
+| GCC        | WCH RISC-V GCC 8.2.0 |
+
+## 3 使用说明
+
+>本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+### 3.1 使用Env编译BSP
+
+本节讲解如何使用Env工具来编译BSP工程。
+
+#### 3.1.1 编译BSP
+
+1. [下载WCH编译工具链](https://github.com/NanjingQinheng/sdk-toolchain-RISC-V-GCC-WCH/archive/refs/tags/V1.0.0.zip)
+2. 下载Env工具[最新版本](https://github.com/RT-Thread/env-windows/releases)
+3. 下载RT-Thread[最新源码](https://github.com/RT-Thread/rt-thread/archive/refs/heads/master.zip)
+4. 并在当前BSP根目录下打开Env工具并执行 `scons --exec-path=D:\sdk-toolchain-RISC-V-GCC-WCH-1.0.0\bin` 命令，在指定工具链位置的同时直接编译。
+5. 编译完成之后会生成 **rtthread.bin** 文件。
+
+![sconscompile](./figures/sconscompile.jpg)
+
+#### 3.1.2 硬件连接
+
+使用数据线连接板载 wch-link 到 PC，打开电源开关。
+
+#### 3.1.3 下载
+
+打开 WCH RISC-V MCU ProgrammerTool 下载软件，选择刚刚生成的 **rtthread.bin**  文件，进行下载。
+
+![tool](./figures/tool.png)
+
+#### 3.1.4 运行结果
+
+在终端工具里打开板载 wch-link 串口（WCHDapLink SERIAL，默认115200-8-1-N），复位设备后，在串口上可以看到 RT-Thread 的输出信息：
+
+![end](./figures/end.png)
+
+### 3.2 使用VSCode编译工程
+
+在Env终端中敲入命令 `scons --target=vsc` 来生成VSCode工程. 接着敲入命令 `code .` 来打开VSCode.
+
+使用 **VSCode 终端** 敲入命令 `scons -j12 --exec-path=D:\sdk-toolchain-RISC-V-GCC-WCH-1.0.0bin` 来编译工程。
+
+![vscode-terminal](./figures/vscode-terminal.png)
+
+### 3.3 导入 RT-Thread Studio 工程
+
+#### 3.3.1 导入
+
+打开 RT-Thread Studio 后点击：文件->导入：
+
+![import](./figures/import.png)
+
+选择“RT-Thread Bsp 到工作空间中”：
+
+![windows](./figures/windows.png)
+
+填写项目信息，Bsp 根目录为 `\rt-thread\bsp\wch\risc-v\ch32v307v-r1` 目录：
+
+![config](./figures/config.png)
+
+#### 3.3.2 配置环境
+
+工程导入后进行编译环境的设置，首先点击“打开构建设置”进入设置界面：
+
+![set](./figures/set.png)
+
+将编译链路径复制到 Toolchain path 中：
+
+![toolchain](./figures/toolchain.png)
+
+如图更改 Prefix ：
+
+![prefix](./figures/prefix.png)
+
+进行工具设置：
+
+![toolset](./figures/toolset.png)
+
+#### 3.3.3 编译
+
+编译结果如下：
+
+![success](./figures/success.png)
diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConscript b/bsp/wch/risc-v/ch32v208v-r0/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConstruct b/bsp/wch/risc-v/ch32v208v-r0/SConstruct
new file mode 100644
index 0000000000..1c21f19f0a
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/SConstruct
@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+from SCons.Script import *
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/Libraries'):
+    libraries_path_prefix = SDK_ROOT + '/Libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ch32_library = 'ch32v20x_libraries'
+rtconfig.BSP_LIBRARY_TYPE = ch32_library
+
+bsp_vdir = 'build'
+library_vdir = 'build/libraries'
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ch32_library, 'SConscript'), variant_dir=library_vdir + '/ch32_library', duplicate=0))
+
+# common include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ch32_drivers','SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript b/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript
new file mode 100644
index 0000000000..9bb9abae89
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/main.c b/bsp/wch/risc-v/ch32v208v-r0/applications/main.c
new file mode 100644
index 0000000000..3246340a93
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/applications/main.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-11-03     WangShun       first version
+ */
+
+#include "ch32v20x.h"
+#include <rtthread.h>
+#include <rthw.h>
+#include "drivers/pin.h"
+#include <board.h>
+
+#define LED0 rt_pin_get("PA.0")
+
+int main(void)
+{
+    rt_pin_mode(LED0,PIN_MODE_OUTPUT);
+    rt_kprintf("MCU-CH32V208WBU6\r\n");
+    while(1)
+    {
+        rt_pin_write(LED0, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig b/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig
new file mode 100644
index 0000000000..613551495b
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/board/Kconfig
@@ -0,0 +1,579 @@
+menu "Hardware Drivers Config"
+
+config SOC_CH32V208WBU6
+    bool
+    select SOC_RISCV_SERIES_CH32V2
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        select RT_USING_SERIAL
+        default n
+
+        if BSP_USING_UART
+           config BSP_USING_UART1
+               bool "Enable UART1"
+               default n
+
+           config BSP_USING_UART2
+               bool "Enable UART2"
+           default n
+
+          config BSP_USING_UART3
+              bool "Enable UART3"
+              default n
+
+          config BSP_USING_UART4
+              bool "Enable UART4"
+              default n
+
+          config BSP_USING_UART5
+              bool "Enable UART5"
+              default n
+
+          config BSP_USING_UART6
+              bool "Enable UART6"
+              default n
+
+          config BSP_USING_UART7
+              bool "Enable UART7"
+              default n
+
+          config BSP_USING_UART8
+              bool "Enable UART8"
+              default n
+        endif
+   
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+        if BSP_USING_ADC
+           config BSP_USING_ADC1
+               bool "Enable ADC1"
+               default n
+
+           config BSP_USING_ADC2
+               bool "Enable ADC2"
+               default n
+
+           config ADC_CHANNEL_16
+               bool "Enable ADC CHANNEL 16 (inside temperature)"
+               default n    
+
+           config ADC_CHANNEL_17
+               bool "Enable ADC CHANNEL 17 (inside Verf)"
+               default n    
+        endif
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        select RT_USING_DAC        
+        default n
+
+        if BSP_USING_DAC
+            config BSP_USING_DAC_CHANNEL1
+                bool "Enable DAC CHANNEL1"
+                default n
+            config BSP_USING_DAC_CHANNEL2
+                bool "Enable DAC CHANNEL2"
+                default n  
+        endif 
+
+    menuconfig BSP_USING_SOFT_I2C
+        bool "Enable I2C Bus"
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        default n
+
+        if BSP_USING_SOFT_I2C
+            config BSP_USING_I2C1
+                bool "Enable I2C1 Bus (software simulation)"
+                default n
+
+                if BSP_USING_I2C1
+                    comment "Notice: PC7 --> 39; PC6 --> 38"
+
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 SCL pin number"
+                        range 0 79
+                        default 38
+                    config BSP_I2C1_SDA_PIN
+                        int "i2c1 SDA pin number"
+                        range 0 79
+                        default 39
+                endif
+
+            config BSP_USING_I2C2
+                bool "Enable I2C2 Bus (software simulation)"
+                default n
+
+                if BSP_USING_I2C2
+                    comment "Notice: PC1 --> 33; PC0 --> 32"
+                    config BSP_I2C2_SCL_PIN
+                        int "i2c2 SCL pin number"
+                        range 0 79
+                        default 32
+                    config BSP_I2C2_SDA_PIN
+                        int "i2c2 SDA pin number"
+                        range 0 79
+                        default 33
+                endif
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        select RT_USING_SPI_BITOPS
+        select RT_USING_SPI
+        
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+		
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                default n
+		
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                default n
+                
+            if  BSP_USING_SPI3
+                config BSP_USING_SPI_FLASH
+                bool "Enable SPI Flash"
+                default n
+            endif
+            
+            config BSP_USING_SOFT_SPI1
+                bool "Enable SSPI1 Bus (User SPI)"
+                default n
+                if BSP_USING_SOFT_SPI1
+                    comment "Notice: PB9 --> 25; PB8 --> 24; PB7 --> 23" 
+                    config BSP_S_SPI1_SCK_PIN
+                        int "sspi1 SCL pin number"
+                        range 1 79
+                        default 25
+                    config BSP_S_SPI1_MOSI_PIN
+                        int "sspi1 MISO pin number"
+                        range 1 79
+                        default 24
+                    config BSP_S_SPI1_MISO_PIN
+                        int "sspi1 MOSI pin number"
+                        range 1 79
+                        default 23    
+                endif
+                
+            config BSP_USING_SOFT_SPI2
+                bool "Enable SSPI2 Bus (soft SPI)"
+                default n
+                if BSP_USING_SOFT_SPI2
+                    comment "Notice: PE0 --> 64; PE1 --> 65; PE2 --> 66" 
+                    config BSP_S_SPI2_SCK_PIN
+                        int "sspi2 SCL pin number"
+                        range 1 79
+                        default 64
+                    config BSP_S_SPI2_MOSI_PIN
+                        int "sspi2 MISO pin number"
+                        range 1 79
+                        default 65
+                    config BSP_S_SPI2_MISO_PIN
+                        int "sspi2 MOSI pin number"
+                        range 1 79
+                        default 66    
+                endif                 
+        endif
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        
+        if BSP_USING_RTC
+            config BSP_USING_RTC_LSI
+                bool "Using LSI clock for rtc, if not, LSE default"
+                select LSI_VALUE
+                default n
+        endif
+
+    config LSI_VALUE
+        int
+        default 40000
+
+    config BSP_USING_IWDT
+        bool "Enable IWDT"
+        select RT_USING_WDT
+        select LSI_VALUE
+        default n
+		
+	menuconfig BSP_USING_CAN
+            bool "Enable CAN"
+            default n
+            select RT_USING_CAN
+            if BSP_USING_CAN
+                config BSP_USING_CAN1
+                    bool "Using CAN1"
+                    default n
+                config BSP_USING_CAN2
+                    bool "Using CAN2"
+                    default n
+            endif
+
+    config BSP_USING_TIM
+        bool "Using TIMx"
+        default n
+
+        if BSP_USING_TIM
+            config BSP_USING_HWTIMER
+                bool
+                select RT_USING_HWTIMER
+                default n
+
+            config BSP_USING_PWM
+                bool
+                select RT_USING_PWM
+                default n
+
+            config BSP_USING_TIM1
+                bool "using TIM1"
+                default n
+
+                if BSP_USING_TIM1
+                    choice
+                        prompt "Using TIM1 as hwtimer or PWM mode"
+                        default BSP_USING_TIM1_HWTIMER
+
+                        config BSP_USING_TIM1_HWTIMER
+                            bool "Using TIM1 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM1_PWM
+                            bool "Using TIM1 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM1_PWM
+                        config BSP_USING_TIM1_PWM_CH1
+                            bool "Using TIM1 channel 1"
+                            default n
+
+                        config BSP_USING_TIM1_PWM_CH2
+                            bool "Using TIM1 channel 2"
+                            default n
+
+                        config BSP_USING_TIM1_PWM_CH3
+                            bool "Using TIM1 channel 3"
+
+                        config BSP_USING_TIM1_PWM_CH4
+                            bool "Using TIM1 channel 4"
+                    endif
+
+                endif
+
+            config BSP_USING_TIM2
+                    bool "Using TIM2"
+                    default n
+
+                if BSP_USING_TIM2
+                    choice
+                        prompt "Using TIM2 as hwtimer or PWM mode"
+                        default BSP_USING_TIM2_HWTIMER
+
+                        config BSP_USING_TIM2_HWTIMER
+                            bool "Using TIM2 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM2_PWM
+                            bool "Using TIM2 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM2_PWM
+                        config BSP_USING_TIM2_PWM_CH1
+                            bool "Using TIM2 channel 1"
+                            default n
+
+                        config BSP_USING_TIM2_PWM_CH2
+                            bool "Using TIM2 channel 2"
+                            default n
+
+                        config BSP_USING_TIM2_PWM_CH3
+                            bool "Using TIM2 channel 3"
+
+                        config BSP_USING_TIM2_PWM_CH4
+                            bool "Using TIM2 channel 4"
+                    endif
+
+                endif
+
+            config BSP_USING_TIM3
+                    bool "Using TIM3"
+                    default n
+
+                if BSP_USING_TIM3
+                    choice
+                        prompt "Using TIM3 as hwtimer or PWM mode"
+                        default BSP_USING_TIM3_HWTIMER
+
+                        config BSP_USING_TIM3_HWTIMER
+                            bool "Using TIM3 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM3_PWM
+                            bool "Using TIM3 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM3_PWM
+                        config BSP_USING_TIM3_PWM_CH1
+                            bool "Using TIM3 channel 1"
+                            default n
+
+                        config BSP_USING_TIM3_PWM_CH2
+                            bool "Using TIM3 channel 2"
+                            default n
+
+                        config BSP_USING_TIM3_PWM_CH3
+                            bool "Using TIM3 channel 3"
+
+                        config BSP_USING_TIM3_PWM_CH4
+                            bool "Using TIM3 channel 4"
+                    endif
+
+                endif
+
+            config BSP_USING_TIM4
+                    bool "Using TIM4"
+                    default n
+
+                if BSP_USING_TIM4
+                    choice
+                        prompt "Using TIM4 as hwtimer or PWM mode"
+                        default BSP_USING_TIM4_HWTIMER
+
+                        config BSP_USING_TIM4_HWTIMER
+                            bool "Using TIM4 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM4_PWM
+                            bool "Using TIM4 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM4_PWM
+                        config BSP_USING_TIM4_PWM_CH1
+                            bool "Using TIM4 channel 1"
+                            default n
+
+                        config BSP_USING_TIM4_PWM_CH2
+                            bool "Using TIM4 channel 2"
+                            default n
+
+                        config BSP_USING_TIM4_PWM_CH3
+                            bool "Using TIM4 channel 3"
+
+                        config BSP_USING_TIM4_PWM_CH4
+                            bool "Using TIM4 channel 4"
+                    endif
+
+                endif
+                
+            config BSP_USING_TIM5
+                    bool "Using TIM5"
+                    default n
+
+                if BSP_USING_TIM5
+                    choice
+                        prompt "Using TIM5 as hwtimer or PWM mode"
+                        default BSP_USING_TIM5_HWTIMER
+
+                        config BSP_USING_TIM5_HWTIMER
+                            bool "Using TIM5 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM5_PWM
+                            bool "Using TIM5 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM5_PWM
+                        config BSP_USING_TIM5_PWM_CH1
+                            bool "Using TIM5 channel 1"
+                            default n
+
+                        config BSP_USING_TIM5_PWM_CH2
+                            bool "Using TIM5 channel 2"
+                            default n
+
+                        config BSP_USING_TIM5_PWM_CH3
+                            bool "Using TIM5 channel 3"
+
+                        config BSP_USING_TIM5_PWM_CH4
+                            bool "Using TIM5 channel 4"
+                    endif
+
+                endif
+                
+            config BSP_USING_TIM6
+                    bool "Using TIM6"
+                    default n
+
+                if BSP_USING_TIM6
+                    choice
+                        prompt "Using TIM5 as hwtimer (PWM mode not supported)"
+                        default BSP_USING_TIM6_HWTIMER
+
+                        config BSP_USING_TIM6_HWTIMER
+                            bool "Using TIM6 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+                    endchoice
+                    
+                endif
+                
+            config BSP_USING_TIM7
+                    bool "Using TIM7"
+                    default n
+
+                if BSP_USING_TIM7
+                    choice
+                        prompt "Using TIM7 as hwtimer (PWM mode not supported)"
+                        default BSP_USING_TIM7_HWTIMER
+
+                        config BSP_USING_TIM7_HWTIMER
+                            bool "Using TIM7 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+                    endchoice
+                    
+                endif
+                
+            config BSP_USING_TIM8
+                    bool "Using TIM8"
+                    default n
+
+                if BSP_USING_TIM8
+                    choice
+                        prompt "Using TIM8 as hwtimer or PWM mode"
+                        default BSP_USING_TIM8_HWTIMER
+
+                        config BSP_USING_TIM8_HWTIMER
+                            bool "Using TIM8 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM8_PWM
+                            bool "Using TIM8 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM8_PWM
+                        config BSP_USING_TIM8_PWM_CH1
+                            bool "Using TIM8 channel 1"
+                            default n
+
+                        config BSP_USING_TIM8_PWM_CH2
+                            bool "Using TIM8 channel 2"
+                            default n
+
+                        config BSP_USING_TIM8_PWM_CH3
+                            bool "Using TIM8 channel 3"
+
+                        config BSP_USING_TIM8_PWM_CH4
+                            bool "Using TIM8 channel 4"
+                    endif
+                    
+                endif
+                
+            config BSP_USING_TIM9
+                    bool "Using TIM9"
+                    default n
+
+                if BSP_USING_TIM9
+                    choice
+                        prompt "Using TIM9 as hwtimer or PWM mode"
+                        default BSP_USING_TIM9_HWTIMER
+
+                        config BSP_USING_TIM9_HWTIMER
+                            bool "Using TIM9 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM9_PWM
+                            bool "Using TIM9 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM9_PWM
+                        config BSP_USING_TIM9_PWM_CH1
+                            bool "Using TIM9 channel 1"
+                            default n
+
+                        config BSP_USING_TIM9_PWM_CH2
+                            bool "Using TIM9 channel 2"
+                            default n
+
+                        config BSP_USING_TIM9_PWM_CH3
+                            bool "Using TIM9 channel 3"
+
+                        config BSP_USING_TIM9_PWM_CH4
+                            bool "Using TIM9 channel 4"
+                    endif
+                    
+                endif
+                
+            config BSP_USING_TIM10
+                    bool "Using TIM10"
+                    default n
+
+                if BSP_USING_TIM10
+                    choice
+                        prompt "Using TIM10 as hwtimer or PWM mode"
+                        default BSP_USING_TIM10_HWTIMER
+
+                        config BSP_USING_TIM10_HWTIMER
+                            bool "Using TIM10 as hwtimer mode"
+                            select BSP_USING_HWTIMER
+
+                        config BSP_USING_TIM10_PWM
+                            bool "Using TIM10 as PWM mode"
+                            select BSP_USING_PWM
+                    endchoice
+
+                    if BSP_USING_TIM10_PWM
+                        config BSP_USING_TIM10_PWM_CH1
+                            bool "Using TIM10 channel 1"
+                            default n
+
+                        config BSP_USING_TIM10_PWM_CH2
+                            bool "Using TIM10 channel 2"
+                            default n
+
+                        config BSP_USING_TIM10_PWM_CH3
+                            bool "Using TIM10 channel 3"
+
+                        config BSP_USING_TIM10_PWM_CH4
+                            bool "Using TIM10 channel 4"
+                    endif
+                    
+                endif
+                
+        endif
+		
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/SConscript b/bsp/wch/risc-v/ch32v208v-r0/board/SConscript
new file mode 100644
index 0000000000..bc8e7636f1
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/board/SConscript
@@ -0,0 +1,17 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+Return('group')
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.c b/bsp/wch/risc-v/ch32v208v-r0/board/board.c
new file mode 100644
index 0000000000..197c3c66ad
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/board/board.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-23     liYony       first version
+ */
+
+#include "board.h"
+#include <stdint.h>
+#include "drv_usart.h"
+#include <rthw.h>
+#include <rtthread.h>
+
+extern uint32_t SystemCoreClock;
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+    NVIC_SetPriority(SysTicK_IRQn,0xf0);
+    NVIC_SetPriority(Software_IRQn,0xf0);
+    NVIC_EnableIRQ(SysTicK_IRQn);
+    NVIC_EnableIRQ(Software_IRQn);
+    SysTick->CTLR=0;
+    SysTick->SR=0;
+    SysTick->CNT=0;
+    SysTick->CMP=ticks-1;
+    SysTick->CTLR=0xF;
+    return 0;
+}
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+#define RT_HEAP_SIZE (1024*10)
+static uint32_t rt_heap[RT_HEAP_SIZE];
+rt_weak void *rt_heap_begin_get(void)
+{
+    return rt_heap;
+}
+
+rt_weak void *rt_heap_end_get(void)
+{
+    return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+    /* System Tick Configuration */
+    _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}
+
+void SysTick_Handler(void) __attribute__((interrupt()));
+void SysTick_Handler(void)
+{
+    GET_INT_SP();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    SysTick->SR=0;
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+    FREE_INT_SP();
+
+}
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/board.h b/bsp/wch/risc-v/ch32v208v-r0/board/board.h
new file mode 100644
index 0000000000..9086e24c4e
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/board/board.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-23     liYony       first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "ch32v20x.h"
+
+#define ch32v20x_PIN_NUMBERS   64
+/* board configuration */
+#define SRAM_SIZE  64
+#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
+
+extern int _ebss;
+#define HEAP_BEGIN  ((void *)&_ebss)
+#define HEAP_END    (SRAM_END-_stack_size)
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds b/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds
new file mode 100644
index 0000000000..b0051ab14d
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/board/linker_scripts/link.lds
@@ -0,0 +1,194 @@
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+		
+		 /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    . = ALIGN(4);
+    
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    . = ALIGN(4);
+
+    /* section information for modules */
+    . = ALIGN(4);
+    __rtmsymtab_start = .;
+    KEEP(*(RTMSymTab))
+    __rtmsymtab_end = .;
+		. = ALIGN(4);
+			
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );    
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM 
+
+}
+
+
+
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/ch32v208.png b/bsp/wch/risc-v/ch32v208v-r0/figures/ch32v208.png
new file mode 100644
index 0000000000..752edca1d6
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/ch32v208.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/config.png b/bsp/wch/risc-v/ch32v208v-r0/figures/config.png
new file mode 100644
index 0000000000..f74e8705f8
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/config.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/dist.png b/bsp/wch/risc-v/ch32v208v-r0/figures/dist.png
new file mode 100644
index 0000000000..d190d816fb
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/dist.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/end.png b/bsp/wch/risc-v/ch32v208v-r0/figures/end.png
new file mode 100644
index 0000000000..ff49a943b4
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/end.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/import.png b/bsp/wch/risc-v/ch32v208v-r0/figures/import.png
new file mode 100644
index 0000000000..eaf0f2213d
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/import.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/prefix.png b/bsp/wch/risc-v/ch32v208v-r0/figures/prefix.png
new file mode 100644
index 0000000000..9542d60a29
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/prefix.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/scons.png b/bsp/wch/risc-v/ch32v208v-r0/figures/scons.png
new file mode 100644
index 0000000000..683dc33ab1
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/scons.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/sconscompile.jpg b/bsp/wch/risc-v/ch32v208v-r0/figures/sconscompile.jpg
new file mode 100644
index 0000000000..2460567f48
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/sconscompile.jpg
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/set.png b/bsp/wch/risc-v/ch32v208v-r0/figures/set.png
new file mode 100644
index 0000000000..573a45c34e
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/set.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/success.png b/bsp/wch/risc-v/ch32v208v-r0/figures/success.png
new file mode 100644
index 0000000000..c5d399d150
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/success.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/tool.png b/bsp/wch/risc-v/ch32v208v-r0/figures/tool.png
new file mode 100644
index 0000000000..94c5aec257
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/tool.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/toolchain.png b/bsp/wch/risc-v/ch32v208v-r0/figures/toolchain.png
new file mode 100644
index 0000000000..610e67cc91
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/toolchain.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/toolset.png b/bsp/wch/risc-v/ch32v208v-r0/figures/toolset.png
new file mode 100644
index 0000000000..3fd87da63f
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/toolset.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/vscode-terminal.png b/bsp/wch/risc-v/ch32v208v-r0/figures/vscode-terminal.png
new file mode 100644
index 0000000000..a227260d84
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/vscode-terminal.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/figures/windows.png b/bsp/wch/risc-v/ch32v208v-r0/figures/windows.png
new file mode 100644
index 0000000000..5deed9009e
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/figures/windows.png
diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h b/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h
new file mode 100644
index 0000000000..394d127847
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/rtconfig.h
@@ -0,0 +1,237 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 2048
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_RISCV_FAMILY_CH32
+#define SOC_RISCV_SERIES_CH32V2
+
+/* Hardware Drivers Config */
+
+#define SOC_CH32V208WBU6
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+#define LSI_VALUE 40000
+
+/* Onboard Peripheral Drivers */
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py b/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py
new file mode 100644
index 0000000000..93507a7f8d
--- /dev/null
+++ b/bsp/wch/risc-v/ch32v208v-r0/rtconfig.py
@@ -0,0 +1,70 @@
+import os
+ARCH     = 'risc-v'
+CPU      = 'ch32'
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\WCH\RISC-V-GCC-WCH\8.2.0\bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+	
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    
+print(EXEC_PATH)
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+CORE = 'risc-v'
+MAP_FILE = 'rtthread.map'
+LINK_FILE = './board/linker_scripts/link.lds'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'riscv-none-embed-'
+    CC = PREFIX + 'gcc'
+    CXX= PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L.  -nostartfiles  -lc '
+    CFLAGS = DEVICE
+    CFLAGS += ' -save-temps=obj'
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
+    POST_ACTION += SIZE + ' $TARGET\n'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
\ No newline at end of file
diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py
index 0761b2b316..299a0c7150 100644
--- a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py
+++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.py
@@ -1,6 +1,6 @@
 import os
 ARCH     = 'risc-v'
-CPU      = 'ch32v3'
+CPU      = 'ch32'
 # toolchains options
 CROSS_TOOL  = 'gcc'
 
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 6639ea7a22..b18bccbe5d 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -18,9 +18,7 @@ elif rtconfig.CPU == "virt64" :
     group = group
 elif rtconfig.CPU == "c906" :
     group = group
-elif rtconfig.CPU == "ch32v1" :
-    group = group
-elif rtconfig.CPU == "ch32v3" :
+elif rtconfig.CPU == "ch32" :
     group = group
 elif rtconfig.CPU == "hpmicro":
     group = group
diff --git a/libcpu/risc-v/ch32v3/SConscript b/libcpu/risc-v/ch32/SConscript
index 383d80e528..383d80e528 100644
--- a/libcpu/risc-v/ch32v3/SConscript
+++ b/libcpu/risc-v/ch32/SConscript
diff --git a/libcpu/risc-v/ch32v3/context_gcc.S b/libcpu/risc-v/ch32/context_gcc.S
index f8622f0700..3d6af17934 100644
--- a/libcpu/risc-v/ch32v3/context_gcc.S
+++ b/libcpu/risc-v/ch32/context_gcc.S
@@ -137,7 +137,11 @@ rt_hw_context_switch_exit:
     LOAD x1,   1 * REGBYTES(sp)
 
 	/* keep machine mode */
+	#if defined (SOC_RISCV_SERIES_CH32V3)
 	li    a0,      0x7800
+	#else
+	li    a0,      0x1800
+	#endif
 	csrs  mstatus, a0
 	/* resume MPIE */
 	LOAD  a0,      2*REGBYTES(sp)
diff --git a/libcpu/risc-v/ch32v3/cpuport.c b/libcpu/risc-v/ch32/cpuport.c
index b36e731554..e42bab949e 100644
--- a/libcpu/risc-v/ch32v3/cpuport.c
+++ b/libcpu/risc-v/ch32/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,7 +10,16 @@
 
 #include <rthw.h>
 #include <rtthread.h>
+#if defined (SOC_RISCV_SERIES_CH32V1)
+#include "ch32v10x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V2)
+#include "ch32v20x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V3)
 #include "ch32v30x.h"
+#else
+#error "CH32 architecture doesn't support!"
+#endif
+
 #include "cpuport.h"
 
 #ifndef RT_USING_SMP
@@ -124,9 +133,13 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     frame->ra      = (rt_ubase_t)texit;
     frame->a0      = (rt_ubase_t)parameter;
     frame->epc     = (rt_ubase_t)tentry;
-
+    #if defined (SOC_RISCV_SERIES_CH32V3)
     /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
     frame->mstatus = 0x00007880;
+    #else
+    /* force to machine mode(MPP=11) and set MPIE to 1 */
+    frame->mstatus = 0x00001880;
+    #endif
     return stk;
 }
 
@@ -135,7 +148,12 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
  */
 void sw_setpend(void)
 {
+    /*CH32V103 does not support systick software interrupt*/
+    #if defined (SOC_RISCV_SERIES_CH32V1)
+    NVIC_SetPendingIRQ(Software_IRQn);
+    #else
     SysTick->CTLR |= (1<<31);
+    #endif
 }
 
 /*
@@ -143,7 +161,12 @@ void sw_setpend(void)
  */
 void sw_clearpend(void)
 {
+    /*CH32V103 does not support systick software interrupt*/
+    #if defined (SOC_RISCV_SERIES_CH32V1)
+    NVIC_ClearPendingIRQ(Software_IRQn);
+    #else
     SysTick->CTLR &= ~(1<<31);
+    #endif
 }
 
 /*
@@ -152,7 +175,11 @@ void sw_clearpend(void)
 rt_base_t rt_hw_interrupt_disable(void)
 {
     rt_base_t value=0;
+    #if defined (SOC_RISCV_SERIES_CH32V3)
     asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
+    #else
+    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
+    #endif
     return value;
 }
 
diff --git a/libcpu/risc-v/ch32v1/cpuport.h b/libcpu/risc-v/ch32/cpuport.h
index c37f3bbb5b..c37f3bbb5b 100644
--- a/libcpu/risc-v/ch32v1/cpuport.h
+++ b/libcpu/risc-v/ch32/cpuport.h
diff --git a/libcpu/risc-v/ch32v3/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S
index ce5cdb210d..96c61ddd33 100644
--- a/libcpu/risc-v/ch32v3/interrupt_gcc.S
+++ b/libcpu/risc-v/ch32/interrupt_gcc.S
@@ -58,8 +58,10 @@ SW_handler:
     STORE t0,   2 * REGBYTES(sp)
 
 	/* Temporarily disable HPE  */
+	#if defined (SOC_RISCV_SERIES_CH32V3)
 	li   t0,    0x20
 	csrs 0x804, t0
+	#endif
 
     STORE x1,   1 * REGBYTES(sp)
     STORE x4,   4 * REGBYTES(sp)
@@ -120,9 +122,13 @@ SW_handler:
     csrw  mepc, a0
 
 1:  LOAD  x1,   1 * REGBYTES(sp)
-
+	#if defined (SOC_RISCV_SERIES_CH32V3)
 	li t0,0x7800
 	csrs mstatus, t0
+	#else
+	li t0,0x1800
+	csrs mstatus, t0	
+	#endif
 	LOAD t0, 2*REGBYTES(sp)
 	csrs mstatus, t0
 
diff --git a/libcpu/risc-v/ch32v1/SConscript b/libcpu/risc-v/ch32v1/SConscript
deleted file mode 100644
index 20f325b692..0000000000
--- a/libcpu/risc-v/ch32v1/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/risc-v/ch32v1/context_gcc.S b/libcpu/risc-v/ch32v1/context_gcc.S
deleted file mode 100644
index 5cf2d39cf8..0000000000
--- a/libcpu/risc-v/ch32v1/context_gcc.S
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- */
-
-#include "cpuport.h"
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_to(rt_ubase_t to);
- * #endif
- * a0 --> to
- * a1 --> to_thread
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    /* first save interrupt stack */
-	la t0, _eusrstack
-	addi t0, t0, -512
-    csrw mscratch,t0
-
-    LOAD sp, (a0)
-    LOAD a0,   2 * REGBYTES(sp)
-    csrw mstatus, a0
-    j    rt_hw_context_switch_exit
-
-
-/*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
- * a0 --> from
- * a1 --> to
- */
-	.globl rt_hw_context_switch
-rt_hw_context_switch:
-	/* switch in thread */
-#ifdef ARCH_RISCV_FPU
-	addi sp, sp, -32*FREGBYTES
-
-    FSTORE  f0, 0 * FREGBYTES(sp)
-    FSTORE  f1, 1 * FREGBYTES(sp)
-    FSTORE  f2, 2 * FREGBYTES(sp)
-    FSTORE  f3, 3 * FREGBYTES(sp)
-    FSTORE  f4, 4 * FREGBYTES(sp)
-    FSTORE  f5, 5 * FREGBYTES(sp)
-    FSTORE  f6, 6 * FREGBYTES(sp)
-    FSTORE  f7, 7 * FREGBYTES(sp)
-    FSTORE  f8, 8 * FREGBYTES(sp)
-    FSTORE  f9, 9 * FREGBYTES(sp)
-    FSTORE  f10, 10 * FREGBYTES(sp)
-    FSTORE  f11, 11 * FREGBYTES(sp)
-    FSTORE  f12, 12 * FREGBYTES(sp)
-    FSTORE  f13, 13 * FREGBYTES(sp)
-    FSTORE  f14, 14 * FREGBYTES(sp)
-    FSTORE  f15, 15 * FREGBYTES(sp)
-    FSTORE  f16, 16 * FREGBYTES(sp)
-    FSTORE  f17, 17 * FREGBYTES(sp)
-    FSTORE  f18, 18 * FREGBYTES(sp)
-    FSTORE  f19, 19 * FREGBYTES(sp)
-    FSTORE  f20, 20 * FREGBYTES(sp)
-    FSTORE  f21, 21 * FREGBYTES(sp)
-    FSTORE  f22, 22 * FREGBYTES(sp)
-    FSTORE  f23, 23 * FREGBYTES(sp)
-    FSTORE  f24, 24 * FREGBYTES(sp)
-    FSTORE  f25, 25 * FREGBYTES(sp)
-    FSTORE  f26, 26 * FREGBYTES(sp)
-    FSTORE  f27, 27 * FREGBYTES(sp)
-    FSTORE  f28, 28 * FREGBYTES(sp)
-    FSTORE  f29, 29 * FREGBYTES(sp)
-    FSTORE  f30, 30 * FREGBYTES(sp)
-    FSTORE  f31, 31 * FREGBYTES(sp)
-#endif
-
-	addi sp, sp, -32 * REGBYTES
-	/* save from sp */
-	STORE sp,   0(a0)
-	/* save ra to epc */
-	STORE x1,   0 * REGBYTES(sp)
-	STORE x1,   1 * REGBYTES(sp)
-	STORE x5,   5 * REGBYTES(sp)
-
-	csrr  t0,  mstatus
-	andi  t0, t0, 8
-	/* if MIE be enabled,set MPIE */
-	beqz  t0, 1f
-	li    t0, 0x80
-
-1:  STORE t0,   2 * REGBYTES(sp)
-	STORE x4,   4 * REGBYTES(sp)
-
-	STORE x6,   6 * REGBYTES(sp)
-    STORE x7,   7 * REGBYTES(sp)
-    STORE x8,   8 * REGBYTES(sp)
-    STORE x9,   9 * REGBYTES(sp)
-    STORE x10, 10 * REGBYTES(sp)
-    STORE x11, 11 * REGBYTES(sp)
-    STORE x12, 12 * REGBYTES(sp)
-    STORE x13, 13 * REGBYTES(sp)
-    STORE x14, 14 * REGBYTES(sp)
-    STORE x15, 15 * REGBYTES(sp)
-    STORE x16, 16 * REGBYTES(sp)
-    STORE x17, 17 * REGBYTES(sp)
-    STORE x18, 18 * REGBYTES(sp)
-    STORE x19, 19 * REGBYTES(sp)
-    STORE x20, 20 * REGBYTES(sp)
-    STORE x21, 21 * REGBYTES(sp)
-    STORE x22, 22 * REGBYTES(sp)
-    STORE x23, 23 * REGBYTES(sp)
-    STORE x24, 24 * REGBYTES(sp)
-    STORE x25, 25 * REGBYTES(sp)
-    STORE x26, 26 * REGBYTES(sp)
-    STORE x27, 27 * REGBYTES(sp)
-    STORE x28, 28 * REGBYTES(sp)
-    STORE x29, 29 * REGBYTES(sp)
-    STORE x30, 30 * REGBYTES(sp)
-    STORE x31, 31 * REGBYTES(sp)
-
-	/* get "to" thread sp */
-	LOAD  sp,  0(a1)
-	j  rt_hw_context_switch_exit
-
-
-.global rt_hw_context_switch_exit
-rt_hw_context_switch_exit:
-    /* resw ra to mepc */
-    LOAD a0,   0 * REGBYTES(sp)
-    csrw mepc, a0
-
-    LOAD x1,   1 * REGBYTES(sp)
-	/* keep machine mode */
-	li    a0,      0x1800
-	csrs  mstatus, a0
-	/* resume MPIE */
-	LOAD  a0,      2*REGBYTES(sp)
-    csrs  mstatus, a0
-
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
-    addi sp,  sp, 32 * REGBYTES
-
- /* load float reg */
-#ifdef ARCH_RISCV_FPU
-
-    FLOAD   f0, 0 * FREGBYTES(sp)
-    FLOAD   f1, 1 * FREGBYTES(sp)
-    FLOAD   f2, 2 * FREGBYTES(sp)
-    FLOAD   f3, 3 * FREGBYTES(sp)
-    FLOAD   f4, 4 * FREGBYTES(sp)
-    FLOAD   f5, 5 * FREGBYTES(sp)
-    FLOAD   f6, 6 * FREGBYTES(sp)
-    FLOAD   f7, 7 * FREGBYTES(sp)
-    FLOAD   f8, 8 * FREGBYTES(sp)
-    FLOAD   f9, 9 * FREGBYTES(sp)
-    FLOAD   f10, 10 * FREGBYTES(sp)
-    FLOAD   f11, 11 * FREGBYTES(sp)
-    FLOAD   f12, 12 * FREGBYTES(sp)
-    FLOAD   f13, 13 * FREGBYTES(sp)
-    FLOAD   f14, 14 * FREGBYTES(sp)
-    FLOAD   f15, 15 * FREGBYTES(sp)
-    FLOAD   f16, 16 * FREGBYTES(sp)
-    FLOAD   f17, 17 * FREGBYTES(sp)
-    FLOAD   f18, 18 * FREGBYTES(sp)
-    FLOAD   f19, 19 * FREGBYTES(sp)
-    FLOAD   f20, 20 * FREGBYTES(sp)
-    FLOAD   f21, 21 * FREGBYTES(sp)
-    FLOAD   f22, 22 * FREGBYTES(sp)
-    FLOAD   f23, 23 * FREGBYTES(sp)
-    FLOAD   f24, 24 * FREGBYTES(sp)
-    FLOAD   f25, 25 * FREGBYTES(sp)
-    FLOAD   f26, 26 * FREGBYTES(sp)
-    FLOAD   f27, 27 * FREGBYTES(sp)
-    FLOAD   f28, 28 * FREGBYTES(sp)
-    FLOAD   f29, 29 * FREGBYTES(sp)
-    FLOAD   f30, 30 * FREGBYTES(sp)
-    FLOAD   f31, 31 * FREGBYTES(sp)
-    addi    sp, sp, 32 * FREGBYTES
-#endif
-
-    mret
diff --git a/libcpu/risc-v/ch32v1/cpuport.c b/libcpu/risc-v/ch32v1/cpuport.c
deleted file mode 100644
index 14bf15ccc2..0000000000
--- a/libcpu/risc-v/ch32v1/cpuport.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "ch32v10x.h"
-#include "cpuport.h"
-
-#ifndef RT_USING_SMP
-volatile rt_ubase_t  rt_interrupt_from_thread = 0;
-volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
-volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
-#endif
-
-struct rt_hw_stack_frame
-{
-    rt_ubase_t epc;        /* epc - epc    - program counter                     */
-    rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
-    rt_ubase_t mstatus;    /*              - machine status register             */
-    rt_ubase_t gp;         /* x3  - gp     - global pointer                      */
-    rt_ubase_t tp;         /* x4  - tp     - thread pointer                      */
-    rt_ubase_t t0;         /* x5  - t0     - temporary register 0                */
-    rt_ubase_t t1;         /* x6  - t1     - temporary register 1                */
-    rt_ubase_t t2;         /* x7  - t2     - temporary register 2                */
-    rt_ubase_t s0_fp;      /* x8  - s0/fp  - saved register 0 or frame pointer   */
-    rt_ubase_t s1;         /* x9  - s1     - saved register 1                    */
-    rt_ubase_t a0;         /* x10 - a0     - return value or function argument 0 */
-    rt_ubase_t a1;         /* x11 - a1     - return value or function argument 1 */
-    rt_ubase_t a2;         /* x12 - a2     - function argument 2                 */
-    rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
-    rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
-    rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
-    rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
-    rt_ubase_t a7;         /* x17 - s7     - function argument 7                 */
-    rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
-    rt_ubase_t s3;         /* x19 - s3     - saved register 3                    */
-    rt_ubase_t s4;         /* x20 - s4     - saved register 4                    */
-    rt_ubase_t s5;         /* x21 - s5     - saved register 5                    */
-    rt_ubase_t s6;         /* x22 - s6     - saved register 6                    */
-    rt_ubase_t s7;         /* x23 - s7     - saved register 7                    */
-    rt_ubase_t s8;         /* x24 - s8     - saved register 8                    */
-    rt_ubase_t s9;         /* x25 - s9     - saved register 9                    */
-    rt_ubase_t s10;        /* x26 - s10    - saved register 10                   */
-    rt_ubase_t s11;        /* x27 - s11    - saved register 11                   */
-    rt_ubase_t t3;         /* x28 - t3     - temporary register 3                */
-    rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
-    rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
-    rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
-
-/* float register */
-#ifdef ARCH_RISCV_FPU
-    rv_floatreg_t f0;      /* f0  */
-    rv_floatreg_t f1;      /* f1  */
-    rv_floatreg_t f2;      /* f2  */
-    rv_floatreg_t f3;      /* f3  */
-    rv_floatreg_t f4;      /* f4  */
-    rv_floatreg_t f5;      /* f5  */
-    rv_floatreg_t f6;      /* f6  */
-    rv_floatreg_t f7;      /* f7  */
-    rv_floatreg_t f8;      /* f8  */
-    rv_floatreg_t f9;      /* f9  */
-    rv_floatreg_t f10;     /* f10 */
-    rv_floatreg_t f11;     /* f11 */
-    rv_floatreg_t f12;     /* f12 */
-    rv_floatreg_t f13;     /* f13 */
-    rv_floatreg_t f14;     /* f14 */
-    rv_floatreg_t f15;     /* f15 */
-    rv_floatreg_t f16;     /* f16 */
-    rv_floatreg_t f17;     /* f17 */
-    rv_floatreg_t f18;     /* f18 */
-    rv_floatreg_t f19;     /* f19 */
-    rv_floatreg_t f20;     /* f20 */
-    rv_floatreg_t f21;     /* f21 */
-    rv_floatreg_t f22;     /* f22 */
-    rv_floatreg_t f23;     /* f23 */
-    rv_floatreg_t f24;     /* f24 */
-    rv_floatreg_t f25;     /* f25 */
-    rv_floatreg_t f26;     /* f26 */
-    rv_floatreg_t f27;     /* f27 */
-    rv_floatreg_t f28;     /* f28 */
-    rv_floatreg_t f29;     /* f29 */
-    rv_floatreg_t f30;     /* f30 */
-    rv_floatreg_t f31;     /* f31 */
-#endif
-};
-
-/*
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void       *tentry,
-                             void       *parameter,
-                             rt_uint8_t *stack_addr,
-                             void       *texit)
-{
-    struct rt_hw_stack_frame *frame;
-    rt_uint8_t *stk;
-    int i;
-
-    stk  = stack_addr + sizeof(rt_ubase_t);
-    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
-    stk -= sizeof(struct rt_hw_stack_frame);
-
-    frame = (struct rt_hw_stack_frame *)stk;
-
-    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
-    {
-        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
-    }
-
-    frame->ra = (rt_ubase_t)texit;
-    frame->a0 = (rt_ubase_t)parameter;
-    frame->epc = (rt_ubase_t)tentry;
-
-    /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
-    frame->mstatus = 0x00001880;
-    return stk;
-}
-
-/*
- * trigger soft interrupt
- */
-void sw_setpend(void)
-{
-    NVIC_SetPendingIRQ(Software_IRQn);
-}
-
-/*
- * clear soft interrupt
- */
-void sw_clearpend(void)
-{
-    NVIC_ClearPendingIRQ(Software_IRQn);
-}
-
-/*
- * disable interrupt and save mstatus
- */
-rt_base_t rt_hw_interrupt_disable(void)
-{
-    register rt_base_t value = 0;
-    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
-    return value;
-}
-
-/*
- * enable interrupt and resume mstatus
- */
-void rt_hw_interrupt_enable(rt_base_t level)
-{
-    asm("csrw mstatus, %0": :"r"(level));
-}
-
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- * #endif
- */
-void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
-{
-    if (rt_thread_switch_interrupt_flag == 0)
-        rt_interrupt_from_thread = from;
-
-    rt_interrupt_to_thread = to;
-    rt_thread_switch_interrupt_flag = 1;
-    /* switch just in sw_handler */
-    sw_setpend();
-}
-
-
-
-/* shutdown CPU */
-void rt_hw_cpu_shutdown(void)
-{
-    rt_base_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
diff --git a/libcpu/risc-v/ch32v1/interrupt_gcc.S b/libcpu/risc-v/ch32v1/interrupt_gcc.S
deleted file mode 100644
index 56410c37d9..0000000000
--- a/libcpu/risc-v/ch32v1/interrupt_gcc.S
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- */
- 
-#include "cpuport.h"
-
-.global SW_handler
-.align 2
-SW_handler:
-    /* save all from thread context */
-#ifdef ARCH_RISCV_FPU
-    addi    sp, sp, -32 * FREGBYTES
-    FSTORE  f0, 0 * FREGBYTES(sp)
-    FSTORE  f1, 1 * FREGBYTES(sp)
-    FSTORE  f2, 2 * FREGBYTES(sp)
-    FSTORE  f3, 3 * FREGBYTES(sp)
-    FSTORE  f4, 4 * FREGBYTES(sp)
-    FSTORE  f5, 5 * FREGBYTES(sp)
-    FSTORE  f6, 6 * FREGBYTES(sp)
-    FSTORE  f7, 7 * FREGBYTES(sp)
-    FSTORE  f8, 8 * FREGBYTES(sp)
-    FSTORE  f9, 9 * FREGBYTES(sp)
-    FSTORE  f10, 10 * FREGBYTES(sp)
-    FSTORE  f11, 11 * FREGBYTES(sp)
-    FSTORE  f12, 12 * FREGBYTES(sp)
-    FSTORE  f13, 13 * FREGBYTES(sp)
-    FSTORE  f14, 14 * FREGBYTES(sp)
-    FSTORE  f15, 15 * FREGBYTES(sp)
-    FSTORE  f16, 16 * FREGBYTES(sp)
-    FSTORE  f17, 17 * FREGBYTES(sp)
-    FSTORE  f18, 18 * FREGBYTES(sp)
-    FSTORE  f19, 19 * FREGBYTES(sp)
-    FSTORE  f20, 20 * FREGBYTES(sp)
-    FSTORE  f21, 21 * FREGBYTES(sp)
-    FSTORE  f22, 22 * FREGBYTES(sp)
-    FSTORE  f23, 23 * FREGBYTES(sp)
-    FSTORE  f24, 24 * FREGBYTES(sp)
-    FSTORE  f25, 25 * FREGBYTES(sp)
-    FSTORE  f26, 26 * FREGBYTES(sp)
-    FSTORE  f27, 27 * FREGBYTES(sp)
-    FSTORE  f28, 28 * FREGBYTES(sp)
-    FSTORE  f29, 29 * FREGBYTES(sp)
-    FSTORE  f30, 30 * FREGBYTES(sp)
-    FSTORE  f31, 31 * FREGBYTES(sp)
-#endif
-
-    addi sp, sp, -32 * REGBYTES
-    STORE x5,   5 * REGBYTES(sp)
-
-    /* saved MPIE */
- 	li    t0,   0x80
-    STORE t0,   2 * REGBYTES(sp)
-
-    STORE x1,   1 * REGBYTES(sp)
-    STORE x4,   4 * REGBYTES(sp)
-    STORE x6,   6 * REGBYTES(sp)
-    STORE x7,   7 * REGBYTES(sp)
-    STORE x8,   8 * REGBYTES(sp)
-    STORE x9,   9 * REGBYTES(sp)
-    STORE x10, 10 * REGBYTES(sp)
-    STORE x11, 11 * REGBYTES(sp)
-    STORE x12, 12 * REGBYTES(sp)
-    STORE x13, 13 * REGBYTES(sp)
-    STORE x14, 14 * REGBYTES(sp)
-    STORE x15, 15 * REGBYTES(sp)
-    STORE x16, 16 * REGBYTES(sp)
-    STORE x17, 17 * REGBYTES(sp)
-    STORE x18, 18 * REGBYTES(sp)
-    STORE x19, 19 * REGBYTES(sp)
-    STORE x20, 20 * REGBYTES(sp)
-    STORE x21, 21 * REGBYTES(sp)
-    STORE x22, 22 * REGBYTES(sp)
-    STORE x23, 23 * REGBYTES(sp)
-    STORE x24, 24 * REGBYTES(sp)
-    STORE x25, 25 * REGBYTES(sp)
-    STORE x26, 26 * REGBYTES(sp)
-    STORE x27, 27 * REGBYTES(sp)
-    STORE x28, 28 * REGBYTES(sp)
-    STORE x29, 29 * REGBYTES(sp)
-    STORE x30, 30 * REGBYTES(sp)
-    STORE x31, 31 * REGBYTES(sp)
-
-    /* switch to interrupt stack */
-	csrrw sp,mscratch,sp
-    call  rt_interrupt_enter
-    /* clear interrupt */
-    jal   sw_clearpend
-    call  rt_interrupt_leave
-    /* switch to from thread stack */
-	csrrw sp,mscratch,sp
-
-    /* if rt_thread_switch_interrupt_flag=1,then clear it  */
-    la    s0, rt_thread_switch_interrupt_flag
-    lw    s2, 0(s0)
-    beqz  s2, 1f
-    sw    zero, 0(s0)
-#1:
-    csrr  a0, mepc
-    STORE a0, 0 * REGBYTES(sp)
-
-    la    s0, rt_interrupt_from_thread
-    LOAD  s1, 0(s0)
-    STORE sp, 0(s1)
-
-    la    s0, rt_interrupt_to_thread
-    LOAD  s1, 0(s0)
-    LOAD  sp, 0(s1)
-
-    LOAD  a0,  0 * REGBYTES(sp)
-    csrw  mepc, a0
-
-1:  LOAD  x1,   1 * REGBYTES(sp)
-
-	li t0,0x1800
-	csrs mstatus, t0
-	LOAD t0, 2*REGBYTES(sp)
-	csrs mstatus, t0
-
-    LOAD  x4,   4 * REGBYTES(sp)
-    LOAD  x5,   5 * REGBYTES(sp)
-    LOAD  x6,   6 * REGBYTES(sp)
-    LOAD  x7,   7 * REGBYTES(sp)
-    LOAD  x8,   8 * REGBYTES(sp)
-    LOAD  x9,   9 * REGBYTES(sp)
-    LOAD  x10, 10 * REGBYTES(sp)
-    LOAD  x11, 11 * REGBYTES(sp)
-    LOAD  x12, 12 * REGBYTES(sp)
-    LOAD  x13, 13 * REGBYTES(sp)
-    LOAD  x14, 14 * REGBYTES(sp)
-    LOAD  x15, 15 * REGBYTES(sp)
-    LOAD  x16, 16 * REGBYTES(sp)
-    LOAD  x17, 17 * REGBYTES(sp)
-    LOAD  x18, 18 * REGBYTES(sp)
-    LOAD  x19, 19 * REGBYTES(sp)
-    LOAD  x20, 20 * REGBYTES(sp)
-    LOAD  x21, 21 * REGBYTES(sp)
-    LOAD  x22, 22 * REGBYTES(sp)
-    LOAD  x23, 23 * REGBYTES(sp)
-    LOAD  x24, 24 * REGBYTES(sp)
-    LOAD  x25, 25 * REGBYTES(sp)
-    LOAD  x26, 26 * REGBYTES(sp)
-    LOAD  x27, 27 * REGBYTES(sp)
-    LOAD  x28, 28 * REGBYTES(sp)
-    LOAD  x29, 29 * REGBYTES(sp)
-    LOAD  x30, 30 * REGBYTES(sp)
-    LOAD  x31, 31 * REGBYTES(sp)
-    addi  sp, sp, 32 * REGBYTES
-
-    /* load float reg */
-#ifdef ARCH_RISCV_FPU
-    FLOAD   f0, 0 * FREGBYTES(sp)
-    FLOAD   f1, 1 * FREGBYTES(sp)
-    FLOAD   f2, 2 * FREGBYTES(sp)
-    FLOAD   f3, 3 * FREGBYTES(sp)
-    FLOAD   f4, 4 * FREGBYTES(sp)
-    FLOAD   f5, 5 * FREGBYTES(sp)
-    FLOAD   f6, 6 * FREGBYTES(sp)
-    FLOAD   f7, 7 * FREGBYTES(sp)
-    FLOAD   f8, 8 * FREGBYTES(sp)
-    FLOAD   f9, 9 * FREGBYTES(sp)
-    FLOAD   f10, 10 * FREGBYTES(sp)
-    FLOAD   f11, 11 * FREGBYTES(sp)
-    FLOAD   f12, 12 * FREGBYTES(sp)
-    FLOAD   f13, 13 * FREGBYTES(sp)
-    FLOAD   f14, 14 * FREGBYTES(sp)
-    FLOAD   f15, 15 * FREGBYTES(sp)
-    FLOAD   f16, 16 * FREGBYTES(sp)
-    FLOAD   f17, 17 * FREGBYTES(sp)
-    FLOAD   f18, 18 * FREGBYTES(sp)
-    FLOAD   f19, 19 * FREGBYTES(sp)
-    FLOAD   f20, 20 * FREGBYTES(sp)
-    FLOAD   f21, 21 * FREGBYTES(sp)
-    FLOAD   f22, 22 * FREGBYTES(sp)
-    FLOAD   f23, 23 * FREGBYTES(sp)
-    FLOAD   f24, 24 * FREGBYTES(sp)
-    FLOAD   f25, 25 * FREGBYTES(sp)
-    FLOAD   f26, 26 * FREGBYTES(sp)
-    FLOAD   f27, 27 * FREGBYTES(sp)
-    FLOAD   f28, 28 * FREGBYTES(sp)
-    FLOAD   f29, 29 * FREGBYTES(sp)
-    FLOAD   f30, 30 * FREGBYTES(sp)
-    FLOAD   f31, 31 * FREGBYTES(sp)
-    addi    sp, sp, 32 * FREGBYTES
-#endif
-    mret
diff --git a/libcpu/risc-v/ch32v3/cpuport.h b/libcpu/risc-v/ch32v3/cpuport.h
deleted file mode 100644
index 5034b2386c..0000000000
--- a/libcpu/risc-v/ch32v3/cpuport.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- */
-
-#ifndef CPUPORT_H__
-#define CPUPORT_H__
-
-/* bytes of register width  */
-//#define ARCH_RISCV_FPU
-#define ARCH_RISCV_FPU_S
-
-#ifdef ARCH_CPU_64BIT
-#define STORE                   sd
-#define LOAD                    ld
-#define REGBYTES                8
-#else
-#define STORE                   sw
-#define LOAD                    lw
-#define REGBYTES                4
-#endif
-
-/* FPU */
-#ifdef ARCH_RISCV_FPU
-#ifdef ARCH_RISCV_FPU_D
-#define FSTORE                  fsd
-#define FLOAD                   fld
-#define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t
-#endif
-#ifdef ARCH_RISCV_FPU_S
-#define FSTORE                  fsw
-#define FLOAD                   flw
-#define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t
-#endif
-#endif
-
-#endif