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authorZYH <[email protected]>2018-02-19 15:31:28 +0800
committerZYH <[email protected]>2018-02-19 15:31:28 +0800
commitccf15490c9c649e313963578960a93d82a89be8f (patch)
tree8ffc6f32d7eeec887ef43a79fe64c29d91a879b3
parent40b580b223ca1e00cb52e71c029de1f48dea689d (diff)
[Bsp][Tina]Fix uart bug
-rw-r--r--bsp/allwinner_tina/drivers/drv_uart.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/bsp/allwinner_tina/drivers/drv_uart.c b/bsp/allwinner_tina/drivers/drv_uart.c
index 1c48c53dca..8dd7e68bee 100644
--- a/bsp/allwinner_tina/drivers/drv_uart.c
+++ b/bsp/allwinner_tina/drivers/drv_uart.c
@@ -184,16 +184,19 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
if ((rt_uint32_t)(uart->hw_base) == UART0_BASE_ADDR)
{
bus_gate_clk_enalbe(UART0_GATING);
+ bus_software_reset_disalbe(UART0_GATING);
bus_software_reset_enalbe(UART0_GATING);
}
else if ((rt_uint32_t)(uart->hw_base) == UART1_BASE_ADDR)
{
bus_gate_clk_enalbe(UART1_GATING);
+ bus_software_reset_disalbe(UART1_GATING);
bus_software_reset_enalbe(UART1_GATING);
}
else if ((rt_uint32_t)(uart->hw_base) == UART2_BASE_ADDR)
{
bus_gate_clk_enalbe(UART2_GATING);
+ bus_software_reset_disalbe(UART2_GATING);
bus_software_reset_enalbe(UART2_GATING);
}
else