diff options
| author | wuyangyong <[email protected]> | 2011-11-05 10:25:23 +0000 |
|---|---|---|
| committer | wuyangyong <[email protected]> | 2011-11-05 10:25:23 +0000 |
| commit | d246a71b91c2f8f870f5d31783f979a48aadee81 (patch) | |
| tree | e9bacb017451bfcc4aa63b4a3fdf865998b3ad30 | |
| parent | f344f002785b1e7ded48d62282f8a5de9a766dce (diff) | |
update lpc1788 bsp
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1784 bbd45198-f89e-11dd-88c7-29a3b14d5316
| -rw-r--r-- | bsp/lpc178x/application.c | 62 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/SConscript | 2 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/board.c | 39 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/board.h | 22 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/emac.c | 54 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/lpc177x_8x_emc.c | 757 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/lpc177x_8x_emc.h | 361 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/lpc17xx_lcd.c | 13 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/lpc17xx_lcd.h | 6 | ||||
| -rw-r--r-- | bsp/lpc178x/drivers/uart.c | 38 | ||||
| -rw-r--r-- | bsp/lpc178x/project.uvproj | 18 | ||||
| -rw-r--r-- | bsp/lpc178x/rtconfig.h | 14 | ||||
| -rw-r--r-- | bsp/lpc178x/rtconfig.py | 2 |
13 files changed, 1301 insertions, 87 deletions
diff --git a/bsp/lpc178x/application.c b/bsp/lpc178x/application.c index 30ce2b7fd4..8b7265d9ce 100644 --- a/bsp/lpc178x/application.c +++ b/bsp/lpc178x/application.c @@ -16,12 +16,14 @@ */
/**
- * @addtogroup LPC17
+ * @addtogroup LPC1700
*/
/*@{*/
#include <rtthread.h>
+#include <board.h>
+
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs_init.h>
@@ -40,19 +42,6 @@ /* thread phase init */
void rt_init_thread_entry(void *parameter)
{
-// unsigned int count=0;
-//
-// while (1)
-// {
-// /* led1 on */
-// rt_kprintf("on count : %d\r\n",count);
-// count++;
-// rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
-//
-// /* led1 off */
-// rt_kprintf("led off\r\n");
-// rt_thread_delay( RT_TICK_PER_SECOND/2 );
-// }
/* Filesystem Initialization */
#ifdef RT_USING_DFS
@@ -91,10 +80,55 @@ void rt_init_thread_entry(void *parameter) #endif
}
+// init led
+#define rt_hw_led_init() LPC_GPIO2->DIR |= 1<<25;
+// trun on led n
+#define rt_hw_led_on(n) LPC_GPIO2->CLR |= 1<<25;
+// trun off led n
+#define rt_hw_led_off(n) LPC_GPIO2->SET |= 1<<25;
+
+ALIGN(RT_ALIGN_SIZE)
+static char thread_led_stack[1024];
+struct rt_thread thread_led;
+static void rt_thread_entry_led(void* parameter)
+{
+ unsigned int count=0;
+
+ rt_hw_led_init();
+
+ while (1)
+ {
+ /* led on */
+#ifndef RT_USING_FINSH
+ rt_kprintf("led on,count : %d\r\n",count);
+#endif
+ count++;
+ rt_hw_led_on(1);
+ /* sleep 0.5 second and switch to other thread */
+ rt_thread_delay(RT_TICK_PER_SECOND/2);
+
+ /* led off */
+#ifndef RT_USING_FINSH
+ rt_kprintf("led off\r\n");
+#endif
+ rt_hw_led_off(1);
+ rt_thread_delay(RT_TICK_PER_SECOND/2);
+ }
+}
+
int rt_application_init()
{
rt_thread_t init_thread;
+ //------- init led thread
+ rt_thread_init(&thread_led,
+ "led",
+ rt_thread_entry_led,
+ RT_NULL,
+ &thread_led_stack[0],
+ sizeof(thread_led_stack),11,5);
+ rt_thread_startup(&thread_led);
+
#if (RT_THREAD_PRIORITY_MAX == 32)
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
diff --git a/bsp/lpc178x/drivers/SConscript b/bsp/lpc178x/drivers/SConscript index 34fe4de75f..3b1dfa33e5 100644 --- a/bsp/lpc178x/drivers/SConscript +++ b/bsp/lpc178x/drivers/SConscript @@ -12,7 +12,7 @@ if GetDepend('RT_USING_LWIP') == False: src_tmp = copy.copy(src)
count = 0
for i in range(0, len(src_tmp)):
- s = str(src_tmp[i])
+ s = os.path.basename(str(src_tmp[i]))
if s in src_need_remove:
src.pop(i-count)
count = count + 1
diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c index 1504a444aa..787f0ad645 100644 --- a/bsp/lpc178x/drivers/board.c +++ b/bsp/lpc178x/drivers/board.c @@ -34,13 +34,13 @@ */
void rt_hw_timer_handler(void)
{
- /* enter interrupt */
- rt_interrupt_enter();
+ /* enter interrupt */
+ rt_interrupt_enter();
- rt_tick_increase();
+ rt_tick_increase();
- /* leave interrupt */
- rt_interrupt_leave();
+ /* leave interrupt */
+ rt_interrupt_leave();
}
void SysTick_Handler(void)
@@ -53,25 +53,32 @@ void SysTick_Handler(void) */
void rt_hw_board_init()
{
- /* NVIC Configuration */
+ /* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
- /* Set the Vector Table base location at 0x10000000 */
- SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
+ /* Set the Vector Table base location at 0x10000000 */
+ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
- /* Set the Vector Table base location at 0x00000000 */
- SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
+ /* Set the Vector Table base location at 0x00000000 */
+ SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
- /* init systick */
- SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND - 1);
- /* set pend exception priority */
- NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+ /* init systick */
+ SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND - 1);
+ /* set pend exception priority */
+ NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
- rt_hw_uart_init();
- rt_console_set_device( CONSOLE_DEVICE );
+ rt_hw_uart_init();
+ rt_console_set_device( CONSOLE_DEVICE );
rt_kprintf("\r\n\r\nSystemInit......\r\n");
+
+#if LPC_EXT_SDRAM == 1
+ {
+ SDRAM_Init();
+ }
+#endif
+
}
/*@}*/
diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h index 45f6d56a82..38937d362b 100644 --- a/bsp/lpc178x/drivers/board.h +++ b/bsp/lpc178x/drivers/board.h @@ -16,14 +16,28 @@ #ifndef __BOARD_H__
#define __BOARD_H__
+#include "LPC177x_8x.h"
+
+/* whether use board external SDRAM memory */
+// <e>Use external SDRAM memory on the board
+// <i>Enable External SDRAM memory
+#define LPC_EXT_SDRAM 0
+// <o>Begin Address of External SDRAM
+// <i>Default: 0x60000000
+#define LPC_EXT_SDRAM_BEGIN 0xA0000000 /* the begining address of external SDRAM */
+// <o>End Address of External SDRAM
+// <i>Default: 0x60000000
+#define LPC_EXT_SDRAM_END 0xA4000000 /* the end address of external SDRAM */
+// </e>
+
/* RT_USING_UART */
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_USING_UART0
-#define RT_USING_UART1
-#define RT_USING_UART2
+//#define RT_USING_UART1
+//#define RT_USING_UART2
-#define CONSOLE_DEVICE "uart1"
-#define FINSH_DEVICE_NAME "uart1"
+#define CONSOLE_DEVICE "uart0"
+#define FINSH_DEVICE_NAME CONSOLE_DEVICE
void rt_hw_board_init(void);
diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c index 06bf61693e..9c78088ee2 100644 --- a/bsp/lpc178x/drivers/emac.c +++ b/bsp/lpc178x/drivers/emac.c @@ -22,7 +22,8 @@ struct lpc17xx_emac rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct lpc17xx_emac lpc17xx_emac_device;
-static struct rt_semaphore sem_slot, sem_lock;
+static struct rt_semaphore sem_lock;
+static struct rt_event tx_event;
/* Local Function Prototypes */
static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value);
@@ -35,10 +36,7 @@ void ENET_IRQHandler(void) /* enter interrupt */
rt_interrupt_enter();
- status = LPC_EMAC->IntStatus & LPC_EMAC->IntEnable;
-
- /* Clear the interrupt. */
- LPC_EMAC->IntClear = status;
+ status = LPC_EMAC->IntStatus;
if (status & INT_RX_DONE)
{
@@ -50,10 +48,23 @@ void ENET_IRQHandler(void) }
else if (status & INT_TX_DONE)
{
- /* release one slot */
- rt_sem_release(&sem_slot);
+ /* set event */
+ rt_event_send(&tx_event, 0x01);
+ }
+
+ if (status & INT_RX_OVERRUN)
+ {
+ rt_kprintf("rx overrun\n");
}
+ if (status & INT_TX_UNDERRUN)
+ {
+ rt_kprintf("tx underrun\n");
+ }
+
+ /* Clear the interrupt. */
+ LPC_EMAC->IntClear = status;
+
/* leave interrupt */
rt_interrupt_leave();
}
@@ -384,8 +395,22 @@ rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p) struct pbuf *q;
rt_uint8_t *ptr;
- /* take a slot */
- rt_sem_take(&sem_slot, RT_WAITING_FOREVER);
+ /* calculate next index */
+ IndexNext = LPC_EMAC->TxProduceIndex + 1;
+ if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+
+ /* check whether block is full */
+ while (IndexNext == LPC_EMAC->TxConsumeIndex)
+ {
+ rt_err_t result;
+ rt_uint32_t recved;
+
+ /* there is no block yet, wait a flag */
+ result = rt_event_recv(&tx_event, 0x01,
+ RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+
+ RT_ASSERT(result == RT_EOK);
+ }
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
@@ -475,7 +500,7 @@ struct pbuf *lpc17xx_emac_rx(rt_device_t dev) void lpc17xx_emac_hw_init(void)
{
- rt_sem_init(&sem_slot, "tx_slot", NUM_TX_FRAG, RT_IPC_FLAG_FIFO);
+ rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
/* set autonegotiation mode */
@@ -486,9 +511,9 @@ void lpc17xx_emac_hw_init(void) lpc17xx_emac_device.dev_addr[1] = 0x60;
lpc17xx_emac_device.dev_addr[2] = 0x37;
/* set mac address: (only for test) */
- lpc17xx_emac_device.dev_addr[3] = 0xA2;
- lpc17xx_emac_device.dev_addr[4] = 0x45;
- lpc17xx_emac_device.dev_addr[5] = 0x5E;
+ lpc17xx_emac_device.dev_addr[3] = 0x12;
+ lpc17xx_emac_device.dev_addr[4] = 0x34;
+ lpc17xx_emac_device.dev_addr[5] = 0x56;
lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
@@ -508,9 +533,8 @@ void lpc17xx_emac_hw_init(void) #include <finsh.h>
void emac_dump()
{
-// rt_kprintf("IntCount : %d\n", intcount);
- rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
rt_kprintf("Command : %08x\n", LPC_EMAC->Command);
+ rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.c b/bsp/lpc178x/drivers/lpc177x_8x_emc.c new file mode 100644 index 0000000000..b136e863a8 --- /dev/null +++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.c @@ -0,0 +1,757 @@ +/**********************************************************************
+* $Id$ lpc177x_8x_emc.c 2011-06-02
+*//**
+* @file lpc177x_8x_emc.c
+* @brief Contains all functions support for EMC firmware library
+* on LPC177x_8x
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#include "lpc177x_8x_emc.h"
+#include "lpc177x_8x_clkpwr.h"
+#include "lpc177x_8x_pinsel.h"
+
+
+/*********************************************************************//**
+ * @brief EMC initialize
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void EMC_Init(void)
+{
+ uint8_t i;
+
+ /* Enable clock for EMC */
+// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
+// LPC_EMC->Control = 0x00000001;
+// LPC_EMC->Config = 0x00000000;
+
+ LPC_SC->PCONP |= 0x00000800;
+ LPC_SC->EMCDLYCTL = 0x00001010;
+ LPC_EMC->Control = 0x00000001;
+ LPC_EMC->Config = 0x00000000;
+
+ /* Pin configuration:
+ * P2.14 - /EMC_CS2
+ * P2.15 - /EMC_CS3
+ *
+ * P2.16 - /EMC_CAS
+ * P2.17 - /EMC_RAS
+ * P2.18 - EMC_CLK[0]
+ * P2.19 - EMC_CLK[1]
+ *
+ * P2.20 - EMC_DYCS0
+ * P2.22 - EMC_DYCS1
+ * P2.22 - EMC_DYCS2
+ * P2.23 - EMC_DYCS3
+ *
+ * P2.24 - EMC_CKE0
+ * P2.25 - EMC_CKE1
+ * P2.26 - EMC_CKE2
+ * P2.27 - EMC_CKE3
+ *
+ * P2.28 - EMC_DQM0
+ * P2.29 - EMC_DQM1
+ * P2.30 - EMC_DQM2
+ * P2.31 - EMC_DQM3
+ *
+ * P3.0-P3.31 - EMC_D[0-31]
+ * P4.0-P4.23 - EMC_A[0-23]
+ *
+ * P4.24 - /EMC_OE
+ * P4.25 - /EMC_WE
+ *
+ * P4.30 - /EMC_CS0
+ * P4.31 - /EMC_CS1 + */
+ PINSEL_ConfigPin(2,14,1);
+ PINSEL_ConfigPin(2,15,1);
+ PINSEL_ConfigPin(2,16,1);
+ PINSEL_ConfigPin(2,17,1);
+ PINSEL_ConfigPin(2,18,1);
+ PINSEL_ConfigPin(2,19,1);
+ PINSEL_ConfigPin(2,20,1);
+ PINSEL_ConfigPin(2,21,1);
+ PINSEL_ConfigPin(2,22,1);
+ PINSEL_ConfigPin(2,23,1);
+ PINSEL_ConfigPin(2,24,1);
+ PINSEL_ConfigPin(2,25,1);
+ PINSEL_ConfigPin(2,26,1);
+ PINSEL_ConfigPin(2,27,1);
+ PINSEL_ConfigPin(2,28,1);
+ PINSEL_ConfigPin(2,29,1);
+ PINSEL_ConfigPin(2,30,1);
+ PINSEL_ConfigPin(2,31,1);
+
+ PINSEL_ConfigPin(5,0,1);
+ PINSEL_ConfigPin(5,1,1);
+
+ for(i = 0; i < 32; i++)
+ {
+ PINSEL_ConfigPin(3,i,1);
+ PINSEL_ConfigPin(4,i,1);
+ }
+}
+/*********************************************************************//**
+ * @brief Configure Little Endian/Big Endian mode for EMC
+ * @param[in] endia_mode Endian mode, should be:
+ * - EMC_LITTLE_ENDIAN_MODE: Little-endian mode
+ * - EMC_BIG_ENDIAN_MODE : Big-endian mode
+ * @return None
+ **********************************************************************/
+void EMC_ConfigEndianMode(uint32_t endian_mode)
+{
+ LPC_EMC->Config = ((LPC_EMC->Config & 0x01)|endian_mode) & EMC_Config_MASK;
+}
+
+/****************** Group of Dynamic control functions************************/
+/*********************************************************************//**
+ * @brief Set the value for dynamic clock enable bit
+ * @param[in] clock_enable clock enable mode, should be:
+ * - 0: Clock enable of idle devices are deasserted to
+ * save power
+ * - 1: All clock enables are driven HIGH continuously
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlClockEnable(uint32_t clock_enable)
+{
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl) |clock_enable);
+}
+
+/*********************************************************************//**
+ * @brief Set the value for dynamic memory clock control:
+ * stops or runs continuously
+ * @param[in] clock_control clock control mode, should be:
+ * - 0: CLKOUT stops when all SDRAMs are idle and
+ * during self-refresh mode
+ * - 1: CLKOUT runs continuously
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlClockControl(int32_t clock_control)
+{
+ uint32_t mask = ~(uint32_t)(2);
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |clock_control);
+}
+
+/*********************************************************************//**
+ * @brief Switch the Self-refresh mode between normal and self-refresh mode
+ * @param[in] self_refresh_mode self refresh mode, should be:
+ * - 0: Normal mode
+ * - 1: Enter self-refresh mode
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
+{
+ uint32_t mask = ~(uint32_t)(4);
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |self_refresh_mode);
+}
+
+/*********************************************************************//**
+ * @brief Enable/disable CLKOUT
+ * @param[in] MMC_val Memory clock control mode, should be:
+ * - 0: CLKOUT enabled
+ * - 1: CLKOUT disabled
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlMMC(uint32_t MMC_val)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(5));
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |MMC_val);
+}
+
+/*********************************************************************//**
+ * @brief Issue SDRAM command
+ * @param[in] SDRAM_command Command mode, should be:
+ * - 0x00: Issue SDRAM NORMAL operation command
+ * - 0x01: Issue SDRAM MODE command
+ * - 0x02: Issue SDRAM PALL (precharge all) command
+ * - 0x03: Issue SRAM NOP (no operation) command
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
+{
+ uint32_t mask = ~(uint32_t)(_SBF(7,0x03));
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|SDRAM_command);
+}
+
+/*********************************************************************//**
+ * @brief Switch between Normal operation and deep sleep power mode
+ * @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
+ * - 0: Normal operation
+ * - 1: Enter deep-sleep mode
+ * @return None
+ **********************************************************************/
+void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(13));
+ LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|Power_command);
+}
+
+/*********************************************************************//**
+ * @brief Set the value of EMC dynamic memory registers
+ * @param[in] par EMC register that will set value, should be:
+ * - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
+ * - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
+ * - EMC_DYN_MEM_TRP: Dynamic RP register
+ * - EMC_DYN_MEM_TRAS: Dynamic RAS register
+ * - EMC_DYN_MEM_TSREX: Dynamic SREX register
+ * - EMC_DYN_MEM_TAPR: Dynamic APR register
+ * - EMC_DYN_MEM_TDAL: Dynamic DAL register
+ * - EMC_DYN_MEM_TWR: Dynamic WR register
+ * - EMC_DYN_MEM_TRC: Dynamic RC register
+ * - EMC_DYN_MEM_TRFC: Dynamic RFC register
+ * - EMC_DYN_MEM_TXSR: Dynamic XSR register
+ * - EMC_DYN_MEM_TRRD: Dynamic RRD register
+ * - EMC_DYN_MEM_TMRD: Dynamic MRD register
+ * @return None
+ **********************************************************************/
+void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
+{
+ switch ( par)
+ {
+ case EMC_DYN_MEM_REFRESH_TIMER:
+ LPC_EMC->DynamicRefresh = val;
+ break;
+ case EMC_DYN_MEM_READ_CONFIG:
+ LPC_EMC->DynamicReadConfig = val;
+ break;
+ case EMC_DYN_MEM_TRP:
+ LPC_EMC->DynamicRP = val;
+ break;
+ case EMC_DYN_MEM_TRAS:
+ LPC_EMC->DynamicRAS = val;
+ break;
+ case EMC_DYN_MEM_TSREX:
+ LPC_EMC->DynamicSREX = val;
+ break;
+ case EMC_DYN_MEM_TAPR:
+ LPC_EMC->DynamicAPR = val;
+ break;
+ case EMC_DYN_MEM_TDAL:
+ LPC_EMC->DynamicDAL = val;
+ break;
+ case EMC_DYN_MEM_TWR:
+ LPC_EMC->DynamicWR = val;
+ break;
+ case EMC_DYN_MEM_TRC:
+ LPC_EMC->DynamicRC = val;
+ break;
+ case EMC_DYN_MEM_TRFC:
+ LPC_EMC->DynamicRFC = val;
+ break;
+ case EMC_DYN_MEM_TXSR:
+ LPC_EMC->DynamicXSR = val;
+ break;
+ case EMC_DYN_MEM_TRRD:
+ LPC_EMC->DynamicRRD = val;
+ break;
+ case EMC_DYN_MEM_TMRD:
+ LPC_EMC->DynamicMRD = val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set extended wait time out for accessing static memory
+ * @param[in] Extended_wait_time_out timeout value that will be set
+ * @return None
+ **********************************************************************/
+void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
+{
+ LPC_EMC->StaticExtendedWait = Extended_wait_time_out;
+}
+
+/*********************************************************************//**
+ * @brief Configure the memory device
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] mem_dev Memory device, should be:
+ * - 0x00: SDRAM
+ * - 0x01: Low-power SDRAM
+ * - 0x02: Micron Syncflash
+ * @return None
+ **********************************************************************/
+void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
+{
+ uint32_t mask = ~(uint32_t)(_SBF(3, 0x03));
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
+ break;
+ case 1:
+ LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
+ break;
+ case 2:
+ LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
+ break;
+ case 3:
+ LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Map the address for the memory device
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] add_mapped address where the memory will be mapped
+ * @return None
+ **********************************************************************/
+void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
+{
+ uint32_t mask = ~(uint32_t)(_SBF(7, 0x3f)) | ~(uint32_t)(_BIT(14)) ;
+
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped;
+ break;
+ case 1:
+ LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped;
+ break;
+ case 2:
+ LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped;
+ break;
+ case 3:
+ LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable/disable the buffer
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] buff_control buffer control mode, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return None
+ **********************************************************************/
+void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(19)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control;
+ break;
+ case 1:
+ LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control;
+ break;
+ case 2:
+ LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control;
+ break;
+ case 3:
+ LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control;
+ break;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configure write permission: protect or not
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] permission permission mode, should be:
+ * - ENABLE: protect
+ * - DISABLE: not protect
+ * @return None
+ **********************************************************************/
+void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(20)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission;
+ break;
+ case 1:
+ LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission;
+ break;
+ case 2:
+ LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission;
+ break;
+ case 3:
+ LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set value for RAS latency
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] ras_val RAS value should be in range: 0..3
+ * @return None
+ **********************************************************************/
+void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
+{
+ uint32_t mask = ~(uint32_t)(0x03) ;
+
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val;
+ break;
+ case 1:
+ LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val;
+ break;
+ case 2:
+ LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val;
+ break;
+ case 3:
+ LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set value for CAS latency
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] ras_val CAS value should be in range: 0..3
+ * @return None
+ **********************************************************************/
+void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
+{
+ uint32_t mask = ~(uint32_t)(_SBF(8, 0x03)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
+ break;
+ case 1:
+ LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
+ break;
+ case 2:
+ LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
+ break;
+ case 3:
+ LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
+ break;
+ }
+}
+/*********************************************************************//**
+ * @brief Configure the memory width
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] mem_width memory width, should be:
+ * - 0x00: 8-bits
+ * - 0x01: 16-bits
+ * - 0x02: 32-bits
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
+{
+ uint32_t mask = ~(uint32_t)(0x03) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width;
+ break;
+ }
+}
+/*********************************************************************//**
+ * @brief Configure the page mode
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] page_mode page mode, should be:
+ * - 0: disable
+ * - 1: asynchronous page mode enable
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(3)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| page_mode;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| page_mode;
+ break;
+ }
+}
+/*********************************************************************//**
+ * @brief Configure the chip select polarity
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] pagepol_val_mode page mode, should be:
+ * - 0: Active LOW ship select
+ * - 1: Active HIGH chip select
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(6)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pol_val;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Configure the byte lane state
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] pb_val Byte lane state, should be:
+ * - 0: For reads all bits in BLSn[3:0] are HIGH.
+ * - 1: For reads all bits in BLSn[3:0] are LOW.
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(7)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)| pb_val;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pb_val;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2 & mask)| pb_val;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| pb_val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Configure the extended wait value
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] ex_wait Extended wait mode, should be:
+ * - 0: Extended wait disabled.
+ * - 1: Extended wait enabled.
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(8)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Configure the buffer enable value
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] buf_val Buffer mode, should be:
+ * - 0: Buffer disabled.
+ * - 1: Buffer enabled.
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(19)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Configure the write permission
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] per_val Permission mode, should be:
+ * - 0: Write not protected.
+ * - 1: Write protected.
+ * @return None
+ **********************************************************************/
+void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
+{
+ uint32_t mask = ~(uint32_t)(_BIT(20)) ;
+ switch ( index)
+ {
+ case 0:
+ LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | per_val;
+ break;
+ case 1:
+ LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | per_val;
+ break;
+ case 2:
+ LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | per_val;
+ break;
+ case 3:
+ LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | per_val;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set the value of LPC_EMC static memory registers
+ * @param[in] index index number, should be from 0 to 3
+ * @param[in] EMC_STA_MEM_PAR Static register, should be:
+ * - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
+ * - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
+ * - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
+ * - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
+ * - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
+ * - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
+ * @return None
+ **********************************************************************/
+void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val)
+{
+ switch (index)
+ {
+ case 0:
+ switch ( par)
+ {
+ case EMC_STA_MEM_WAITWEN:
+ LPC_EMC->StaticWaitWen0 = val;
+ break;
+ case EMC_STA_MEM_WAITOEN:
+ LPC_EMC->StaticWaitOen0 = val;
+ break;
+ case EMC_STA_MEM_WAITRD:
+ LPC_EMC->StaticWaitRd0 = val;
+ break;
+ case EMC_STA_MEM_WAITPAGE:
+ LPC_EMC->StaticWaitPage0 = val;
+ break;
+ case EMC_STA_MEM_WAITWR:
+ LPC_EMC->StaticWaitWr0 = val;
+ break;
+ case EMC_STA_MEM_WAITTURN:
+ LPC_EMC->StaticWaitTurn0 = val;
+ break;
+ }
+ break;
+ case 1:
+ switch ( par)
+ {
+ case EMC_STA_MEM_WAITWEN:
+ LPC_EMC->StaticWaitWen1 = val;
+ break;
+ case EMC_STA_MEM_WAITOEN:
+ LPC_EMC->StaticWaitOen1 = val;
+ break;
+ case EMC_STA_MEM_WAITRD:
+ LPC_EMC->StaticWaitRd1 = val;
+ break;
+ case EMC_STA_MEM_WAITPAGE:
+ LPC_EMC->StaticWaitPage1 = val;
+ break;
+ case EMC_STA_MEM_WAITWR:
+ LPC_EMC->StaticWaitWr1 = val;
+ break;
+ case EMC_STA_MEM_WAITTURN:
+ LPC_EMC->StaticWaitTurn1 = val;
+ break;
+ }
+ break;
+ case 2:
+ switch ( par)
+ {
+ case EMC_STA_MEM_WAITWEN:
+ LPC_EMC->StaticWaitWen2 = val;
+ break;
+ case EMC_STA_MEM_WAITOEN:
+ LPC_EMC->StaticWaitOen2 = val;
+ break;
+ case EMC_STA_MEM_WAITRD:
+ LPC_EMC->StaticWaitRd2 = val;
+ break;
+ case EMC_STA_MEM_WAITPAGE:
+ LPC_EMC->StaticWaitPage2 = val;
+ break;
+ case EMC_STA_MEM_WAITWR:
+ LPC_EMC->StaticWaitWr2 = val;
+ break;
+ case EMC_STA_MEM_WAITTURN:
+ LPC_EMC->StaticWaitTurn2 = val;
+ break;
+ }
+ break;
+ case 3:
+ switch ( par)
+ {
+ case EMC_STA_MEM_WAITWEN:
+ LPC_EMC->StaticWaitWen3 = val;
+ break;
+ case EMC_STA_MEM_WAITOEN:
+ LPC_EMC->StaticWaitOen3 = val;
+ break;
+ case EMC_STA_MEM_WAITRD:
+ LPC_EMC->StaticWaitRd3 = val;
+ break;
+ case EMC_STA_MEM_WAITPAGE:
+ LPC_EMC->StaticWaitPage3 = val;
+ break;
+ case EMC_STA_MEM_WAITWR:
+ LPC_EMC->StaticWaitWr3 = val;
+ break;
+ case EMC_STA_MEM_WAITTURN:
+ LPC_EMC->StaticWaitTurn3 = val;
+ break;
+ }
+ break;
+ }
+}
+
+
+
+
+
+
+
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.h b/bsp/lpc178x/drivers/lpc177x_8x_emc.h new file mode 100644 index 0000000000..d146914cf5 --- /dev/null +++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.h @@ -0,0 +1,361 @@ +/**********************************************************************
+* $Id$ lpc177x_8x_emc.h 2011-06-02
+*//**
+* @file lpc177x_8x_emc.h
+* @brief Contains all macro definitions and function prototypes
+* support for EMC firmware library on LPC177x_8x
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EMC EMC (External Memory Controller)
+ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC177X_8X_EMC_H_
+#define __LPC177X_8X_EMC_H_
+
+#include "lpc_types.h"
+#include "LPC177x_8x.h"
+
+
+/** @defgroup EMC_Private_Macros EMC Private Macros
+ * @{
+ */
+
+/***********************************************************************
+ * EMC Control Register (EMCControl)
+ **********************************************************************/
+/* Control register mask */
+#define EMC_Control_MASK ((uint32_t )0x07)
+/* Control register EMC: Enable control. */
+#define EMC_Control_E ((uint32_t )(1<<0))
+/* Control register EMC: Address mirror control. */
+#define EMC_Control_M ((uint32_t )(1<<1))
+/* Control register EMC: Low-power mode control. */
+#define EMC_Control_L ((uint32_t )(1<<2))
+
+/***********************************************************************
+ * EMC Status Register (EMCStatus)
+ **********************************************************************/
+/* Status register mask */
+#define EMC_Status_MASK ((uint32_t )0x07)
+/* Status register EMC: Busy. */
+#define EMC_Status_B ((uint32_t )(1<<0))
+/* Status register EMC: Write buffer status. */
+#define EMC_Status_S ((uint32_t )(1<<1))
+/* Status register EMC: Self-refresh acknowledge.. */
+#define EMC_Status_SA ((uint32_t )(1<<2))
+
+/***********************************************************************
+ * EMC Configuration register (EMCConfig)
+ **********************************************************************/
+/* EMC Configuration register : Enable control. */
+#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
+/* EMC Configuration register: CCLK. */
+#define EMC_Config_CCLK ((uinr32_t)(1<<8))
+/* EMC Configuration register mask */
+#define EMC_Config_MASK ((uint32_t)(0x101))
+
+
+/***********************************************************************
+ * Dynamic Memory Control register (EMCDynamicControl)
+ **********************************************************************/
+/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
+#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
+/* Dynamic Memory Control register EMC: Dynamic memory clock control */
+#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
+/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
+#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
+/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
+#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
+/* Dynamic Memory Control register EMC: SDRAM initialization*/
+#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
+/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
+#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
+
+/***********************************************************************
+ * Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
+ **********************************************************************/
+/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
+#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
+
+/***********************************************************************
+ * Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
+ **********************************************************************/
+/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
+#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
+
+/***********************************************************************
+ * Dynamic Memory Percentage Command Period register (EMCDynamictRP)
+ **********************************************************************/
+/* EMCDynamictRP register EMC: Precharge command period (tRP). */
+#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
+ **********************************************************************/
+/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
+#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
+ **********************************************************************/
+/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
+#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
+ **********************************************************************/
+/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
+#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Dynamic Memory Write Recovery Time register (EMCDynamictWR)
+ **********************************************************************/
+/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
+#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
+
+/***********************************************************************
+ * Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
+ **********************************************************************/
+/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
+#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
+
+/***********************************************************************
+ * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
+ **********************************************************************/
+/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
+#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
+ **********************************************************************/
+/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
+#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
+ **********************************************************************/
+/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
+#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
+ **********************************************************************/
+/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
+#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Static Memory Extended Wait Register (EMCStaticExtendedWait)
+ **********************************************************************/
+/* StaticExtendedWait register EMC: External wait time out. */
+#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
+
+
+/***********************************************************************
+ * Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
+ **********************************************************************/
+/* DynamicConfig register EMC: Memory device (MD). */
+#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
+/* DynamicConfig register EMC: Address mapping (AM) */
+#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
+/* DynamicConfig register EMC: Address mapping (AM) */
+#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
+/* DynamicConfig register EMC: Buffer enable */
+#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
+/* DynamicConfig register EMC: Write protect (P) */
+#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
+
+/***********************************************************************
+ * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
+ **********************************************************************/
+/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
+#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
+/* DynamicRASCAS register EMC: CAS latency (CAS)*/
+#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
+
+/***********************************************************************
+ * Static Memory Configuration registers (EMCStaticConfig0-3)
+ **********************************************************************/
+/* StaticConfig register EMC: Memory width (MW). */
+#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
+/* StaticConfig register EMC: Memory width 8bit . */
+#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
+/* StaticConfig register EMC: Memory width 16bit . */
+#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
+/* StaticConfig register EMC: Memory width 32bit . */
+#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
+/* StaticConfig register EMC: Page mode (PM) */
+#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
+/* StaticConfig register EMC: Chip select polarity (PC) */
+#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
+/* StaticConfig register EMC: Byte lane state (PB) */
+#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
+/* StaticConfig register EMC: Extended wait (EW) */
+#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
+/* StaticConfig register EMC: Buffer enable (B) */
+#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
+/* StaticConfig register EMC: Write protect (P) */
+#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
+
+/***********************************************************************
+ * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
+ **********************************************************************/
+/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
+#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
+ **********************************************************************/
+/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
+#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Static Memory Read Delay registers (EMCStaticWaitRd0-3)
+ **********************************************************************/
+/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
+read first access wait state (WAITRD) */
+#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
+ **********************************************************************/
+/* StaticwaitPage register EMC: Asynchronous page mode read after the first
+read wait states (WAITPAGE). */
+#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Static Memory Write Delay registers (EMCStaticWaitwr0-3)
+ **********************************************************************/
+/* StaticWaitwr register EMC: Write wait states (WAITWR). */
+#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
+
+/***********************************************************************
+ * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
+ **********************************************************************/
+/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
+#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
+
+/***********************************************************************
+ * Delay Control register (EMCDLYCTL)
+ **********************************************************************/
+#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
+#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
+#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
+#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
+
+/***********************************************************************
+ * EMC Calibration register (EMCCAL)
+ **********************************************************************/
+#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
+#define EMC_CAL_START ((uint32_t)(1<<14))
+#define EMC_CAL_DONE ((uint32_t)(1<<15))
+
+#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
+#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup EMC_Public_Types EMC Public Types
+ * @{
+ */
+/*EMC dynamic memory registers enum*/
+typedef enum
+{
+ EMC_DYN_MEM_REFRESH_TIMER,
+ EMC_DYN_MEM_READ_CONFIG,
+ EMC_DYN_MEM_TRP,
+ EMC_DYN_MEM_TRAS,
+ EMC_DYN_MEM_TSREX,
+ EMC_DYN_MEM_TAPR,
+ EMC_DYN_MEM_TDAL,
+ EMC_DYN_MEM_TWR,
+ EMC_DYN_MEM_TRC,
+ EMC_DYN_MEM_TRFC,
+ EMC_DYN_MEM_TXSR,
+ EMC_DYN_MEM_TRRD,
+ EMC_DYN_MEM_TMRD
+} EMC_DYN_MEM_PAR;
+
+/*EMC static memory registers enum*/
+typedef enum
+{
+ EMC_STA_MEM_WAITWEN,
+ EMC_STA_MEM_WAITOEN,
+ EMC_STA_MEM_WAITRD,
+ EMC_STA_MEM_WAITPAGE,
+ EMC_STA_MEM_WAITWR,
+ EMC_STA_MEM_WAITTURN,
+} EMC_STA_MEM_PAR;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EMC_Public_Functions EMC Public Functions
+ * @{
+ */
+
+extern void EMC_Init(void);
+extern void EMC_ConfigEndianMode(uint32_t endian_mode);
+extern void EMC_DynCtrlClockEnable(uint32_t clock_enable);
+extern void EMC_DynCtrlClockControl(int32_t clock_control);
+extern void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
+extern void EMC_DynCtrlMMC(uint32_t MMC_val);
+extern void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
+extern void EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
+extern void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
+extern void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
+extern void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
+extern void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped);
+extern void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
+extern void EMC_DynMemConfigP(uint32_t index , uint32_t permission);
+extern void EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
+extern void EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
+extern void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
+extern void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
+extern void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
+extern void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
+extern void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
+extern void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
+extern void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
+extern void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);
+
+/**
+ * @}
+ */
+
+
+#endif /* __LPC177X_8X_EMC_H_ */
+
+/**
+ * @}
+ */
+
+
+
diff --git a/bsp/lpc178x/drivers/lpc17xx_lcd.c b/bsp/lpc178x/drivers/lpc17xx_lcd.c new file mode 100644 index 0000000000..3eb9d14971 --- /dev/null +++ b/bsp/lpc178x/drivers/lpc17xx_lcd.c @@ -0,0 +1,13 @@ +#include <rtthread.h>
+
+#include "LPC177x_8x.h"
+#include "lpc177x_8x_pinsel.h"
+
+/* LCD BL P5_4 */
+void rt_hw_lcd_init(void)
+{
+ PINSEL_ConfigPin(5, 4, 0);
+ LPC_GPIO5->DIR |= 1<<4;
+ LPC_GPIO5->CLR = 1<<4;
+ LPC_GPIO5->SET = 1<<4;
+}
diff --git a/bsp/lpc178x/drivers/lpc17xx_lcd.h b/bsp/lpc178x/drivers/lpc17xx_lcd.h new file mode 100644 index 0000000000..ae7db3fe92 --- /dev/null +++ b/bsp/lpc178x/drivers/lpc17xx_lcd.h @@ -0,0 +1,6 @@ +#ifndef LPC17XX_LCD_H_INCLUDED
+#define LPC17XX_LCD_H_INCLUDED
+
+
+
+#endif // LPC17XX_LCD_H_INCLUDED
diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c index 3537978b43..608bbaec61 100644 --- a/bsp/lpc178x/drivers/uart.c +++ b/bsp/lpc178x/drivers/uart.c @@ -21,25 +21,6 @@ #include "lpc177x_8x_uart.h"
#include "lpc177x_8x_pinsel.h"
-#define IER_RBR 0x01
-#define IER_THRE 0x02
-#define IER_RLS 0x04
-
-#define IIR_PEND 0x01
-#define IIR_RLS 0x03
-#define IIR_RDA 0x02
-#define IIR_CTI 0x06
-#define IIR_THRE 0x01
-
-#define LSR_RDR 0x01
-#define LSR_OE 0x02
-#define LSR_PE 0x04
-#define LSR_FE 0x08
-#define LSR_BI 0x10
-#define LSR_THRE 0x20
-#define LSR_TEMT 0x40
-#define LSR_RXFE 0x80
-
/**
* @addtogroup LPC11xx
*/
@@ -65,6 +46,7 @@ struct rt_uart_lpc uart0_device; struct rt_uart_lpc uart1_device;
#endif
+#ifdef RT_USING_UART0
void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
@@ -76,10 +58,7 @@ void UART0_IRQHandler(void) /* read IIR and clear it */
iir = uart->UART->IIR;
- iir >>= 1; /* skip pending bit in IIR */
- iir &= 0x07; /* check bit 1~3, interrupt identification */
-
- if (iir == IIR_RDA) /* Receive Data Available */
+ if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
@@ -108,7 +87,9 @@ void UART0_IRQHandler(void) return;
}
+#endif
+#ifdef RT_USING_UART1
void UART1_IRQHandler(void)
{
rt_ubase_t level, iir;
@@ -120,9 +101,6 @@ void UART1_IRQHandler(void) /* read IIR and clear it */
iir = uart->UART->IIR;
-// iir >>= 1; /* skip pending bit in IIR */
-// iir &= 0x07; /* check bit 1~3, interrupt identification */
-
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
@@ -152,6 +130,7 @@ void UART1_IRQHandler(void) return;
}
+#endif
static rt_err_t rt_uart_init (rt_device_t dev)
{
@@ -167,7 +146,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) * P0.3: RXD
*/
PINSEL_ConfigPin(0, 2, 1);
- PINSEL_ConfigPin(0, 2, 1);
+ PINSEL_ConfigPin(0, 3, 1);
UART_ConfigStruct.Baud_rate = 115200;
UART_ConfigStruct.Databits = UART_DATABIT_8;
@@ -179,7 +158,8 @@ static rt_err_t rt_uart_init (rt_device_t dev) // Enable UART Transmit
UART_TxCmd( uart->UART, ENABLE);
- UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
+// UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
+ UART_IntConfig( uart->UART, UART_INTCFG_RBR, ENABLE);
}
#endif
@@ -204,7 +184,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) // Enable UART Transmit
UART_TxCmd( uart->UART, ENABLE);
- UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
+// UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
UART_IntConfig( uart->UART, UART_INTCFG_RBR, ENABLE);
}
#endif
diff --git a/bsp/lpc178x/project.uvproj b/bsp/lpc178x/project.uvproj index 4c986e40d8..9f08eaccb7 100644 --- a/bsp/lpc178x/project.uvproj +++ b/bsp/lpc178x/project.uvproj @@ -346,7 +346,7 @@ <MiscControls></MiscControls> <Define></Define> <Undefine></Undefine> - <IncludePath>CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x;drivers;.;..\..\libcpu\arm\lpc17xx;..\..\include;..\..\libcpu\arm\common;CMSIS\CM3\CoreSupport;..\..\components\finsh</IncludePath> + <IncludePath>drivers;.;CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;CMSIS\CM3\CoreSupport;..\..\components\finsh</IncludePath> </VariousControls> </Cads> <Aads> @@ -464,17 +464,17 @@ </Files> </Group> <Group> - <GroupName>LPC17XX</GroupName> + <GroupName>CORTEX-M3</GroupName> <Files> <File> <FileName>cpuport.c</FileName> <FileType>1</FileType> - <FilePath>..\..\libcpu\arm\lpc17xx\cpuport.c</FilePath> + <FilePath>..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> </File> <File> <FileName>context_rvds.S</FileName> <FileType>2</FileType> - <FilePath>..\..\libcpu\arm\lpc17xx\context_rvds.S</FilePath> + <FilePath>..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> </File> <File> <FileName>backtrace.c</FileName> @@ -597,6 +597,11 @@ <FilePath>drivers\lpc177x_8x_clkpwr.c</FilePath> </File> <File> + <FileName>lpc177x_8x_emc.c</FileName> + <FileType>1</FileType> + <FilePath>drivers\lpc177x_8x_emc.c</FilePath> + </File> + <File> <FileName>lpc177x_8x_pinsel.c</FileName> <FileType>1</FileType> <FilePath>drivers\lpc177x_8x_pinsel.c</FilePath> @@ -607,6 +612,11 @@ <FilePath>drivers\lpc177x_8x_uart.c</FilePath> </File> <File> + <FileName>lpc17xx_lcd.c</FileName> + <FileType>1</FileType> + <FilePath>drivers\lpc17xx_lcd.c</FilePath> + </File> + <File> <FileName>uart.c</FileName> <FileType>1</FileType> <FilePath>drivers\uart.c</FilePath> diff --git a/bsp/lpc178x/rtconfig.h b/bsp/lpc178x/rtconfig.h index 8d1eaf5be4..2302e56094 100644 --- a/bsp/lpc178x/rtconfig.h +++ b/bsp/lpc178x/rtconfig.h @@ -3,10 +3,10 @@ #define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE 4
+#define RT_ALIGN_SIZE 8
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32
@@ -56,6 +56,9 @@ /* Using Small MM */
#define RT_USING_SMALL_MEM
+/* Using SLAB Allocator */
+//#define RT_USING_SLAB
+
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
@@ -84,7 +87,7 @@ #define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-//#define RT_USING_LWIP
+/* #define RT_USING_LWIP */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
@@ -127,6 +130,11 @@ #define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+/* TCP sender buffer space */
+#define RT_LWIP_TCP_SND_BUF 8192
+/* TCP receive window. */
+#define RT_LWIP_TCP_WND 8192
+
/* SECTION: RT-Thread/GUI */
/* #define RT_USING_RTGUI */
diff --git a/bsp/lpc178x/rtconfig.py b/bsp/lpc178x/rtconfig.py index 678522f928..11c425ff93 100644 --- a/bsp/lpc178x/rtconfig.py +++ b/bsp/lpc178x/rtconfig.py @@ -1,6 +1,6 @@ # toolchains options
ARCH='arm'
-CPU='lpc17xx'
+CPU='cortex-m3'
CROSS_TOOL='keil'
if CROSS_TOOL == 'gcc':
|