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authorbernard.xiong <[email protected]>2010-04-28 23:06:37 +0000
committerbernard.xiong <[email protected]>2010-04-28 23:06:37 +0000
commitd39175daa9636f8a6cd937754c87f689c5120eb2 (patch)
tree8b780b1420d28df9aedad0e1c5727233c2f14ea7
parent7df7dafe7038c51fa84572ec8276e847e85137b5 (diff)
update CM0 context switch code.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@679 bbd45198-f89e-11dd-88c7-29a3b14d5316
-rw-r--r--libcpu/arm/lpc1100/context_rvds.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/libcpu/arm/lpc1100/context_rvds.S b/libcpu/arm/lpc1100/context_rvds.S
index 7d9080643e..9eb913f27a 100644
--- a/libcpu/arm/lpc1100/context_rvds.S
+++ b/libcpu/arm/lpc1100/context_rvds.S
@@ -107,9 +107,10 @@ rt_hw_pend_sv PROC
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
- STMIA r1!, {r4 - r7} ; push r4 - r7 register
+ SUBS r1, r1, #0x10
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
+ STMIA r1!, {r4 - r7} ; push r4 - r7 register
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
@@ -123,9 +124,8 @@ pendsv_exit
; restore interrupt
MSR PRIMASK, r2
- MOV r0, lr
- MOVS r1, #0x04
- ORRS r0, r0, r1
+ MOVS r0, #0x04
+ RSBS r0, #0
BX r0
ENDP