diff options
| author | xiao xie <[email protected]> | 2023-02-07 11:17:31 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-02-06 22:17:31 -0500 |
| commit | e94a3bf52ca1b4cbbec74c4af2e83a6633b8bffc (patch) | |
| tree | 9fdc14d2333628617447f9d28d6c2fb7aa9084f4 | |
| parent | 53dcac6f68fd330e2fd86ffc6d136d15a85e3e6a (diff) | |
[imxrt1060] Update 1060 sdk 2.12.1 (#6892)
更新的SDK2.12.1更新imxrt1060的驱动
139 files changed, 34157 insertions, 11170 deletions
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/.config b/bsp/imxrt/imxrt1060-nxp-evk/.config index 5f2d48dad2..cd968455f3 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/.config +++ b/bsp/imxrt/imxrt1060-nxp-evk/.config @@ -73,6 +73,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50000 + CONFIG_RT_USING_CACHE=y # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -105,7 +106,39 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 -# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_FAL is not set # CONFIG_RT_USING_LWP is not set @@ -127,7 +160,7 @@ CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PHY=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -157,9 +190,13 @@ CONFIG_RT_USING_PIN=y # # Using USB # -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set +CONFIG_RT_USING_USB=y +CONFIG_RT_USING_USB_HOST=y +CONFIG_RT_USBH_MSTORAGE=y +CONFIG_UDISK_MOUNTPOINT="/" +# CONFIG_RT_USBH_HID is not set # CONFIG_RT_USING_USB_DEVICE is not set +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 # # C/C++ and POSIX layer @@ -192,7 +229,15 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Network # # CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set @@ -297,6 +342,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -1013,19 +1059,23 @@ CONFIG_SOC_MIMXRT1062DVL6A=y # # Onboard Peripheral Drivers # -# CONFIG_BSP_USING_SDRAM is not set +CONFIG_BSP_USING_SDRAM=y +# CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_LCD is not set # CONFIG_BSP_USING_TOUCHPAD is not set # CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_FS is not set # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C1=y -CONFIG_HW_I2C1_BADURATE_100kHZ=y -# CONFIG_HW_I2C1_BADURATE_400kHZ is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_USB=y +CONFIG_BSP_USB0_HOST=y +# CONFIG_BSP_USB1_HOST is not set +# CONFIG_BSP_USING_I2C is not set CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_USING_LPUART2 is not set @@ -1035,7 +1085,7 @@ CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_USING_LPUART6 is not set # CONFIG_BSP_USING_LPUART7 is not set # CONFIG_BSP_USING_LPUART8 is not set -CONFIG_BSP_USING_PXP=y +# CONFIG_BSP_USING_PXP is not set CONFIG_BSP_USING_CACHE=y # diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c index cab9cb7431..c8a1cd7636 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/main.c @@ -14,7 +14,7 @@ #include "core_cm7.h" /* defined the LED pin: GPIO1_IO9 */ -#define LED0_PIN GET_PIN(1, 8) +#define LED0_PIN GET_PIN(1, 9) int main(void) { diff --git a/bsp/imxrt/imxrt1060-nxp-evk/applications/mnt.c b/bsp/imxrt/imxrt1060-nxp-evk/applications/mnt.c new file mode 100644 index 0000000000..44c9a5d588 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/applications/mnt.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-09-19 Gavin first version + * + */ + +#include <rtthread.h> +#ifdef RT_USING_DFS_RAMFS +#include <dfs_fs.h> + +extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + +int mnt_init(void) +{ + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8*1024*1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + return 0; + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + rt_kprintf("RAM file system initializated!\n"); + else + rt_kprintf("RAM file system initializate failed!\n"); + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + +#ifdef BSP_USING_SDCARD_FATFS +#include <dfs_fs.h> +#include <dfs_file.h> +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> +static int filesystem_mount(void) +{ + while(rt_device_find("sd0") == RT_NULL) + { + rt_thread_mdelay(1); + } + + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + rt_kprintf("ret: %d\n",ret); + LOG_E("sd0 mount to '/' failed!"); + return ret; + } + + return RT_EOK; +} +INIT_ENV_EXPORT(filesystem_mount); +#endif diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig index 2547a5b3cb..f644a8fb2a 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig @@ -23,6 +23,44 @@ menu "Onboard Peripheral Drivers" bool "Enable SDRAM" default n + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1060EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 9 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + endif + menuconfig BSP_USING_LCD bool "Enable LCD" default n @@ -108,6 +146,20 @@ menu "Onboard Peripheral Drivers" select PKG_USING_GUI_GUIDER_DEMO default n endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif endmenu menu "On-chip Peripheral Drivers" @@ -117,6 +169,40 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + if BSP_USING_SDIO + config CODE_STORED_ON_SDCARD + bool "Enable Code STORED On SDCARD" + default n + help + "SD CARD work as boot devive" + endif + + config BSP_USING_USB + bool "Enable USB" + select RT_USING_USB_HOST + default n + + if BSP_USING_USB + config BSP_USB0_HOST + bool "Enable USB0" + default n + + config BSP_USB1_HOST + bool "Enable USB1" + default n + endif + menuconfig BSP_USING_I2C bool "Enable I2C" select RT_USING_I2C diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex index 191861773b..4dbb7ee462 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex @@ -1,5 +1,5 @@ <?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="1.8" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> +<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_12 http://mcuxpresso.nxp.com/XSD/mex_configuration_12.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="12" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_12" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <common> <processor>MIMXRT1062xxxxA</processor> <package>MIMXRT1062DVL6A</package> @@ -14,11 +14,16 @@ <validate_boot_init_only>true</validate_boot_init_only> <generate_extended_information>false</generate_extended_information> <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> </preferences> <tools> - <pins name="Pins" version="8.0" enabled="true" update_project_code="true"> + <pins name="Pins" version="12.0" enabled="true" update_project_code="true"> <pins_profile> - <processor_version>0.8.11</processor_version> + <processor_version>12.0.1</processor_version> + <pin_labels> + <pin_label pin_num="F13" pin_signal="GPIO_AD_B0_08" label="GPIO1_08" identifier="gpio1_08"/> + </pin_labels> <power_domains/> </pins_profile> <functions_list> @@ -35,17 +40,17 @@ <data>true</data> </feature> </dependency> - <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> <data>true</data> </feature> </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> <feature name="enabled" evaluation="equal" configuration="core0"> <data>true</data> </feature> </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> <feature name="enabled" evaluation="equal" configuration="core0"> <data>true</data> </feature> @@ -78,21 +83,23 @@ <pin_feature name="slew_rate" value="Slow"/> </pin_features> </pin> - <pin peripheral="ARM" signal="arm_trace_swo" pin_num="G13" pin_signal="GPIO_AD_B0_10"> + <pin peripheral="GPIO1" signal="gpio_io, 08" pin_num="F13" pin_signal="GPIO_AD_B0_08"> <pin_features> - <pin_feature name="slew_rate" value="Fast"/> + <pin_feature name="direction" value="OUTPUT"/> </pin_features> </pin> + <pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09"/> + <pin peripheral="GPIO1" signal="gpio_io, 10" pin_num="G13" pin_signal="GPIO_AD_B0_10"/> </pins> </function> </functions_list> </pins> - <clocks name="Clocks" version="7.0" enabled="true" update_project_code="true"> + <clocks name="Clocks" version="10.0" enabled="true" update_project_code="true"> <clocks_profile> - <processor_version>0.8.11</processor_version> + <processor_version>12.0.1</processor_version> </clocks_profile> <clock_configurations> - <clock_configuration name="BOARD_BootClockRUN"> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> <description></description> <options/> <dependencies> @@ -157,9 +164,7 @@ <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> - <clock_output id="ENET1_TX_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> - <clock_output id="ENET2_TX_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> @@ -240,7 +245,7 @@ </clocks> <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true"> <dcdx_profile> - <processor_version>0.8.11</processor_version> + <processor_version>12.0.1</processor_version> <output_format>c_array</output_format> </dcdx_profile> <dcdx_configurations> @@ -392,8 +397,6 @@ <tee_profile> <processor_version>N/A</processor_version> </tee_profile> - <global_options/> - <user_memory_regions/> </tee> </tools> </configuration>
\ No newline at end of file diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c index 1ab35dfe2b..2972305a58 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c @@ -1,4 +1,11 @@ /* + * Copyright 2018-2020 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* * How to setup clock using clock driver functions: * * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. @@ -15,11 +22,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v7.0 +product: Clocks v8.0 processor: MIMXRT1062xxxxA package_id: MIMXRT1062DVL6A mcu_data: ksdk2_0 -processor_version: 8.0.3 +processor_version: 10.0.0 board: MIMXRT1060-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -58,9 +65,7 @@ outputs: - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} @@ -100,6 +105,8 @@ settings: - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} @@ -128,8 +135,8 @@ settings: - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} @@ -491,14 +498,10 @@ void BOARD_BootClockRUN(void) IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h index b67e7691d6..bbaae5db72 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h @@ -1,3 +1,10 @@ +/* + * Copyright 2018-2020 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + #ifndef _CLOCK_CONFIG_H_ #define _CLOCK_CONFIG_H_ @@ -44,11 +51,13 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL #define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c index 26e98307c6..61ff49968e 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c @@ -32,281 +32,281 @@ processor: MIMXRT1062xxxxA package_id: MIMXRT1062DVL6A mcu_data: ksdk2_0 processor_version: 0.0.0 -board: MIMXRT1060-EVKB +board: MIMXRT1060-EVK output_format: c_array * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ const uint8_t dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x04, 0x10, - /* Version */ - 0x41, + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, - /* COMMANDS */ + /* COMMANDS */ - /* group: 'Imported Commands' */ - /* #1.1-113, command header bytes for merged 'Write - value' command */ - 0xCC, 0x03, 0x8C, 0x04, - /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ - 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, - /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ - 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, - /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ - 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ - 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, - /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, - /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, - /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, - /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, - /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, - /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, - /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, - /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, - /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, - /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, - /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, - /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, - /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, - /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, - /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, - /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, - /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, - /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, - /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, - /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ - 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, - /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, - /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ - 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, - /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, - /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, - /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ - 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, - /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ - 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, - /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, - /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ - 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, - /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, - /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, - /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ - 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, - /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #3.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #5.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #7.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ - 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, - /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 - }; + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ #else diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h index 872000097d..185b0ecd89 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1060-nxp-evk/board/SConscript index 4003338493..8c84a67d74 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/SConscript +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/SConscript @@ -17,7 +17,12 @@ if GetDepend(['BSP_USING_TOUCHPAD']): CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'DATA_SECTION_IS_CACHEABLE=1'] +# CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', +# 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=1'] + + +CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', + 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=0', 'XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1'] if rtconfig.PLATFORM in ['armcc', 'armclang']: CPPDEFINES.append('__FPU_PRESENT=1') diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/board.c b/bsp/imxrt/imxrt1060-nxp-evk/board/board.c index 2b0e6ee7a5..6c203ba5d9 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/board.c @@ -31,6 +31,7 @@ #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority 0 bits for subpriority */ +/* MPU configuration. */ void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -48,10 +49,10 @@ void BOARD_ConfigMPU(void) uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; #elif defined(__ICCARM__) || defined(__GNUC__) - extern uint32_t __noncachedata_start__[]; - extern uint32_t __noncachedata_end__[]; - uint32_t nonCacheStart = (uint32_t)__noncachedata_start__; - uint32_t size = (uint32_t)((uint32_t)__noncachedata_end__ - (uint32_t)__noncachedata_start__); + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; #endif volatile uint32_t i = 0; @@ -79,7 +80,7 @@ void BOARD_ConfigMPU(void) * Use MACROS defined in mpu_armv7.h: * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache * 0 x 0 0 Strongly Ordered shareable * 0 x 0 1 Device shareable * 0 0 1 0 Normal not shareable Outer and inner write @@ -772,47 +773,51 @@ static void imxrt_lcd_pins_init(void) #ifdef BSP_USING_ETH void imxrt_enet_pins_init(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */ + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */ + ); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -820,9 +825,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: medium(100MHz) Open Drain Enable Field: Open Drain Disabled @@ -830,9 +835,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -840,9 +845,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -850,9 +855,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -860,9 +865,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -870,9 +875,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -880,9 +885,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -890,9 +895,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/6 Speed Field: low(50MHz) Open Drain Enable Field: Open Drain Disabled @@ -900,9 +905,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Keeper Pull Up / Down Config. Field: 100K Ohm Pull Down Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -910,9 +915,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: max(200MHz) Open Drain Enable Field: Open Drain Disabled @@ -920,9 +925,9 @@ void imxrt_enet_pins_init(void) Pull / Keep Select Field: Pull Pull Up / Down Config. Field: 100K Ohm Pull Up Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ - 0xB829u); /* Slew Rate Field: Fast Slew Rate + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: R0/5 Speed Field: low(50MHz) Open Drain Enable Field: Open Drain Enabled @@ -968,6 +973,140 @@ void imxrt_phy_pins_init( void ) } #endif /* BSP_USING_PHY */ +#ifdef BSP_USING_SDIO +void imrt_sdio_pins_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, /* GPIO_AD_B0_05 is configured as GPIO1_IO05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_12_GPIO2_IO28, /* GPIO_B1_12 is configured as GPIO2_IO28 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_14_USDHC1_VSELECT, /* GPIO_B1_14 is configured as USDHC1_VSELECT */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, /* GPIO_SD_B0_00 is configured as USDHC1_CMD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, /* GPIO_SD_B0_01 is configured as USDHC1_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, /* GPIO_SD_B0_02 is configured as USDHC1_DATA0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, /* GPIO_SD_B0_03 is configured as USDHC1_DATA1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, /* GPIO_SD_B0_04 is configured as USDHC1_DATA2 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, /* GPIO_SD_B0_05 is configured as USDHC1_DATA3 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */ + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */ + ); + IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 & + (~(IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */ + | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) /* GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: 0x00U */ + ); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, /* GPIO_AD_B0_05 PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_12_GPIO2_IO28, /* GPIO_B1_12 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_14_USDHC1_VSELECT, /* GPIO_B1_14 PAD functional properties : */ + 0x0170A1U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/4 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, /* GPIO_SD_B0_00 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, /* GPIO_SD_B0_01 PAD functional properties : */ + 0x014089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, /* GPIO_SD_B0_02 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, /* GPIO_SD_B0_03 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, /* GPIO_SD_B0_04 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, /* GPIO_SD_B0_05 PAD functional properties : */ + 0x017089U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0(150 Ohm @ 3.3V, 260 [email protected]) + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 47K Ohm Pull Up + Hyst. Enable Field: Hysteresis Enabled */ +} +#endif + /* * When PXP fetch images from FlexSPI flash, the default FlexSPI RX buffer * configuration does not meet the PXP bandwidth requirement. Reconfigure @@ -1060,6 +1199,10 @@ void rt_hw_board_init() imxrt_lcd_pins_init(); #endif +#ifdef BSP_USING_SDIO + imrt_sdio_pins_init(); +#endif + #ifdef BSP_USING_DMA imxrt_dma_init(); #endif diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/board.h b/bsp/imxrt/imxrt1060-nxp-evk/board/board.h index 72f7be0149..35fd056322 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/board.h @@ -41,7 +41,7 @@ extern int heap_end; /*! @brief The board flash size */ -#define BOARD_FLASH_SIZE (0x400000U) +#define BOARD_FLASH_SIZE (0x800000U) void rt_hw_board_init(void); diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf index 5555cd099a..f4e0a0a603 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf @@ -1,20 +1,22 @@ /*
** ###################################################################
-** Processors: MIMXRT1052CVJ5B
-** MIMXRT1052CVL5B
-** MIMXRT1052DVJ6B
-** MIMXRT1052DVL6B
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1050RM Rev.1, 03/2018
-** Version: rev. 1.0, 2018-09-21
-** Build: b180921
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -25,45 +27,57 @@ ** ###################################################################
*/
-define symbol m_interrupts_start = 0x70002000;
-define symbol m_interrupts_end = 0x700023FF;
+define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
+define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
-define symbol m_text_start = 0x70002400;
-define symbol m_text_end = 0x73FFFFFF;
+define symbol m_interrupts_start = 0x60002000;
+define symbol m_interrupts_end = 0x600023FF;
-define symbol m_data_start = 0x20000000;
+define symbol m_text_start = 0x60002400;
+define symbol m_text_end = 0x607FFFFF;
+
+define symbol m_interrupts_ram_start = 0x20000000;
+define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
-define symbol m_data2_end = 0x2023FFFF;
+define symbol m_data2_end = 0x202BFFFF;
-define exported symbol m_boot_hdr_conf_start = 0x70000000;
-define symbol m_boot_hdr_ivt_start = 0x70001000;
-define symbol m_boot_hdr_boot_data_start = 0x70001020;
-define symbol m_boot_hdr_dcd_data_start = 0x70001030;
+define symbol m_qacode_start = 0x00000000;
+define symbol m_qacode_end = 0x0001FFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start = 0x60001000;
+define symbol m_boot_hdr_boot_data_start = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start = 0x60001030;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
- define symbol __size_cstack__ = 0x0400;
+ define symbol __size_cstack__ = 0x2000;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
- define symbol __size_heap__ = 0x0400;
+ define symbol __size_heap__ = 0x2000;
}
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __NCACHE_REGION_START = m_data2_start;
+define exported symbol __NCACHE_REGION_SIZE = 0x0;
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define exported symbol __RTT_HEAP_END = m_data2_end;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
-
+define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
@@ -73,16 +87,17 @@ define block HEAP with alignment = 8, size = __size_heap__ { }; define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE { section CodeQuickAccess };
+define block QACCESS_DATA { section DataQuickAccess };
-initialize by copy { readwrite, section .textrw };
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess};
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
-
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+place at address mem: m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem: m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem: m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem: m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
@@ -92,4 +107,5 @@ place in DATA_region { block ZI }; place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
-
+place in QACODE_region { block QACCESS_CODE };
+place in DATA_region { block QACCESS_DATA };
\ No newline at end of file diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds index ab64f3ef37..f56a63fed0 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds @@ -1,42 +1,25 @@ /* ** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2022 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: [email protected] @@ -47,60 +30,57 @@ /* Entry Point */ ENTRY(Reset_Handler) -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x2000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; +VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; /* Specify the memory areas */ MEMORY { - m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 - m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x003FDC00 - - m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 - - m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 - m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00 + m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 } /* Define output sections */ SECTIONS { - .boot_data : + __NCACHE_REGION_START = ORIGIN(m_data2); + __NCACHE_REGION_SIZE = 0; + + .flash_config : { . = ALIGN(4); __FLASH_BASE = .; KEEP(* (.boot_hdr.conf)) /* flash config section */ . = ALIGN(4); - } > m_boot_data + } > m_flash_config - ivt_begin = ORIGIN(m_boot_data) + LENGTH(m_boot_data); + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); - .image_vertor_table : AT(ivt_begin) + .ivt : AT(ivt_begin) { . = ALIGN(4); - KEEP(*(.boot_hdr.ivt)) - KEEP(*(.boot_hdr.boot_data)) - KEEP(*(.boot_hdr.dcd_data)) + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(4); - } > m_image_vertor_table + } > m_ivt /* The startup code goes first into internal RAM */ .interrupts : { __VECTOR_TABLE = .; + __Vectors = .; . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } > m_interrupts - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - /* The program code and other data goes into internal RAM */ .text : { @@ -211,6 +191,20 @@ SECTIONS __etext = .; /* define a global symbol at end of code */ __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + .data : AT(__DATA_ROM) { . = ALIGN(4); @@ -219,26 +213,38 @@ SECTIONS *(m_usb_dma_init_data) *(.data) /* .data sections */ *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ KEEP(*(.jcr*)) - *(NonCacheable.init) - *(NonCacheable) . = ALIGN(4); __data_end__ = .; /* define a global symbol at data end */ - } > m_sdram + } > m_data + + __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); .ncache.init : AT(__NDATA_ROM) { __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) . = ALIGN(4); __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ocram + } > m_data . = __noncachedata_init_end__; .ncache : { + *(NonCacheable) . = ALIGN(4); __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_ocram + } > m_data __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); text_end = ORIGIN(m_text) + LENGTH(m_text); @@ -258,26 +264,25 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; __END_BSS = .; - } > m_sdram + } > m_data - .stack : + .stack : { . = ALIGN(8); stack_start = .; . += STACK_SIZE; stack_end = .; __StackTop = .; - } > m_sdram + } > m_data .RTT_HEAP : { heap_start = .; . = ALIGN(8); - } > m_sdram + } > m_data - PROVIDE(heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram)); + PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2)); .ARM.attributes 0 : { *(.ARM.attributes) } } - diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct index 395f64fef0..a45fda42af 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct @@ -60,13 +60,13 @@ #if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
- #define Stack_Size 0x0400
+ #define Stack_Size 0x2000
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
- #define Heap_Size 0x0400
+ #define Heap_Size 0x2000
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.icf b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.icf new file mode 100644 index 0000000000..3fe44d1868 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.icf @@ -0,0 +1,91 @@ +/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2022 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0001FFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2001FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x202BFFFF;
+
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x2000;
+}
+
+define exported symbol __NCACHE_REGION_START = m_data2_start;
+define exported symbol __NCACHE_REGION_SIZE = 0x0;
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE { section CodeQuickAccess };
+define block QACCESS_DATA { section DataQuickAccess };
+
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in DATA_region { block NCACHE_VAR };
+place in TEXT_region { block QACCESS_CODE };
+place in DATA_region { block QACCESS_DATA };
+place in CSTACK_region { block CSTACK };
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram_txt.icf b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram_txt.icf new file mode 100644 index 0000000000..f330c14ac1 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram_txt.icf @@ -0,0 +1,106 @@ +/*
+** ###################################################################
+** Processors: MIMXRT1062CVJ5A
+** MIMXRT1062CVL5A
+** MIMXRT1062DVJ6A
+** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2022 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x80000000;
+define symbol m_interrupts_end = 0x800003FF;
+
+define symbol m_text_start = 0x80000400;
+define symbol m_text_end = 0x801FFFFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x2001FFFF;
+
+define symbol m_data2_start = 0x20200000;
+define symbol m_data2_end = 0x202BFFFF;
+
+define symbol m_data3_start = 0x80200000;
+define symbol m_data3_end = 0x81DFFFFF;
+
+define symbol m_ncache_start = 0x81E00000;
+define symbol m_ncache_end = 0x81FFFFFF;
+
+define symbol m_qacode_start = 0x00000000;
+define symbol m_qacode_end = 0x0001FFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __NCACHE_REGION_START = m_ncache_start;
+define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end-__size_cstack__;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
+define region DATA_region = mem:[from m_data_start to m_data_end];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
+define region DATA3_region = mem:[from m_data3_start to m_data3_end];
+define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { first readwrite, section m_usb_dma_init_data };
+define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE { section CodeQuickAccess };
+define block QACCESS_DATA { section DataQuickAccess };
+
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+
+place in TEXT_region { readonly };
+place in DATA2_region { block RW };
+place in DATA2_region { block ZI };
+if (isdefinedsymbol(__heap_noncacheable__)) {
+ place in NCACHE_region { last block HEAP };
+} else {
+ place in DATA2_region { last block HEAP };
+}
+place in NCACHE_region { block NCACHE_VAR };
+place in QACODE_region { block QACCESS_CODE };
+place in DATA_region { block QACCESS_DATA };
+place in CSTACK_region { block CSTACK };
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/evkmimxrt1060_sdram_init.mac b/bsp/imxrt/imxrt1060-nxp-evk/evkmimxrt1060_sdram_init.mac new file mode 100644 index 0000000000..4888bca4d6 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/evkmimxrt1060_sdram_init.mac @@ -0,0 +1,258 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +_load_dcdc_trim() +{ + __var dcdc_trim_loaded; + __var ocotp_base; + __var ocotp_fuse_bank0_base; + __var dcdc_base; + __var reg; + __var trim_value; + __var index; + + ocotp_base = 0x401F4000; + ocotp_fuse_bank0_base = 0x401F4000 + 0x400; + dcdc_base = 0x40080000; + + dcdc_trim_loaded = 0; + + reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory"); + if (reg & (1<<10)) + { + // DCDC: REG0->VBG_TRM + trim_value = (reg & (0x1F << 11)) >> 11; + reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24); + __writeMemory32(reg, dcdc_base + 0x4, "Memory"); + dcdc_trim_loaded = 1; + } + + reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory"); + if (reg & (1<<30)) + { + index = (reg & (3 << 28)) >> 28; + if (index < 4) + { + // DCDC: REG3->TRG + reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index); + __writeMemory32(reg, dcdc_base + 0xC, "Memory"); + dcdc_trim_loaded = 1; + } + } + + if (dcdc_trim_loaded) + { + // delay 1ms for dcdc to get stable + __delay(1); + __message "DCDC trim value loaded.\n"; + } + +} + +SDRAM_WaitIpCmdDone() +{ + __var reg; + do + { + reg = __readMemory32(0x402F003C, "Memory"); + }while((reg & 0x3) == 0); + + __writeMemory32(0x00000003, 0x402F003C, "Memory"); // clear IPCMDERR and IPCMDDONE bits +} + +_clock_init() +{ + __var reg; + // Enable all clocks + __writeMemory32(0xffffffff, 0x400FC068, "Memory"); + __writeMemory32(0xffffffff, 0x400FC06C, "Memory"); + __writeMemory32(0xffffffff, 0x400FC070, "Memory"); + __writeMemory32(0xffffffff, 0x400FC074, "Memory"); + __writeMemory32(0xffffffff, 0x400FC078, "Memory"); + __writeMemory32(0xffffffff, 0x400FC07C, "Memory"); + __writeMemory32(0xffffffff, 0x400FC080, "Memory"); + + // PERCLK_PODF: 1 divide by 2 + __writeMemory32(0x04900001, 0x400FC01C, "Memory"); + // Enable SYS PLL but keep it bypassed. + __writeMemory32(0x00012001, 0x400D8030, "Memory"); + do + { + reg = __readMemory32(0x400D8030, "Memory"); + }while((reg & 0x80000000) == 0); + // Disable bypass of SYS PLL + __writeMemory32(0x00002001, 0x400D8030, "Memory"); + + // PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327 + // Ungate SYS PLL PFD2 + reg = __readMemory32(0x400D8100, "Memory"); + reg &= ~0xBF0000; + reg |= 0x1D0000; + __writeMemory32(reg, 0x400D8100, "Memory"); + + // SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01 + // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2 + // SEMC_CLK_SEL: 1 SEMC_ALT_CLK + __writeMemory32(0x00010D40, 0x400FC014, "Memory"); + + __message "clock init done\n"; +} + +_sdr_Init() +{ + // Config IOMUX + __writeMemory32(0x00000000, 0x401F8014, "Memory"); + __writeMemory32(0x00000000, 0x401F8018, "Memory"); + __writeMemory32(0x00000000, 0x401F801C, "Memory"); + __writeMemory32(0x00000000, 0x401F8020, "Memory"); + __writeMemory32(0x00000000, 0x401F8024, "Memory"); + __writeMemory32(0x00000000, 0x401F8028, "Memory"); + __writeMemory32(0x00000000, 0x401F802C, "Memory"); + __writeMemory32(0x00000000, 0x401F8030, "Memory"); + __writeMemory32(0x00000000, 0x401F8034, "Memory"); + __writeMemory32(0x00000000, 0x401F8038, "Memory"); + __writeMemory32(0x00000000, 0x401F803C, "Memory"); + __writeMemory32(0x00000000, 0x401F8040, "Memory"); + __writeMemory32(0x00000000, 0x401F8044, "Memory"); + __writeMemory32(0x00000000, 0x401F8048, "Memory"); + __writeMemory32(0x00000000, 0x401F804C, "Memory"); + __writeMemory32(0x00000000, 0x401F8050, "Memory"); + __writeMemory32(0x00000000, 0x401F8054, "Memory"); + __writeMemory32(0x00000000, 0x401F8058, "Memory"); + __writeMemory32(0x00000000, 0x401F805C, "Memory"); + __writeMemory32(0x00000000, 0x401F8060, "Memory"); + __writeMemory32(0x00000000, 0x401F8064, "Memory"); + __writeMemory32(0x00000000, 0x401F8068, "Memory"); + __writeMemory32(0x00000000, 0x401F806C, "Memory"); + __writeMemory32(0x00000000, 0x401F8070, "Memory"); + __writeMemory32(0x00000000, 0x401F8074, "Memory"); + __writeMemory32(0x00000000, 0x401F8078, "Memory"); + __writeMemory32(0x00000000, 0x401F807C, "Memory"); + __writeMemory32(0x00000000, 0x401F8080, "Memory"); + __writeMemory32(0x00000000, 0x401F8084, "Memory"); + __writeMemory32(0x00000000, 0x401F8088, "Memory"); + __writeMemory32(0x00000000, 0x401F808C, "Memory"); + __writeMemory32(0x00000000, 0x401F8090, "Memory"); + __writeMemory32(0x00000000, 0x401F8094, "Memory"); + __writeMemory32(0x00000000, 0x401F8098, "Memory"); + __writeMemory32(0x00000000, 0x401F809C, "Memory"); + __writeMemory32(0x00000000, 0x401F80A0, "Memory"); + __writeMemory32(0x00000000, 0x401F80A4, "Memory"); + __writeMemory32(0x00000000, 0x401F80A8, "Memory"); + __writeMemory32(0x00000000, 0x401F80AC, "Memory"); + __writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION + + // PAD ctrl + // drive strength = 0x7 to increase drive strength + // otherwise the data7 bit may fail. + __writeMemory32(0x000110F9, 0x401F8204, "Memory"); + __writeMemory32(0x000110F9, 0x401F8208, "Memory"); + __writeMemory32(0x000110F9, 0x401F820C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8210, "Memory"); + __writeMemory32(0x000110F9, 0x401F8214, "Memory"); + __writeMemory32(0x000110F9, 0x401F8218, "Memory"); + __writeMemory32(0x000110F9, 0x401F821C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8220, "Memory"); + __writeMemory32(0x000110F9, 0x401F8224, "Memory"); + __writeMemory32(0x000110F9, 0x401F8228, "Memory"); + __writeMemory32(0x000110F9, 0x401F822C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8230, "Memory"); + __writeMemory32(0x000110F9, 0x401F8234, "Memory"); + __writeMemory32(0x000110F9, 0x401F8238, "Memory"); + __writeMemory32(0x000110F9, 0x401F823C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8240, "Memory"); + __writeMemory32(0x000110F9, 0x401F8244, "Memory"); + __writeMemory32(0x000110F9, 0x401F8248, "Memory"); + __writeMemory32(0x000110F9, 0x401F824C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8250, "Memory"); + __writeMemory32(0x000110F9, 0x401F8254, "Memory"); + __writeMemory32(0x000110F9, 0x401F8258, "Memory"); + __writeMemory32(0x000110F9, 0x401F825C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8260, "Memory"); + __writeMemory32(0x000110F9, 0x401F8264, "Memory"); + __writeMemory32(0x000110F9, 0x401F8268, "Memory"); + __writeMemory32(0x000110F9, 0x401F826C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8270, "Memory"); + __writeMemory32(0x000110F9, 0x401F8274, "Memory"); + __writeMemory32(0x000110F9, 0x401F8278, "Memory"); + __writeMemory32(0x000110F9, 0x401F827C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8280, "Memory"); + __writeMemory32(0x000110F9, 0x401F8284, "Memory"); + __writeMemory32(0x000110F9, 0x401F8288, "Memory"); + __writeMemory32(0x000110F9, 0x401F828C, "Memory"); + __writeMemory32(0x000110F9, 0x401F8290, "Memory"); + __writeMemory32(0x000110F9, 0x401F8294, "Memory"); + __writeMemory32(0x000110F9, 0x401F8298, "Memory"); + __writeMemory32(0x000110F9, 0x401F829C, "Memory"); + __writeMemory32(0x000110F9, 0x401F82A0, "Memory"); + + // Config SDR Controller Registers/ + __writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR + __writeMemory32(0x00000081, 0x402F0008, "Memory"); // BMCR0 + __writeMemory32(0x00000081, 0x402F000C, "Memory"); // BMCR1 + __writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB + + __writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0 + __writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1 + __writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2 + __writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3 + + __writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0 + __writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1 + __writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2 + + __writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA + SDRAM_WaitIpCmdDone(); + __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + __writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT + __writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS + SDRAM_WaitIpCmdDone(); + + __writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done. + + __message "SDRAM init done\n"; +} + +restoreFlexRAM() +{ + __var base; + __var value; + + base = 0x400AC000; + + value = __readMemory32(base + 0x44, "Memory"); + value &= ~(0xFFFFFFFF); + value |= 0x55AFFA55; + __writeMemory32(value, base + 0x44, "Memory"); + + value = __readMemory32(base + 0x40, "Memory"); + value |= (1 << 2); + __writeMemory32(value, base + 0x40, "Memory"); + __message "FlexRAM configuration is restored"; +} + +execUserPreload() +{ + restoreFlexRAM(); + _load_dcdc_trim(); + _clock_init(); + _sdr_Init(); + __message "execUserPreload() done.\n"; +} + +execUserReset() +{ + restoreFlexRAM(); + _load_dcdc_trim(); + _clock_init(); + _sdr_Init(); + __message "execUserReset() done.\n"; +} + diff --git a/bsp/imxrt/imxrt1060-nxp-evk/project.ewd b/bsp/imxrt/imxrt1060-nxp-evk/project.ewd new file mode 100644 index 0000000000..8eafc09c34 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/project.ewd @@ -0,0 +1,1546 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rtthread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state>$PROJ_DIR$/evkmimxrt1060_sdram_init.mac</state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1062xxx6A.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.32.1.18618</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>9.30.1.50052</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>0</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashIMXRT1060_EVK_FlexSPI.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>4</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + 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<state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/bsp/imxrt/imxrt1060-nxp-evk/project.ewp b/bsp/imxrt/imxrt1060-nxp-evk/project.ewp new file mode 100644 index 0000000000..d8df37cf4d --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/project.ewp @@ -0,0 +1,1613 @@ +<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>rtthread</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>35</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>BrowseInfoPath</name>
+ <state>rtthread\BrowseInfo</state>
+ </option>
+ <option>
+ <name>ExePath</name>
+ <state>build\iar\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>build\iar\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>build\iar\List</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.6.53380</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>9.30.1.50052</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>MIMXRT1062xxx6A NXP MIMXRT1062xxx6A</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CoreVariant</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>MIMXRT1062xxx6A NXP MIMXRT1062xxx6A</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>6</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>OGCMSISPackSelectDevice</name>
+ </option>
+ <option>
+ <name>OgLibHeap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGLibAdditionalLocale</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenLocaleTags</name>
+ <state />
+ </option>
+ <option>
+ <name>GenLocaleDisplayOnly</name>
+ <state />
+ </option>
+ <option>
+ <name>DSPExtension</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TrustZone</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>TrustZoneModes</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGAarch64Abi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OG_32_64Device</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BuildFilesPath</name>
+ <state>rtthread</state>
+ </option>
+ <option>
+ <name>PointerAuthentication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU64</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>37</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state />
+ <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
+ <state>RT_USING_DLIBC</state>
+ <state>RT_USING_LIBC</state>
+ <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
+ <state>_DLIB_FILE_DESCRIPTOR</state>
+ <state>CPU_MIMXRT1062DVL6A</state>
+ <state>SKIP_SYSCLK_INIT</state>
+ <state>EVK_MCIMXRM</state>
+ <state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
+ <state>FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1</state>
+ <state>DATA_SECTION_IS_CACHEABLE=0</state>
+ <state>XIP_EXTERNAL_FLASH=1</state>
+ <state>XIP_BOOT_HEADER_ENABLE=1</state>
+ <state>ENDIANNESS</state>
+ <state>USE_RTOS</state>
+ <state>__RTTHREAD__</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state>Pa082,Pa050,Pe167</state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state />
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state />
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state />
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>00000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state />
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state />
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state />
+ <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs</state>
+ <state>$PROJ_DIR$\..\..\..\components\finsh</state>
+ <state>$PROJ_DIR$\board\MCUX_Config</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include\posix</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
+ <state>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include\netif</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
+ <state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
+ <state>$PROJ_DIR$\..\libraries\drivers</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\include</state>
+ <state>$PROJ_DIR$\..\libraries\MIMXRT1060\CMSIS\Include</state>
+ <state>$PROJ_DIR$\.</state>
+ <state>$PROJ_DIR$\xip</state>
+ <state>$PROJ_DIR$\..\..\..\components\utilities\libadt</state>
+ <state>$PROJ_DIR$\board</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+ <state>$PROJ_DIR$\board\ports</state>
+ <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\class</state>
+ <state>$PROJ_DIR$\applications</state>
+ <state>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\lwip\port</state>
+ <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat</state>
+ <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
+ <state>$PROJ_DIR$\..\..\..\include</state>
+ <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
+ <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\netdev\include</state>
+ <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include\ipv4</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptStrategySlave</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCGuardCalls</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccExceptions2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccRTTI2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OICompilerExtraOption</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCStackProtection</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>11</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
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+ <name>IlinkStackControlFile</name>
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+ <name>IlinkStackCallGraphFile</name>
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+ <name>IlinkTrustzoneImportLibraryOut</name>
+ <state>template_import_lib.o</state>
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+ <state>###Unitialized###</state>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
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+ <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c</name>
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+ <file>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\phy\phy.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\block_dev.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\gpt.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmc.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmcsd_core.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sd.c</name>
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+ <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sdio.c</name>
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+ <file>
+ <name>$PROJ_DIR$\board\MCUX_Config\pin_mux.c</name>
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+ <file>
+ <name>$PROJ_DIR$\board\board.c</name>
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+ <file>
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+ <file>
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+ <file>
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+ <file>
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+ <file>
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+ <file>
+ <name>$PROJ_DIR$\..\libraries\drivers\drv_uart.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\libraries\drivers\drv_usbh.c</name>
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+ <file>
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+ <file>
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+ <file>
+ <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_framework.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_hci.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\libraries\drivers\usb\phy\usb_phy.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ffunicode.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name>
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+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name>
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+ <group>
+ <name>Finsh</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\finsh\msh_file.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Kernel</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Libraries</name>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_lpuart.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\system_MIMXRT1062.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_xbara.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_clock.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_usdhc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_gpio.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_xbarb.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_enet.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_common.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_semc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_os_abstraction_rtthread.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_cache.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_common_arm.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\iar\startup_MIMXRT1062.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\generic_list.c</name>
+ </file>
+ </group>
+ <group>
+ <name>lwIP</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\api_lib.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\api_msg.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\err.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netbuf.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netdb.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netifapi.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\sockets.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\tcpip.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\apps\ping\ping.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\def.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\dns.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\inet_chksum.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\init.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ip.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\autoip.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\dhcp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\etharp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\icmp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\igmp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_addr.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_frag.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\memp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\netif.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\pbuf.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\raw.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\stats.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\sys.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_in.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_out.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\timeouts.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\udp.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\netif\ethernet.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\netif\lowpan6.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\port\ethernetif.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\lwip\port\sys_arch.c</name>
+ </file>
+ </group>
+ <group>
+ <name>POSIX</name>
+ </group>
+ <group>
+ <name>rt_usbh</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\hub.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\usbhost.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\class\udisk.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\class\mass.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\driver.c</name>
+ </file>
+ </group>
+ <group>
+ <name>SAL</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
+ </file>
+ </group>
+ <group>
+ <name>xip</name>
+ <file>
+ <name>$PROJ_DIR$\xip\evkmimxrt1060_flexspi_nor_config.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
+ </file>
+ </group>
+</project>
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/project.eww b/bsp/imxrt/imxrt1060-nxp-evk/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/project.eww @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\project.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h index d9a6714d79..9902699656 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h @@ -45,6 +45,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50000 + #define RT_USING_CACHE #define RT_USING_CPU_FFS #define ARCH_ARM @@ -52,6 +53,7 @@ #define ARCH_ARM_CORTEX_FPU #define ARCH_ARM_CORTEX_M7 + /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT @@ -71,6 +73,28 @@ #define MSH_USING_BUILT_IN_COMMANDS #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -81,10 +105,16 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_I2C #define RT_USING_I2C_BITOPS +#define RT_USING_PHY #define RT_USING_PIN /* Using USB */ +#define RT_USING_USB +#define RT_USING_USB_HOST +#define RT_USBH_MSTORAGE +#define UDISK_MOUNTPOINT "/" +#define RT_USBD_THREAD_STACK_SZ 4096 /* C/C++ and POSIX layer */ @@ -101,6 +131,13 @@ /* Network */ +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 /* Utilities */ @@ -215,7 +252,6 @@ /* Device Control */ - /* Other */ /* Signal IO */ @@ -226,13 +262,14 @@ /* Privated Packages of RealThread */ -/* Network Utilities */ +/* Other */ -/* RT-Thread Smart */ +/* Signal IO */ #define SOC_IMXRT1060_SERIES + /* Hardware Drivers Config */ #define BSP_USING_4MFLASH @@ -240,16 +277,15 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_SDRAM /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO -#define BSP_USING_I2C -#define BSP_USING_I2C1 -#define HW_I2C1_BADURATE_100kHZ +#define BSP_USING_USB +#define BSP_USB0_HOST #define BSP_USING_LPUART #define BSP_USING_LPUART1 -#define BSP_USING_PXP #define BSP_USING_CACHE /* Board extended module Drivers */ diff --git a/bsp/imxrt/imxrt1060-nxp-evk/template.ewd b/bsp/imxrt/imxrt1060-nxp-evk/template.ewd new file mode 100644 index 0000000000..b56cd99889 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/template.ewd @@ -0,0 +1,1546 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rtthread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1062xxx6A.ddf</state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>1</state> + </option> + <option> + <name>OCProductVersion</name> + <state>8.20.1.14181</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>CMSISDAP_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>9.30.1.50052</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>1</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>1</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + 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<name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>2</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/bsp/imxrt/imxrt1060-nxp-evk/template.ewp b/bsp/imxrt/imxrt1060-nxp-evk/template.ewp new file mode 100644 index 0000000000..6dd50d10eb --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/template.ewp @@ -0,0 +1,1074 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>rtthread</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>35</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>BrowseInfoPath</name>
+ <state>rtthread\BrowseInfo</state>
+ </option>
+ <option>
+ <name>ExePath</name>
+ <state>build\iar\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>build\iar\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>build\iar\List</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter, without multibyte support.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.6.53380</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>9.30.1.50052</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>MIMXRT1062xxx6A NXP MIMXRT1062xxx6A</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibThreads</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CoreVariant</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>MIMXRT1062xxx6A NXP MIMXRT1062xxx6A</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>6</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>32</version>
+ <state>41</state>
+ </option>
+ <option>
+ <name>OGCMSISPackSelectDevice</name>
+ </option>
+ <option>
+ <name>OgLibHeap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGLibAdditionalLocale</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGPrintfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfVariant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGScanfMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenLocaleTags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GenLocaleDisplayOnly</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DSPExtension</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TrustZone</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>TrustZoneModes</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGAarch64Abi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OG_32_64Device</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BuildFilesPath</name>
+ <state>rtthread</state>
+ </option>
+ <option>
+ <name>PointerAuthentication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU64</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>37</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state>Pa082,Pa050,Pe167</state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>00000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCNoLiteralPool</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptStrategySlave</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCGuardCalls</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEncOutputBom</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEncInput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccExceptions2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccRTTI2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OICompilerExtraOption</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCStackProtection</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>11</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
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+ </package> + </checks_tree> + </cstat_settings> + </data> + </settings> + <settings> + <name>RuntimeChecking</name> + <archiveVersion>0</archiveVersion> + <data> + <version>2</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>GenRtcDebugHeap</name> + <state>0</state> + </option> + <option> + <name>GenRtcEnableBoundsChecking</name> + <state>0</state> + </option> + <option> + <name>GenRtcCheckPtrsNonInstrMem</name> + <state>1</state> + </option> + <option> + <name>GenRtcTrackPointerBounds</name> + <state>1</state> + </option> + <option> + <name>GenRtcCheckAccesses</name> + <state>1</state> + </option> + <option> + <name>GenRtcGenerateEntries</name> + <state>0</state> + </option> + <option> + <name>GenRtcNrTrackedPointers</name> + <state>1000</state> + </option> + <option> + <name>GenRtcIntOverflow</name> + <state>0</state> + </option> + <option> + <name>GenRtcIncUnsigned</name> + <state>0</state> + </option> + <option> + <name>GenRtcIntConversion</name> + <state>0</state> + </option> + <option> + <name>GenRtcInclExplicit</name> + <state>0</state> + </option> + <option> + <name>GenRtcIntShiftOverflow</name> + <state>0</state> + </option> + <option> + <name>GenRtcInclUnsignedShiftOverflow</name> + <state>0</state> + </option> + <option> + <name>GenRtcUnhandledCase</name> + <state>0</state> + </option> + <option> + <name>GenRtcDivByZero</name> + <state>0</state> + </option> + <option> + <name>GenRtcEnable</name> + <state>0</state> + </option> + <option> + <name>GenRtcCheckPtrsNonInstrFunc</name> + <state>1</state> + </option> + </data> + </settings> + </configuration> +</project> diff --git a/bsp/imxrt/imxrt1060-nxp-evk/template.eww b/bsp/imxrt/imxrt1060-nxp-evk/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/template.eww @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\template.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.c b/bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.c deleted file mode 100644 index 69af1b8963..0000000000 --- a/bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "evkbmimxrt1060_flexspi_nor_config.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const flexspi_nor_config_t qspiflash_config = { - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.c b/bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.c new file mode 100644 index 0000000000..8b3023a0e8 --- /dev/null +++ b/bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.c @@ -0,0 +1,70 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1060_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.h b/bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.h index 76503d6083..f416a822f9 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.h @@ -1,12 +1,12 @@ /* - * Copyright 2021 NXP + * Copyright 2018-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ -#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ #include <stdint.h> #include <stdbool.h> @@ -265,4 +265,4 @@ extern "C" { #ifdef __cplusplus } #endif -#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ +#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h index 79eb0d82f8..38d5d1833e 100644 --- a/bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h +++ b/bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -9,13 +9,15 @@ #define __FLEXSPI_NOR_BOOT_H__ #include <stdint.h> -#include "board.h" #include "fsl_common.h" +#ifndef BOARD_FLASH_SIZE +#include "board.h" +#endif /*! @name Driver version */ /*@{*/ -/*! @brief XIP_DEVICE driver version 2.0.2. */ -#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief XIP_DEVICE driver version 2.0.3. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /************************************* @@ -75,8 +77,8 @@ extern uint32_t __Vectors[]; extern uint32_t __VECTOR_TABLE[]; #define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) #elif defined(__GNUC__) -extern uint32_t __isr_vector[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__isr_vector) +extern uint32_t __VECTOR_TABLE[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) #endif #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) @@ -100,7 +102,12 @@ typedef struct _boot_data_ uint32_t placeholder; /* placehoder to make even 0x10 size */ } BOOT_DATA_T; +#ifdef FlexSPI1_AMBA_BASE +#define FLASH_BASE FlexSPI1_AMBA_BASE +#else #define FLASH_BASE FlexSPI_AMBA_BASE +#endif + #if defined(BOARD_FLASH_SIZE) #define FLASH_SIZE BOARD_FLASH_SIZE #else diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/.config b/bsp/imxrt/imxrt1170-nxp-evk/m7/.config index 7d21ef3ff2..7560427a65 100644 --- a/bsp/imxrt/imxrt1170-nxp-evk/m7/.config +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/.config @@ -84,8 +84,10 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50000 + # CONFIG_RT_USING_CACHE is not set # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set + # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -160,9 +162,12 @@ CONFIG_RT_USING_PIN=y # # Using USB # -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set +CONFIG_RT_USING_USB=y +CONFIG_RT_USING_USB_HOST=y +# CONFIG_RT_USBH_MSTORAGE is not set +# CONFIG_RT_USBH_HID is not set # CONFIG_RT_USING_USB_DEVICE is not set +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 # # C/C++ and POSIX layer @@ -308,6 +313,7 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -955,6 +961,7 @@ CONFIG_NETDEV_IPV6=0 # Uncategorized # + # # Privated Packages of RealThread # @@ -1012,6 +1019,7 @@ CONFIG_NETDEV_IPV6=0 # CONFIG_PKG_USING_UKERNEL is not set # CONFIG_PKG_USING_TRACE_AGENT is not set + # # Hardware Drivers Config # @@ -1024,7 +1032,9 @@ CONFIG_SOC_MIMXRT1176DVMAA=y # CONFIG_BSP_USING_DMA is not set CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USB1_HOST is not set # CONFIG_BSP_USING_USB is not set + # CONFIG_BSP_USING_SDIO is not set CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd index e0424639a2..09d4a99002 100644 --- a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd @@ -76,7 +76,7 @@ </option> <option> <name>OCDownloadVerifyAll</name> - <state>1</state> + <state>0</state> </option> <option> <name>OCProductVersion</name> @@ -84,15 +84,15 @@ </option> <option> <name>OCDynDriverList</name> - <state>CMSISDAP_ID</state> + <state>JLINK_ID</state> </option> <option> <name>OCLastSavedByProductVersion</name> - <state>9.20.4.46976</state> + <state>9.30.1.50052</state> </option> <option> <name>UseFlashLoader</name> - <state>1</state> + <state>0</state> </option> <option> <name>CLowLevel</name> @@ -112,7 +112,7 @@ </option> <option> <name>FlashLoadersV3</name> - <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1170_FlexSPI.board</state> + <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.board</state> </option> <option> <name>OCImagesSuppressCheck1</name> @@ -429,7 +429,7 @@ </option> <option> <name>OCProbeConfig</name> - <state>$TOOLKIT_DIR$\config\debugger\NXP\IMXRT1170.ProbeConfig</state> + <state>$TOOLKIT_DIR$/config/debugger/NXP/IMXRT1170.ProbeConfig</state> </option> <option> <name>CMSISDAPProbeConfigRadio</name> @@ -1417,7 +1417,7 @@ </option> <option> <name>CCXds100ResetList</name> - <version>1</version> + <version>0</version> <state>0</state> </option> <option> diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp index d73d08a449..528c371d72 100644 --- a/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp @@ -10,10 +10,14 @@ <name>General</name>
<archiveVersion>3</archiveVersion>
<data>
- <version>31</version>
+ <version>35</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
+ <name>BrowseInfoPath</name>
+ <state>rtthread\BrowseInfo</state>
+ </option>
+ <option>
<name>ExePath</name>
<state>build\iar\Exe</state>
</option>
@@ -57,7 +61,7 @@ </option>
<option>
<name>RTDescription</name>
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -65,15 +69,7 @@ </option>
<option>
<name>OGLastSavedByProductVersion</name>
- <state>8.32.1.18618</state>
- </option>
- <option>
- <name>GeneralEnableMisra</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraVerbose</name>
- <state>0</state>
+ <state>9.30.1.50052</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
@@ -96,26 +92,12 @@ <state>0</state>
</option>
<option>
- <name>GeneralMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>GeneralMisraVer</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GBECoreSlave</name>
- <version>26</version>
+ <version>32</version>
<state>41</state>
</option>
<option>
@@ -132,7 +114,7 @@ </option>
<option>
<name>CoreVariant</name>
- <version>26</version>
+ <version>32</version>
<state>41</state>
</option>
<option>
@@ -155,7 +137,7 @@ </option>
<option>
<name>GFPUCoreSlave2</name>
- <version>26</version>
+ <version>32</version>
<state>41</state>
</option>
<option>
@@ -208,13 +190,33 @@ <version>0</version>
<state>0</state>
</option>
+ <option>
+ <name>OGAarch64Abi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OG_32_64Device</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BuildFilesPath</name>
+ <state>rtthread</state>
+ </option>
+ <option>
+ <name>PointerAuthentication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU64</name>
+ <state>1</state>
+ </option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>35</version>
+ <version>37</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -236,6 +238,8 @@ <state>ARM_MATH_CM7</state>
<state>USE_SDRAM</state>
<state>SOC_IMXRT1170_SERIES</state>
+ <state>ENDIANNESS</state>
+ <state>USE_RTOS</state>
<state>__RTTHREAD__</state>
</option>
<option>
@@ -356,35 +360,35 @@ <state />
</option>
<option>
- <name>CompilerMisraOverride</name>
- <state>0</state>
- </option>
- <option>
<name>CCIncludePath2</name>
<state />
- <state>$PROJ_DIR$\..\..\..\components\finsh</state>
- <state>$PROJ_DIR$\board\MCUX_Config</state>
- <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
- <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176</state>
- <state>$PROJ_DIR$\xip</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
- <state>$PROJ_DIR$\..\libraries\drivers</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\extension</state>
+ <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176</state>
+ <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\CMSIS\Include</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\io\stdio</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\io\poll</state>
+ <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7</state>
+ <state>$PROJ_DIR$\..\..\libraries\drivers</state>
+ <state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\.</state>
- <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers</state>
+ <state>$PROJ_DIR$\xip</state>
<state>$PROJ_DIR$\board</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+ <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\net\netdev\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
+ <state>$PROJ_DIR$\board\MCUX_Config</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\class</state>
<state>$PROJ_DIR$\board\ports</state>
<state>$PROJ_DIR$\applications</state>
- <state>$PROJ_DIR$\..\libraries\MIMXRT1170\CMSIS\Include</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
- <state>$PROJ_DIR$\..\..\..\include</state>
- <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
- <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7</state>
- <state>$PROJ_DIR$\..\..\..\components\net\netdev\include</state>
- <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7</state>
- <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
+ <state>$PROJ_DIR$\..\..\..\..\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
+ <state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\finsh</state>
+ <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost</state>
</option>
<option>
<name>CCStdIncCheck</name>
@@ -412,16 +416,6 @@ <state>1</state>
</option>
<option>
- <name>CompilerMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>CompilerMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
<name>CCPosIndRopi</name>
<state>0</state>
</option>
@@ -502,13 +496,17 @@ <name>OICompilerExtraOption</name>
<state>1</state>
</option>
+ <option>
+ <name>CCStackProtection</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>10</version>
+ <version>11</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -664,6 +662,10 @@ <name>AsmNoLiteralPool</name>
<state>0</state>
</option>
+ <option>
+ <name>PreInclude</name>
+ <state />
+ </option>
</data>
</settings>
<settings>
@@ -702,15 +704,11 @@ <data>
<extensions />
<cmdline />
- <hasPrio>0</hasPrio>
+ <hasPrio>208</hasPrio>
+ <buildSequence>inputOutputBased</buildSequence>
</data>
</settings>
<settings>
- <name>BICOMP</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- <settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
<data>
@@ -722,7 +720,7 @@ <name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
- <version>22</version>
+ <version>27</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -730,10 +728,6 @@ <state>1</state>
</option>
<option>
- <name>XLinkMisraHandler</name>
- <state>0</state>
- </option>
- <option>
<name>IlinkInputFileSlave</name>
<state>0</state>
</option>
@@ -1042,6 +1036,58 @@ <name>OILinkExtraOption</name>
<state>1</state>
</option>
+ <option>
+ <name>IlinkRawBinaryFile2</name>
+ <state />
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol2</name>
+ <state />
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment2</name>
+ <state />
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign2</name>
+ <state />
+ </option>
+ <option>
+ <name>IlinkLogCrtRoutineSelection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogFragmentInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInlining</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogMerging</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkDemangle</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkWrapperFileEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkWrapperFile</name>
+ <state />
+ </option>
+ <option>
+ <name>IlinkProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkFpuProcessor</name>
+ <state>1</state>
+ </option>
</data>
</settings>
<settings>
@@ -1065,11 +1111,6 @@ </option>
</data>
</settings>
- <settings>
- <name>BILINK</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
</configuration>
<group>
<name>Applications</name>
@@ -1083,106 +1124,106 @@ <group>
<name>Compiler</name>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdio.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdio.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
</file>
</group>
<group>
<name>CPU</name>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\backtrace.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
</file>
</group>
<group>
<name>DeviceDrivers</name>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\cputime\cputime.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\misc\pin.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\phy\phy.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\phy\phy.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\serial\serial.c</name>
</file>
</group>
<group>
@@ -1200,124 +1241,166 @@ <name>$PROJ_DIR$\board\dcd.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\drivers\drv_gpio.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\drv_common.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\drv_gpio.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\drv_uart.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\drv_usbh.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_devices.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\drivers\drv_uart.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_ehci.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_framework.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_hci.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\drivers\usb\phy\usb_phy.c</name>
</file>
</group>
<group>
<name>Finsh</name>
<file>
- <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\finsh\shell.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\finsh\msh.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\finsh\cmd.c</name>
</file>
</group>
<group>
<name>Kernel</name>
<file>
- <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\clock.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\components.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\device.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\idle.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\ipc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\irq.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\kservice.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\memheap.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\mempool.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\object.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\scheduler.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\thread.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\src\timer.c</name>
</file>
</group>
<group>
<name>Libraries</name>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_os_abstraction_rtthread.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\iar\startup_MIMXRT1176_cm7.s</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\iar\startup_MIMXRT1176_cm7.s</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c</name>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\generic_list.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c</name>
</file>
</group>
<group>
<name>POSIX</name>
</group>
<group>
+ <name>rt_usbh</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\hub.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\usbhost.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\driver.c</name>
+ </file>
+ </group>
+ <group>
<name>SAL</name>
<file>
- <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\net\netdev\src\netdev.c</name>
</file>
<file>
- <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
+ <name>$PROJ_DIR$\..\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
</file>
</group>
<group>
<name>xip</name>
<file>
- <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
+ <name>$PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c</name>
</file>
<file>
- <name>$PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c</name>
+ <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
</file>
</group>
</project>
diff --git a/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h index abbeebaf15..2661e6716d 100644 --- a/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h +++ b/bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h @@ -80,6 +80,9 @@ /* Using USB */ +#define RT_USING_USB +#define RT_USING_USB_HOST +#define RT_USBD_THREAD_STACK_SZ 4096 /* C/C++ and POSIX layer */ @@ -217,23 +220,14 @@ /* Device Control */ +/* Privated Packages of RealThread */ /* Other */ /* Signal IO */ - /* Uncategorized */ -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - - -/* RT-Thread Smart */ - - /* Hardware Drivers Config */ #define BSP_USING_QSPIFLASH @@ -242,6 +236,8 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_USB +#define BSP_USB0_HOST #define BSP_USING_LPUART #define BSP_USING_LPUART1 diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.h index 54ff24aed2..355a347ada 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.h @@ -4,6 +4,8 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler @@ -12,14 +14,14 @@ ** MCUXpresso Compiler ** ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 -** Version: rev. 1.3, 2021-08-10 -** Build: b211108 +** Version: rev. 1.4, 2022-03-25 +** Build: b220720 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1062 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -38,14 +40,16 @@ ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. ** - rev. 1.3 (2021-08-10) ** Update header files to align with IMXRT1060RM Rev.3. +** - rev. 1.4 (2022-03-25) +** Add RT1060X device ** ** ################################################################### */ /*! * @file MIMXRT1062.h - * @version 1.3 - * @date 2021-08-10 + * @version 1.4 + * @date 2022-03-25 * @brief CMSIS Peripheral Access Layer for MIMXRT1062 * * CMSIS Peripheral Access Layer for MIMXRT1062 @@ -58,7 +62,7 @@ * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0003U +#define MCU_MEM_MAP_VERSION_MINOR 0x0004U /* ---------------------------------------------------------------------------- @@ -160,7 +164,7 @@ typedef enum IRQn { ADC2_IRQn = 68, /**< ADC2 interrupt */ DCDC_IRQn = 69, /**< DCDC interrupt */ Reserved86_IRQn = 70, /**< Reserved interrupt */ - Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO10_Combined_0_31_IRQn = 71, /**< Combined interrupt indication for GPIO10 signal 0 throughout 31 */ GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ @@ -198,7 +202,7 @@ typedef enum IRQn { PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ FLEXSPI2_IRQn = 107, /**< FlexSPI2 interrupt */ FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ - SEMC_IRQn = 109, /**< Reserved interrupt */ + SEMC_IRQn = 109, /**< SEMC interrupt */ USDHC1_IRQn = 110, /**< USDHC1 interrupt */ USDHC2_IRQn = 111, /**< USDHC2 interrupt */ USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ @@ -1371,11 +1375,14 @@ typedef struct { #define ADC_HC_ADCH_MASK (0x1FU) #define ADC_HC_ADCH_SHIFT (0U) /*! ADCH - Input Channel Select + * 0b00000-0b01111..External channels 0 to 15 See External Signals for more information * 0b10000..External channel selection from ADC_ETC + * 0b10001-0b10111..Reserved * 0b11000..Reserved. * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally * 0b11010..Reserved. * 0b11011..Reserved. + * 0b11100-0b11110..Reserved. * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. */ #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) @@ -4196,21 +4203,45 @@ typedef struct { __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ } MB_8B[64]; - struct { /* offset: 0x80, array step: 0x18 */ - __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */ - __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */ - __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ - } MB_16B[42]; - struct { /* offset: 0x80, array step: 0x28 */ - __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */ - __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */ - __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ - } MB_32B[24]; - struct { /* offset: 0x80, array step: 0x48 */ - __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */ - __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */ - __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ - } MB_64B[14]; + struct { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B_L[21]; + uint8_t RESERVED_0[8]; + struct { /* offset: 0x280, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4 */ + } MB_16B_H[21]; + } MB_16B; + struct { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B_L[12]; + uint8_t RESERVED_0[32]; + struct { /* offset: 0x280, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4 */ + } MB_32B_H[12]; + } MB_32B; + struct { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B_L[7]; + uint8_t RESERVED_0[8]; + struct { /* offset: 0x280, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4 */ + } MB_64B_H[7]; + } MB_64B; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ @@ -4249,10 +4280,10 @@ typedef struct { #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode - * 0b00..Format A One full ID (standard or extended) per ID filter Table element. - * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. - * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. - * 0b11..Format D All frames rejected. + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) @@ -4267,16 +4298,16 @@ typedef struct { #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable - * 0b1..Abort enabled - * 0b0..Abort disabled + * 0b0..Abort disabled. + * 0b1..Abort enabled. */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable - * 0b1..Local Priority enabled - * 0b0..Local Priority disabled + * 0b0..Local Priority disabled. + * 0b1..Local Priority enabled. */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) @@ -4291,16 +4322,17 @@ typedef struct { #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual Rx Masking And Queue Enable + * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy + * applications, the reading of C/S word locks the MB even if it is EMPTY. * 0b1..Individual Rx masking and queue feature are enabled. - * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self Reception Disable - * 0b1..Self reception disabled - * 0b0..Self reception enabled + * 0b0..Self-reception enabled. + * 0b1..Self-reception disabled. */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) @@ -4331,89 +4363,89 @@ typedef struct { #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable - * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. - * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. + * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake Up - * 0b1..FLEXCAN Self Wake Up feature is enabled - * 0b0..FLEXCAN Self Wake Up feature is disabled + * 0b0..FlexCAN Self Wake Up feature is disabled. + * 0b1..FlexCAN Self Wake Up feature is enabled. */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) /*! SUPV - Supervisor Mode - * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access - * behaves as though the access was done to an unimplemented register location - * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. + * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access + * behaves as though the access was done to an unimplemented register location. */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge - * 0b1..FLEXCAN in Freeze Mode, prescaler stopped - * 0b0..FLEXCAN not in Freeze Mode, prescaler running + * 0b0..FlexCAN not in Freeze mode, prescaler running. + * 0b1..FlexCAN in Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset - * 0b1..Reset the registers - * 0b0..No reset request + * 0b0..No reset request. + * 0b1..Resets the registers affected by soft reset. */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake Up Interrupt Mask - * 0b1..Wake Up Interrupt is enabled - * 0b0..Wake Up Interrupt is disabled + * 0b0..Wake Up interrupt is disabled. + * 0b1..Wake Up interrupt is enabled. */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready - * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode - * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. + * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN - * 0b1..Enters Freeze Mode if the FRZ bit is asserted. - * 0b0..No Freeze Mode request. + * 0b0..No Freeze mode request. + * 0b1..Enters Freeze mode if the FRZ bit is asserted. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Rx FIFO Enable - * 0b1..FIFO enabled - * 0b0..FIFO not enabled + * 0b0..Rx FIFO not enabled. + * 0b1..Rx FIFO enabled. */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable - * 0b1..Enabled to enter Freeze Mode - * 0b0..Not enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze mode. + * 0b1..Enabled to enter Freeze mode. */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable - * 0b1..Disable the FLEXCAN module - * 0b0..Enable the FLEXCAN module + * 0b0..Enable the FlexCAN module. + * 0b1..Disable the FlexCAN module. */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ @@ -4430,24 +4462,24 @@ typedef struct { #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode - * 0b1..FLEXCAN module operates in Listen Only Mode - * 0b0..Listen Only Mode is deactivated + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First - * 0b1..Lowest number buffer is transmitted first - * 0b0..Buffer with highest priority is transmitted first + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync - * 0b1..Timer Sync feature enabled - * 0b0..Timer Sync feature disabled + * 0b0..Timer sync feature disabled + * 0b1..Timer sync feature enabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) @@ -4462,49 +4494,49 @@ typedef struct { #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling - * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 - * preceding samples, a majority rule is used - * 0b0..Just one sample is used to determine the bit value + * 0b0..Just one sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples; a majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - Rx Warning Interrupt Mask - * 0b1..Rx Warning Interrupt enabled - * 0b0..Rx Warning Interrupt disabled + * 0b0..Rx Warning interrupt disabled. + * 0b1..Rx Warning interrupt enabled. */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - Tx Warning Interrupt Mask - * 0b1..Tx Warning Interrupt enabled - * 0b0..Tx Warning Interrupt disabled + * 0b0..Tx Warning interrupt disabled. + * 0b1..Tx Warning interrupt enabled. */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loop Back Mode - * 0b1..Loop Back enabled - * 0b0..Loop Back disabled + * 0b0..Loop Back disabled. + * 0b1..Loop Back enabled. */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask - * 0b1..Error interrupt enabled - * 0b0..Error interrupt disabled + * 0b0..Error interrupt disabled. + * 0b1..Error interrupt enabled. */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask - * 0b1..Bus Off interrupt enabled - * 0b0..Bus Off interrupt disabled + * 0b0..Bus Off interrupt disabled. + * 0b1..Bus Off interrupt enabled. */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) @@ -4629,24 +4661,24 @@ typedef struct { #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt - * 0b1..Indicates setting of any Error Bit in the Error and Status Register - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error bit in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt - * 0b1..FLEXCAN module entered 'Bus Off' state - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN In Reception - * 0b1..FLEXCAN is transmitting a message - * 0b0..FLEXCAN is receiving a message + * 0b0..FlexCAN is not receiving a message. + * 0b1..FlexCAN is receiving a message. */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) @@ -4655,111 +4687,111 @@ typedef struct { /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive - * 0b1x..Bus off + * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission - * 0b1..FLEXCAN is transmitting a message - * 0b0..FLEXCAN is receiving a message + * 0b0..FlexCAN is not transmitting a message. + * 0b1..FlexCAN is transmitting a message. */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - IDLE - * 0b1..CAN bus is now IDLE - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..CAN bus is now IDLE. */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - Rx Error Warning - * 0b1..Rx_Err_Counter >= 96 - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning - * 0b1..TX_Err_Counter >= 96 - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..TXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error - * 0b1..A Stuffing Error occurred since last read of this register. * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error - * 0b1..A Form Error occurred since last read of this register - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error + * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. - * 0b0..No such occurrence */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error - * 0b1..An ACK error occurred since last read of this register - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..An ACK error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error - * 0b1..At least one bit sent as dominant is received as recessive - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error - * 0b1..At least one bit sent as recessive is received as dominant - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - Rx Warning Interrupt Flag - * 0b1..The Rx error counter transition from < 96 to >= 96 - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - Tx Warning Interrupt Flag - * 0b1..The Tx error counter transition from < 96 to >= 96 - * 0b0..No such occurrence + * 0b0..No such occurrence. + * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status - * 0b1..FlexCAN is synchronized to the CAN bus - * 0b0..FlexCAN is not synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus. + * 0b1..FlexCAN is synchronized to the CAN bus. */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) @@ -4910,24 +4942,25 @@ typedef struct { #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO - * 0b1..MB5 completed transmission/reception or frames available in the FIFO - * 0b0..No such occurrence + * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 + * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when + * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning - * 0b1..MB6 completed transmission/reception or FIFO almost full - * 0b0..No such occurrence + * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 + * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow - * 0b1..MB7 completed transmission/reception or FIFO overflow - * 0b0..No such occurrence + * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 + * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) @@ -4980,25 +5013,25 @@ typedef struct { #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes - * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within + * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within * the incoming frame. Mask bits do apply. - * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing - * 0b1..Remote Request Frame is stored - * 0b0..Remote Response Frame is generated + * 0b0..Remote response frame is generated. + * 0b1..Remote request frame is stored. */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Mailboxes Reception Priority - * 0b1..Matching starts from Mailboxes and continues on Rx FIFO - * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + * 0b0..Matching starts from Rx FIFO and continues on mailboxes. + * 0b1..Matching starts from mailboxes and continues on Rx FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) @@ -5045,16 +5078,16 @@ typedef struct { #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Mailbox - * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. - * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status - * 0b1..Contents of IMB and LPTM are valid - * 0b0..Contents of IMB and LPTM are invalid + * 0b0..Contents of IMB and LPTM are invalid. + * 0b1..Contents of IMB and LPTM are valid. */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) @@ -5206,30 +5239,54 @@ typedef struct { #define CAN_WORD_COUNT_MB8B2 (2U) /* The count of CAN_CS */ -#define CAN_CS_COUNT_MB16B (42U) +#define CAN_CS_COUNT_MB16B_L (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B_L (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B_L (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B_L2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B_H (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B_H (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B_H (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B_H2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B_L (12U) /* The count of CAN_ID */ -#define CAN_ID_COUNT_MB16B (42U) +#define CAN_ID_COUNT_MB32B_L (12U) /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB16B (42U) +#define CAN_WORD_COUNT_MB32B_L (12U) /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB16B2 (4U) +#define CAN_WORD_COUNT_MB32B_L2 (8U) /* The count of CAN_CS */ -#define CAN_CS_COUNT_MB32B (24U) +#define CAN_CS_COUNT_MB32B_H (12U) /* The count of CAN_ID */ -#define CAN_ID_COUNT_MB32B (24U) +#define CAN_ID_COUNT_MB32B_H (12U) /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB32B (24U) +#define CAN_WORD_COUNT_MB32B_H (12U) /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB32B2 (8U) +#define CAN_WORD_COUNT_MB32B_H2 (8U) -/*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */ +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ /*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) @@ -5292,9 +5349,9 @@ typedef struct { /*! @} */ /* The count of CAN_CS */ -#define CAN_CS_COUNT_MB64B (14U) +#define CAN_CS_COUNT_MB64B_L (7U) -/*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */ +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ /*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) @@ -5319,9 +5376,9 @@ typedef struct { /*! @} */ /* The count of CAN_ID */ -#define CAN_ID_COUNT_MB64B (14U) +#define CAN_ID_COUNT_MB64B_L (7U) -/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */ +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ /*! @{ */ #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) @@ -5710,10 +5767,496 @@ typedef struct { /*! @} */ /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB64B (14U) +#define CAN_WORD_COUNT_MB64B_L (7U) /* The count of CAN_WORD */ -#define CAN_WORD_COUNT_MB64B2 (16U) +#define CAN_WORD_COUNT_MB64B_L2 (16U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. + */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. + */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. + */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. + */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B_H (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. + */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. + */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B_H (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. + */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B_H (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B_H2 (16U) /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) @@ -7043,6 +7586,7 @@ typedef struct { * 0b011..derive clock from PLL2 PFD0 * 0b100..derive clock from PLL2 PFD1 * 0b101..derive clock from PLL3 PFD1 + * 0b110-0b111..Reserved */ #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) @@ -8843,7 +9387,7 @@ typedef struct { #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) /*! ENABLE - Enable bit * 0b0..Spread spectrum modulation disabled - * 0b1..Soread spectrum modulation enabled + * 0b1..Spread spectrum modulation enabled */ #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) @@ -11791,10 +12335,16 @@ typedef struct { #define CSI_CR2_HSC_MASK (0xFFU) #define CSI_CR2_HSC_SHIFT (0U) +/*! HSC + * 0b00000000-0b11111111..Number of pixels to skip minus 1 + */ #define CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK) #define CSI_CR2_VSC_MASK (0xFF00U) #define CSI_CR2_VSC_SHIFT (8U) +/*! VSC + * 0b00000000-0b11111111..Number of rows to skip minus 1 + */ #define CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK) #define CSI_CR2_LVRM_MASK (0x70000U) @@ -21413,15 +21963,15 @@ typedef struct { /** Peripheral ENET2 base pointer */ #define ENET2 ((ENET_Type *)ENET2_BASE) /** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET_BASE, ENET2_BASE } +#define ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE } /** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET, ENET2 } +#define ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 } /** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_Receive_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_Error_IRQS { ENET_IRQn, ENET2_IRQn } -#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET2_1588_Timer_IRQn } -#define ENET_Ts_IRQS { ENET_1588_Timer_IRQn, ENET2_1588_Timer_IRQn } +#define ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn } +#define ENET_Ts_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } /* ENET Buffer Descriptor and Buffer Address Alignment. */ #define ENET_BUFF_ALIGNMENT (64U) @@ -21891,9 +22441,14 @@ typedef struct { #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop bit * 0b00..Stop bit disabled for transmitter/receiver/match store - * 0b01..Reserved for transmitter/receiver/match store - * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 - * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + * 0b01..Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on + * the configured shift edge when timer in stop condition + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not + * 0, receiver/match store will also store receive data on the configured shift edge when timer in stop + * condition + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not + * 1, receiver/match store will also store receive data on the configured shift edge when timer in stop + * condition */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) @@ -22538,7 +23093,7 @@ typedef struct { #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) -/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . See Clocks section for more details on clocking. +/*! SERCLKDIV - Serial root clock * 0b000..Divided by 1 * 0b001..Divided by 2 * 0b010..Divided by 3 @@ -22552,7 +23107,7 @@ typedef struct { #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) -/*! HSEN - Half Speed Serial Flash access Enable. +/*! HSEN - Half Speed Serial Flash Access Enable. * 0b0..Disable divide by 2 of serial flash clock for half speed commands. * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ @@ -22577,9 +23132,8 @@ typedef struct { #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) -/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, - * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is - * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). +/*! SCKFREERUNEN - This bit is used to enable SCLK output free-running. For FPGA applications, the + * external device may use SCLK as reference clock to its internal PLL. * 0b0..Disable. * 0b1..Enable. */ @@ -22587,7 +23141,7 @@ typedef struct { #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) -/*! IPGRANTWAIT - Time out wait cycle for IP command grant. +/*! IPGRANTWAIT - Timeout wait cycle for IP command grant. */ #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) @@ -22603,10 +23157,17 @@ typedef struct { #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +/*! AHBBUSWAIT - AHB Bus wait + */ #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root + * Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated + * (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is + * ignored by arbitrator. + */ #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ @@ -22615,23 +23176,20 @@ typedef struct { #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) -/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned - * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or - * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP - * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. - * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. - * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. +/*! CLRAHBBUFOPT - Clear AHB buffer + * 0b0..AHB RX/TX Buffer will not be cleared automatically when FlexSPI returns Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleared automatically when FlexSPI returns Stop mode ACK. */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) -/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. +/*! SAMEDEVICEEN - All external devices are same devices (both in type and size) for A1/A2/B1/B2. * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, - * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be + * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register setting will be * ignored. - * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register setting will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) @@ -22657,7 +23215,7 @@ typedef struct { #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) -/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write). * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ @@ -22671,7 +23229,7 @@ typedef struct { #define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) #define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) -/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. For internal use only. +/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared. */ #define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) @@ -22685,10 +23243,9 @@ typedef struct { #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) -/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat - * of AHB write access, refer for more details about AHB bufferable write. - * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus - * ready after all data is transmitted to External device and AHB command finished. +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. + * 0b0..Disabled. For all AHB write accesses (bufferable or non-bufferable), FlexSPI will return AHB Bus ready + * after all data is transmitted to external device and AHB command finished. * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is * granted by arbitrator and will not wait for AHB command finished. */ @@ -22702,7 +23259,7 @@ typedef struct { #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) -/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. +/*! READADDROPT - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation. * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable. * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB * burst required to meet the alignment requirement. @@ -22777,13 +23334,13 @@ typedef struct { #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) -/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. +/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt. */ #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) -/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. +/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable. */ #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) /*! @} */ @@ -22850,7 +23407,7 @@ typedef struct { #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) -/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. +/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt. */ #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) @@ -22910,7 +23467,7 @@ typedef struct { #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) -/*! REGIONEN - AHB RX Buffer address region funciton enable +/*! REGIONEN - AHB RX Buffer address region function enable */ #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) @@ -22974,9 +23531,9 @@ typedef struct { #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) -/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection - * deassertion and flash device Chip selection assertion. If external flash has a limitation on - * the interval between command sequences, this field should be set accordingly. If there is no +/*! CSINTERVAL - This field is used to set the minimum interval between flash device chip select + * deassertion and flash device chip select assertion. If external flash has a limitation on the + * interval between command sequences, this field should be set accordingly. If there is no * limitation, set this field with value 0x0. */ #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) @@ -23014,26 +23571,33 @@ typedef struct { #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal + * memory after the command sequences finished on FlexSPI interface. If another Read command sequence + * comes before previous programming finished internally, the read data may be wrong. This field + * is used to hold AHB Bus ready for AHB write access to wait the programming finished in + * external device. Then there will be no AHB read command triggered before the programming finished in + * external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI + * interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT + */ #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit - * 0b000..The AWRWAIT unit is 2 ahb clock cycle - * 0b001..The AWRWAIT unit is 8 ahb clock cycle - * 0b010..The AWRWAIT unit is 32 ahb clock cycle - * 0b011..The AWRWAIT unit is 128 ahb clock cycle - * 0b100..The AWRWAIT unit is 512 ahb clock cycle - * 0b101..The AWRWAIT unit is 2048 ahb clock cycle - * 0b110..The AWRWAIT unit is 8192 ahb clock cycle - * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + * 0b000..The AWRWAIT unit is 2 AHB clock cycle + * 0b001..The AWRWAIT unit is 8 AHB clock cycle + * 0b010..The AWRWAIT unit is 32 AHB clock cycle + * 0b011..The AWRWAIT unit is 128 AHB clock cycle + * 0b100..The AWRWAIT unit is 512 AHB clock cycle + * 0b101..The AWRWAIT unit is 2048 AHB clock cycle + * 0b110..The AWRWAIT unit is 8192 AHB clock cycle + * 0b111..The AWRWAIT unit is 32768 AHB clock cycle */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. - * Refer Programmable Sequence Engine for details. */ #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ @@ -23046,11 +23610,12 @@ typedef struct { #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) -/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. - * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write - * burst start address alignment when flash is accessed in individual mode. - * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write - * burst start address alignment when flash is accessed in individual mode. +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB and IP write burst + * start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB/IP + * write burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB/IP + * write burst start address alignment when flash is accessed in individual mode. */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) @@ -23058,7 +23623,7 @@ typedef struct { #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for * memory device on port A, this bit must be set. - * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) @@ -23067,7 +23632,7 @@ typedef struct { #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for * memory device on port B, this bit must be set. - * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) @@ -23142,7 +23707,7 @@ typedef struct { #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) -/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. +/*! RXWMRK - Watermark level is (RXWMRK+1)*64 bits. */ #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ @@ -23182,10 +23747,7 @@ typedef struct { #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) -/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the - * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset - * action is edge triggered, so software need to clear this bit after set this bit (no delay - * limitation). +/*! DLLRESET - DLL reset */ #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) @@ -23236,9 +23798,9 @@ typedef struct { #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). - * 0b00..Triggered by AHB read command (triggered by AHB read). - * 0b01..Triggered by AHB write command (triggered by AHB Write). - * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b00..Triggered by AHB read command. + * 0b01..Triggered by AHB write command. + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD[TRG]). * 0b11..Triggered by suspended command (resumed). */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) @@ -23269,8 +23831,7 @@ typedef struct { #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) -/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be - * cleared when INTR[IPCMDERR] is write-1-clear(w1c). +/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. */ #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) @@ -24146,14 +24707,18 @@ typedef struct { #define GPIO9_BASE (0x4200C000u) /** Peripheral GPIO9 base pointer */ #define GPIO9 ((GPIO_Type *)GPIO9_BASE) +/** Peripheral GPIO10 base address */ +#define GPIO10_BASE (0x401C8000u) +/** Peripheral GPIO10 base pointer */ +#define GPIO10 ((GPIO_Type *)GPIO10_BASE) /** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE } +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE } /** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 } +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10 } /** Interrupt vectors for the GPIO peripheral type */ -#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } -#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn } -#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn } +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO10_Combined_0_31_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO10_Combined_0_31_IRQn } /*! * @} @@ -24175,8 +24740,8 @@ typedef struct { __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ - __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ - __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register, array offset: 0x1C, array step: 0x4 */ __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ } GPT_Type; @@ -24194,134 +24759,168 @@ typedef struct { #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) -/*! EN - * 0b0..GPT is disabled. - * 0b1..GPT is enabled. +/*! EN - GPT Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) -/*! ENMOD - * 0b0..GPT counter will retain its value when it is disabled. - * 0b1..GPT counter value is reset to 0 when it is disabled. +/*! ENMOD - GPT Enable Mode + * 0b0..Restart counting from their frozen values after GPT is enabled (EN=1). + * 0b1..Reset counting from 0 after GPT is enabled (EN=1). */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) -/*! DBGEN - * 0b0..GPT is disabled in debug mode. - * 0b1..GPT is enabled in debug mode. +/*! DBGEN - GPT Debug Mode Enable + * 0b0..Disable in Debug mode + * 0b1..Enable in Debug mode */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) -/*! WAITEN - * 0b0..GPT is disabled in wait mode. - * 0b1..GPT is enabled in wait mode. +/*! WAITEN - GPT Wait Mode Enable + * 0b0..Disable in Wait mode + * 0b1..Enable in Wait mode */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) -/*! DOZEEN - * 0b0..GPT is disabled in doze mode. - * 0b1..GPT is enabled in doze mode. +/*! DOZEEN - GPT Doze Mode Enable + * 0b0..Disable in Doze mode + * 0b1..Enable in Doze mode */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) -/*! STOPEN - * 0b0..GPT is disabled in Stop mode. - * 0b1..GPT is enabled in Stop mode. +/*! STOPEN - GPT Stop Mode Enable + * 0b0..Disable in Stop mode + * 0b1..Enable in Stop mode */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) -/*! CLKSRC +/*! CLKSRC - Clock Source Select * 0b000..No clock * 0b001..Peripheral Clock (ipg_clk) * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) * 0b011..External Clock * 0b100..Low Frequency Reference Clock (ipg_clk_32k) - * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + * 0b101..Oscillator as Reference Clock (ipg_clk_24M) */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) -/*! FRR - * 0b0..Restart mode - * 0b1..Free-Run mode +/*! FRR - Free-Run or Restart Mode + * 0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting. + * 0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0. */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) -/*! EN_24M - * 0b0..24M clock disabled - * 0b1..24M clock enabled +/*! EN_24M - Enable Oscillator Clock Input + * 0b0..Disable + * 0b1..Enable */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) -/*! SWR - * 0b0..GPT is not in reset state - * 0b1..GPT is in reset state +/*! SWR - Software Reset + * 0b0..GPT is not in software reset state + * 0b1..GPT is in software reset state */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) +/*! IM1 - Input Capture Operating Mode for Channel 1 + * 0b00..Capture disabled + * 0b01..Capture on rising edge only + * 0b10..Capture on falling edge only + * 0b11..Capture on both edges + */ #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) -/*! IM2 - * 0b00..capture disabled - * 0b01..capture on rising edge only - * 0b10..capture on falling edge only - * 0b11..capture on both edges +/*! IM2 - Input Capture Operating Mode for Channel 2 + * 0b00..Capture disabled + * 0b01..Capture on rising edge only + * 0b10..Capture on falling edge only + * 0b11..Capture on both edges */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) +/*! OM1 - Output Compare Operating Mode for Channel 1 + * 0b000..Output disabled. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed + * as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). + * "Input clock" here refers to the clock selected by the CLKSRC field of this register. + */ #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) #define GPT_CR_OM2_MASK (0x3800000U) #define GPT_CR_OM2_SHIFT (23U) +/*! OM2 - Output Compare Operating Mode for Channel 2 + * 0b000..Output disabled. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed + * as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). + * "Input clock" here refers to the clock selected by the CLKSRC field of this register. + */ #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) -/*! OM3 - * 0b000..Output disconnected. No response on pin. +/*! OM3 - Output Compare Operating Mode for Channel 3 + * 0b000..Output disabled. No response on pin. * 0b001..Toggle output pin * 0b010..Clear output pin * 0b011..Set output pin - * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + * 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed + * as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). + * "Input clock" here refers to the clock selected by the CLKSRC field of this register. */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) +/*! FO1 - Force Output Compare for Channel 1 + * 0b0..No effect + * 0b1..Trigger the programmed response on the pin + */ #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) #define GPT_CR_FO2_MASK (0x40000000U) #define GPT_CR_FO2_SHIFT (30U) +/*! FO2 - Force Output Compare for Channel 2 + * 0b0..No effect + * 0b1..Trigger the programmed response on the pin + */ #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) -/*! FO3 - * 0b0..Writing a 0 has no effect. - * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. +/*! FO3 - Force Output Compare for Channel 3 + * 0b0..No effect + * 0b1..Trigger the programmed response on the pin */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) /*! @} */ @@ -24331,7 +24930,7 @@ typedef struct { #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) -/*! PRESCALER +/*! PRESCALER - Prescaler divide value * 0b000000000000..Divide by 1 * 0b000000000001..Divide by 2 * 0b111111111111..Divide by 4096 @@ -24340,7 +24939,7 @@ typedef struct { #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) -/*! PRESCALER24M +/*! PRESCALER24M - Prescaler divide value for the oscillator clock * 0b0000..Divide by 1 * 0b0001..Divide by 2 * 0b1111..Divide by 16 @@ -24353,15 +24952,23 @@ typedef struct { #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) +/*! OF1 - Output Compare Flag for Channel 1 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) #define GPT_SR_OF2_MASK (0x2U) #define GPT_SR_OF2_SHIFT (1U) +/*! OF2 - Output Compare Flag for Channel 2 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) -/*! OF3 +/*! OF3 - Output Compare Flag for Channel 3 * 0b0..Compare event has not occurred. * 0b1..Compare event has occurred. */ @@ -24369,11 +24976,15 @@ typedef struct { #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) +/*! IF1 - Input Capture Flag for Channel 1 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) -/*! IF2 +/*! IF2 - Input Capture Flag for Channel 2 * 0b0..Capture event has not occurred. * 0b1..Capture event has occurred. */ @@ -24381,7 +24992,7 @@ typedef struct { #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) -/*! ROV +/*! ROV - Rollover Flag * 0b0..Rollover has not occurred. * 0b1..Rollover has occurred. */ @@ -24393,57 +25004,73 @@ typedef struct { #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) +/*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) #define GPT_IR_OF2IE_MASK (0x2U) #define GPT_IR_OF2IE_SHIFT (1U) +/*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) -/*! OF3IE - * 0b0..Output Compare Channel n interrupt is disabled. - * 0b1..Output Compare Channel n interrupt is enabled. +/*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) +/*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) -/*! IF2IE - * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. - * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. +/*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) -/*! ROVIE - * 0b0..Rollover interrupt is disabled. - * 0b1..Rollover interrupt enabled. +/*! ROVIE - Rollover Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) /*! @} */ -/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @name OCR - GPT Output Compare Register */ /*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) +/*! COMP - Compare Value + */ #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) /*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) -/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @name ICR - GPT Input Capture Register */ /*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) +/*! CAPT - Capture Value + */ #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) /*! @} */ @@ -24455,6 +25082,8 @@ typedef struct { #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) +/*! COUNT - Counter Value + */ #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /*! @} */ @@ -25428,7 +26057,8 @@ typedef struct { __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ - uint8_t RESERVED_1[176]; + __IO uint32_t SW_MUX_CTL_PAD_1[22]; /**< SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register, array offset: 0x65C, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_1[22]; /**< SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register, array offset: 0x6B4, array step: 0x4 */ __IO uint32_t SELECT_INPUT_1[33]; /**< ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register, array offset: 0x70C, array step: 0x4 */ } IOMUXC_Type; @@ -25447,19 +26077,23 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. - * 0b000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc - * 0b001..Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 - * 0b010..Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 - * 0b011..Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1 - * 0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 - * 0b101..Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + * 0b0000..Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + * 0b0001..Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + * 0b0010..Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + * 0b0011..Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + * 0b0100..Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + * 0b0101..Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + * 0b0110..Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + * 0b0111..Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + * 0b1000..Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + * 0b1001..Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO01 of instance: flexio3 */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. - * 0b1..Force input path of pad GPIO_EMC_00 + * 0b1..Force input path of pad GPIO_AD_B0_00 * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) @@ -25555,8 +26189,11 @@ typedef struct { #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. - * 0b0..Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 - * 0b1..Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + * 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + * 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + * 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + * 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + * 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3 */ #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ /*! @} */ @@ -25564,15 +26201,120 @@ typedef struct { /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (154U) +/*! @name SW_MUX_CTL_PAD_1 - SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2 + * 0b101..Select mux mode: ALT5 mux port: GPIO10_IO02 of instance: gpio10 + */ +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK) + +#define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_SPI_B0_00 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD_1 */ +#define IOMUXC_SW_MUX_CTL_PAD_1_COUNT (22U) + +/*! @name SW_PAD_CTL_PAD_1 - SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register */ +/*! @{ */ + +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 [email protected]) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..fast(150MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK) + +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD_1 */ +#define IOMUXC_SW_PAD_CTL_PAD_1_COUNT (22U) + /*! @name SELECT_INPUT_1 - ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register */ /*! @{ */ #define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. - * 0b00..Selecting Pad: GPIO_EMC_33 for Mode: ALT9 - * 0b01..Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9 - * 0b10..Selecting Pad: GPIO_B0_15 for Mode: ALT9 + * 0b00..Selecting Pad: GPIO_SD_B0_00 for Mode: ALT9 + * 0b01..Selecting Pad: GPIO_EMC_39 for Mode: ALT9 + * 0b10..Selecting Pad: GPIO_AD_B0_09 for Mode: ALT9 + * 0b11..Selecting Pad: GPIO_B1_13 for Mode: ALT8 */ #define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ /*! @} */ @@ -28711,7 +29453,7 @@ typedef struct { #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) -/*! KRE +/*! KRE - KRE * 0b00000000..Row is not included in the keypad key press detect. * 0b00000001..Row is included in the keypad key press detect. */ @@ -28719,7 +29461,7 @@ typedef struct { #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) -/*! KCO +/*! KCO - KCO * 0b00000000..Column strobe output is totem pole drive. * 0b00000001..Column strobe output is open drain. */ @@ -28731,7 +29473,7 @@ typedef struct { #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) -/*! KPKD +/*! KPKD - KPKD * 0b0..No key presses detected * 0b1..A key has been depressed */ @@ -28739,7 +29481,7 @@ typedef struct { #define KPP_KPSR_KPKR_MASK (0x2U) #define KPP_KPSR_KPKR_SHIFT (1U) -/*! KPKR +/*! KPKR - KPKR * 0b0..No key release detected * 0b1..All keys have been released */ @@ -28747,7 +29489,7 @@ typedef struct { #define KPP_KPSR_KDSC_MASK (0x4U) #define KPP_KPSR_KDSC_SHIFT (2U) -/*! KDSC +/*! KDSC - KDSC * 0b0..No effect * 0b1..Set bits that clear the keypad depress synchronizer chain */ @@ -28755,7 +29497,7 @@ typedef struct { #define KPP_KPSR_KRSS_MASK (0x8U) #define KPP_KPSR_KRSS_SHIFT (3U) -/*! KRSS +/*! KRSS - KRSS * 0b0..No effect * 0b1..Set bits which sets keypad release synchronizer chain */ @@ -28763,7 +29505,7 @@ typedef struct { #define KPP_KPSR_KDIE_MASK (0x100U) #define KPP_KPSR_KDIE_SHIFT (8U) -/*! KDIE +/*! KDIE - KDIE * 0b0..No interrupt request is generated when KPKD is set. * 0b1..An interrupt request is generated when KPKD is set. */ @@ -28771,7 +29513,7 @@ typedef struct { #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) -/*! KRIE +/*! KRIE - KRIE * 0b0..No interrupt request is generated when KPKR is set. * 0b1..An interrupt request is generated when KPKR is set. */ @@ -28783,7 +29525,7 @@ typedef struct { #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) -/*! KRDD +/*! KRDD - KRDD * 0b00000000..ROWn pin configured as an input. * 0b00000001..ROWn pin configured as an output. */ @@ -28791,7 +29533,7 @@ typedef struct { #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) -/*! KCDD +/*! KCDD - KCDD * 0b00000000..COLn pin is configured as an input. * 0b00000001..COLn pin is configured as an output. */ @@ -28803,10 +29545,14 @@ typedef struct { #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) +/*! KRD - KRD + */ #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) +/*! KCD - KCD + */ #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /*! @} */ @@ -30982,8 +31728,8 @@ typedef struct { #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled + * 0b0..Disabled + * 0b1..Enabled */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) @@ -31309,7 +32055,7 @@ typedef struct { #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty +/*! RXEMPTY - Receive Empty * 0b0..Receive FIFO is not empty * 0b1..Receive FIFO is empty */ @@ -31674,10 +32420,10 @@ typedef struct { #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]). - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address - * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag - * is clear, returns received data and clears the Receive Data flag (MSR[RDF]). + * 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag. + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is set, returns the Address + * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid + * flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]). */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) @@ -31807,7 +32553,7 @@ typedef struct { #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty +/*! RXEMPTY - Receive Empty * 0b0..The Receive Data Register is not empty * 0b1..The Receive Data Register is empty */ @@ -31976,7 +32722,8 @@ typedef struct { #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable - * 0b0..LPSPI module is disabled in debug mode + * 0b0..LPSPI module is disabled when the CPU is halted. When LPSPI is disabled, the PCS will be negated once the + * transmit FIFO is empty regardless of the state of TCR register. * 0b1..LPSPI module is enabled in debug mode */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) @@ -37685,7 +38432,7 @@ typedef struct { #define PWM_CTRL2_WAITEN_MASK (0x4000U) #define PWM_CTRL2_WAITEN_SHIFT (14U) -/*! WAITEN - WAIT Enable +/*! WAITEN - Wait Enable */ #define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) @@ -44017,7 +44764,7 @@ typedef struct { #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) -/*! USrc_Sel +/*! USrc_Sel - USrc_Sel * 0b00..No embedded U channel * 0b01..U channel from SPDIF receive block (CD mode) * 0b10..Reserved @@ -44027,7 +44774,7 @@ typedef struct { #define SPDIF_SCR_TXSEL_MASK (0x1CU) #define SPDIF_SCR_TXSEL_SHIFT (2U) -/*! TxSel +/*! TxSel - TxSel * 0b000..Off and output 0 * 0b001..Feed-through SPDIFIN * 0b101..Tx Normal operation @@ -44036,23 +44783,35 @@ typedef struct { #define SPDIF_SCR_VALCTRL_MASK (0x20U) #define SPDIF_SCR_VALCTRL_SHIFT (5U) -/*! ValCtrl +/*! ValCtrl - ValCtrl * 0b0..Outgoing Validity always set * 0b1..Outgoing Validity always clear */ #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_INPUTSRCSEL_MASK (0xC0U) +#define SPDIF_SCR_INPUTSRCSEL_SHIFT (6U) +/*! InputSrcSel - InputSrcSel + * 0b00..SPDIF_IN + * 0b01-0b11..None + */ +#define SPDIF_SCR_INPUTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK) + #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +/*! DMA_TX_En - DMA_TX_En + */ #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +/*! DMA_Rx_En - DMA_Rx_En + */ #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) -/*! TxFIFO_Ctrl +/*! TxFIFO_Ctrl - TxFIFO_Ctrl * 0b00..Send out digital zero on SPDIF Tx * 0b01..Tx Normal operation * 0b10..Reset to 1 sample remaining @@ -44062,15 +44821,19 @@ typedef struct { #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +/*! soft_reset - soft_reset + */ #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) #define SPDIF_SCR_LOW_POWER_MASK (0x2000U) #define SPDIF_SCR_LOW_POWER_SHIFT (13U) +/*! LOW_POWER - LOW_POWER + */ #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) -/*! TxFIFOEmpty_Sel +/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs @@ -44080,7 +44843,7 @@ typedef struct { #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) -/*! TxAutoSync +/*! TxAutoSync - TxAutoSync * 0b0..Tx FIFO auto sync off * 0b1..Tx FIFO auto sync on */ @@ -44088,7 +44851,7 @@ typedef struct { #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) -/*! RxAutoSync +/*! RxAutoSync - RxAutoSync * 0b0..Rx FIFO auto sync off * 0b1..RxFIFO auto sync on */ @@ -44096,7 +44859,7 @@ typedef struct { #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) -/*! RxFIFOFull_Sel +/*! RxFIFOFull_Sel - RxFIFOFull_Sel * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs @@ -44106,7 +44869,7 @@ typedef struct { #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) -/*! RxFIFO_Rst +/*! RxFIFO_Rst - RxFIFO_Rst * 0b0..Normal operation * 0b1..Reset register to 1 sample remaining */ @@ -44114,7 +44877,7 @@ typedef struct { #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) -/*! RxFIFO_Off_On +/*! RxFIFO_Off_On - RxFIFO_Off_On * 0b0..SPDIF Rx FIFO is on * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface */ @@ -44122,7 +44885,7 @@ typedef struct { #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) -/*! RxFIFO_Ctrl +/*! RxFIFO_Ctrl - RxFIFO_Ctrl * 0b0..Normal operation * 0b1..Always read zero from Rx data register */ @@ -44134,7 +44897,7 @@ typedef struct { #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) -/*! USyncMode +/*! USyncMode - USyncMode * 0b0..Non-CD data * 0b1..CD user channel subcode */ @@ -44146,7 +44909,7 @@ typedef struct { #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) -/*! GainSel +/*! GainSel - GainSel * 0b000..24*(2**10) * 0b001..16*(2**10) * 0b010..12*(2**10) @@ -44159,11 +44922,13 @@ typedef struct { #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) +/*! LOCK - LOCK + */ #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) -/*! ClkSrc_Sel +/*! ClkSrc_Sel - ClkSrc_Sel * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK @@ -44179,74 +44944,110 @@ typedef struct { #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +/*! RxFIFOFul - RxFIFOFul + */ #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) #define SPDIF_SIE_TXEM_MASK (0x2U) #define SPDIF_SIE_TXEM_SHIFT (1U) +/*! TxEm - TxEm + */ #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) #define SPDIF_SIE_LOCKLOSS_MASK (0x4U) #define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) #define SPDIF_SIE_UQERR_MASK (0x20U) #define SPDIF_SIE_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) #define SPDIF_SIE_UQSYNC_MASK (0x40U) #define SPDIF_SIE_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) #define SPDIF_SIE_QRXOV_MASK (0x80U) #define SPDIF_SIE_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) #define SPDIF_SIE_QRXFUL_MASK (0x100U) #define SPDIF_SIE_QRXFUL_SHIFT (8U) +/*! QRxFul - QRxFul + */ #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) #define SPDIF_SIE_URXOV_MASK (0x200U) #define SPDIF_SIE_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) #define SPDIF_SIE_URXFUL_MASK (0x400U) #define SPDIF_SIE_URXFUL_SHIFT (10U) +/*! URxFul - URxFul + */ #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) #define SPDIF_SIE_BITERR_MASK (0x4000U) #define SPDIF_SIE_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) #define SPDIF_SIE_SYMERR_MASK (0x8000U) #define SPDIF_SIE_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) #define SPDIF_SIE_CNEW_MASK (0x20000U) #define SPDIF_SIE_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) #define SPDIF_SIE_TXRESYN_MASK (0x40000U) #define SPDIF_SIE_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) #define SPDIF_SIE_TXUNOV_MASK (0x80000U) #define SPDIF_SIE_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) /*! @} */ @@ -44255,58 +45056,86 @@ typedef struct { #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) #define SPDIF_SIC_UQERR_MASK (0x20U) #define SPDIF_SIC_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) #define SPDIF_SIC_UQSYNC_MASK (0x40U) #define SPDIF_SIC_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) #define SPDIF_SIC_QRXOV_MASK (0x80U) #define SPDIF_SIC_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) #define SPDIF_SIC_URXOV_MASK (0x200U) #define SPDIF_SIC_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) #define SPDIF_SIC_BITERR_MASK (0x4000U) #define SPDIF_SIC_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) #define SPDIF_SIC_SYMERR_MASK (0x8000U) #define SPDIF_SIC_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) #define SPDIF_SIC_CNEW_MASK (0x20000U) #define SPDIF_SIC_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) #define SPDIF_SIC_TXRESYN_MASK (0x40000U) #define SPDIF_SIC_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) #define SPDIF_SIC_TXUNOV_MASK (0x80000U) #define SPDIF_SIC_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) /*! @} */ @@ -44315,74 +45144,110 @@ typedef struct { #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +/*! RxFIFOFul - RxFIFOFul + */ #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) #define SPDIF_SIS_TXEM_MASK (0x2U) #define SPDIF_SIS_TXEM_SHIFT (1U) +/*! TxEm - TxEm + */ #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) #define SPDIF_SIS_LOCKLOSS_MASK (0x4U) #define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) #define SPDIF_SIS_UQERR_MASK (0x20U) #define SPDIF_SIS_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) #define SPDIF_SIS_UQSYNC_MASK (0x40U) #define SPDIF_SIS_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) #define SPDIF_SIS_QRXOV_MASK (0x80U) #define SPDIF_SIS_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) #define SPDIF_SIS_QRXFUL_MASK (0x100U) #define SPDIF_SIS_QRXFUL_SHIFT (8U) +/*! QRxFul - QRxFul + */ #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) #define SPDIF_SIS_URXOV_MASK (0x200U) #define SPDIF_SIS_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) #define SPDIF_SIS_URXFUL_MASK (0x400U) #define SPDIF_SIS_URXFUL_SHIFT (10U) +/*! URxFul - URxFul + */ #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) #define SPDIF_SIS_BITERR_MASK (0x4000U) #define SPDIF_SIS_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) #define SPDIF_SIS_SYMERR_MASK (0x8000U) #define SPDIF_SIS_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) #define SPDIF_SIS_CNEW_MASK (0x20000U) #define SPDIF_SIS_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) #define SPDIF_SIS_TXRESYN_MASK (0x40000U) #define SPDIF_SIS_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) #define SPDIF_SIS_TXUNOV_MASK (0x80000U) #define SPDIF_SIS_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) /*! @} */ @@ -44391,6 +45256,8 @@ typedef struct { #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +/*! RxDataLeft - RxDataLeft + */ #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) /*! @} */ @@ -44399,6 +45266,8 @@ typedef struct { #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +/*! RxDataRight - RxDataRight + */ #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) /*! @} */ @@ -44407,6 +45276,8 @@ typedef struct { #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +/*! RxCChannel_h - RxCChannel_h + */ #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) /*! @} */ @@ -44415,6 +45286,8 @@ typedef struct { #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +/*! RxCChannel_l - RxCChannel_l + */ #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) /*! @} */ @@ -44423,6 +45296,8 @@ typedef struct { #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +/*! RxUChannel - RxUChannel + */ #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) /*! @} */ @@ -44431,6 +45306,8 @@ typedef struct { #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +/*! RxQChannel - RxQChannel + */ #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) /*! @} */ @@ -44439,6 +45316,8 @@ typedef struct { #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) +/*! TxDataLeft - TxDataLeft + */ #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) /*! @} */ @@ -44447,6 +45326,8 @@ typedef struct { #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +/*! TxDataRight - TxDataRight + */ #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) /*! @} */ @@ -44455,6 +45336,8 @@ typedef struct { #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +/*! TxCChannelCons_h - TxCChannelCons_h + */ #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) /*! @} */ @@ -44463,6 +45346,8 @@ typedef struct { #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +/*! TxCChannelCons_l - TxCChannelCons_l + */ #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) /*! @} */ @@ -44471,6 +45356,8 @@ typedef struct { #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +/*! FreqMeas - FreqMeas + */ #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) /*! @} */ @@ -44479,7 +45366,7 @@ typedef struct { #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) -/*! TxClk_DF +/*! TxClk_DF - TxClk_DF * 0b0000000..divider factor is 1 * 0b0000001..divider factor is 2 * 0b1111111..divider factor is 128 @@ -44488,7 +45375,7 @@ typedef struct { #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) -/*! tx_all_clk_en +/*! tx_all_clk_en - tx_all_clk_en * 0b0..disable transfer clock. * 0b1..enable transfer clock. */ @@ -44496,20 +45383,17 @@ typedef struct { #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) -/*! TxClk_Source - * 0b000..XTALOSC input (XTALOSC clock) - * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) - * 0b010..tx_clk1 (from SAI1) - * 0b011..tx_clk2 SPDIF_EXT_CLK, from pads - * 0b100..tx_clk3 (from SAI2) +/*! TxClk_Source - TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.) + * 0b011..SPDIF_EXT_CLK, from pads * 0b101..ipg_clk input (frequency divided) - * 0b110..tx_clk4 (from SAI3) */ #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) -/*! SYSCLK_DF +/*! SYSCLK_DF - SYSCLK_DF * 0b000000000..no clock signal * 0b000000001..divider factor is 2 * 0b111111111..divider factor is 512 @@ -44981,6 +45865,12 @@ typedef struct { #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +/*! MEASURE_FREQ + * 0b0000000000000000..Defines a single measurement with no repeat. + * 0b0000000000000001..Updates the temperature value at a RTC clock rate. + * 0b0000000000000010..Updates the temperature value at a RTC/2 clock rate. + * 0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + */ #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) /*! @} */ @@ -44989,6 +45879,12 @@ typedef struct { #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +/*! MEASURE_FREQ + * 0b0000000000000000..Defines a single measurement with no repeat. + * 0b0000000000000001..Updates the temperature value at a RTC clock rate. + * 0b0000000000000010..Updates the temperature value at a RTC/2 clock rate. + * 0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + */ #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) /*! @} */ @@ -44997,6 +45893,12 @@ typedef struct { #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +/*! MEASURE_FREQ + * 0b0000000000000000..Defines a single measurement with no repeat. + * 0b0000000000000001..Updates the temperature value at a RTC clock rate. + * 0b0000000000000010..Updates the temperature value at a RTC/2 clock rate. + * 0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + */ #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) /*! @} */ @@ -45005,6 +45907,12 @@ typedef struct { #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +/*! MEASURE_FREQ + * 0b0000000000000000..Defines a single measurement with no repeat. + * 0b0000000000000001..Updates the temperature value at a RTC clock rate. + * 0b0000000000000010..Updates the temperature value at a RTC/2 clock rate. + * 0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + */ #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) /*! @} */ @@ -47705,6 +48613,7 @@ typedef struct { * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) @@ -48822,7 +49731,7 @@ typedef struct { __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ uint8_t RESERVED_0[12]; - __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */ __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ @@ -50763,7 +51672,7 @@ typedef struct { __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[84]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ - __IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */ + __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ } USDHC_Type; @@ -51031,7 +51940,7 @@ typedef struct { #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) -/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and eMMC HS200 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ @@ -51356,7 +52265,7 @@ typedef struct { #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) -/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) +/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode) * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. */ @@ -51364,7 +52273,7 @@ typedef struct { #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) -/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) +/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */ #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) @@ -51440,7 +52349,7 @@ typedef struct { #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) -/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) +/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */ #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) @@ -52052,7 +52961,7 @@ typedef struct { #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) -/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) +/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) * 0b1..Execute tuning * 0b0..Not tuned or tuning completed */ @@ -52068,7 +52977,7 @@ typedef struct { #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) -/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) +/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and eMMC HS200 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ @@ -52076,7 +52985,7 @@ typedef struct { #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) -/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) +/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ @@ -52421,7 +53330,7 @@ typedef struct { #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ -/*! @name MMC_BOOT - MMC Boot */ +/*! @name MMC_BOOT - eMMC Boot */ /*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) @@ -52672,7 +53581,7 @@ typedef struct { #define WDOG_WCR_SRE_MASK (0x40U) #define WDOG_WCR_SRE_SHIFT (6U) -/*! SRE - software reset extension, an option way to generate software reset +/*! SRE - Software Reset Extension, an optional way to generate software reset * 0b0..using original way to generate software reset (default) * 0b1..using new way to generate software reset. */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.xml b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.xml index f7b24dd493..e3f8163c13 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.xml +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.xml @@ -5,7 +5,7 @@ <version>1.0</version> <description>MIMXRT1062DVL6A</description> <licenseText> -Copyright 2016-2021 NXP +Copyright 2016-2022 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -1707,7 +1707,7 @@ SPDX-License-Identifier: BSD-3-Clause <dim>4</dim> <dimIncrement>0x10</dimIncrement> <name>TIMER[%s]</name> - <description>no description available</description> + <description>Timer array.</description> <addressOffset>0x100</addressOffset> <register> <name>LDVAL</name> @@ -1821,6 +1821,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TIF</name> @@ -10885,7 +10886,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>SRE</name> - <description>software reset extension, an option way to generate software reset</description> + <description>Software Reset Extension, an optional way to generate software reset</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -11213,12 +11214,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>STOP_0</name> + <name>DIS</name> <description>Watchdog disabled in chip stop mode.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>STOP_1</name> + <name>EN</name> <description>Watchdog enabled in chip stop mode.</description> <value>0x1</value> </enumeratedValue> @@ -11232,12 +11233,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WAIT_0</name> + <name>DIS</name> <description>Watchdog disabled in chip wait mode.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WAIT_1</name> + <name>EN</name> <description>Watchdog enabled in chip wait mode.</description> <value>0x1</value> </enumeratedValue> @@ -11251,12 +11252,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DBG_0</name> + <name>DIS</name> <description>Watchdog disabled in chip debug mode.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DBG_1</name> + <name>EN</name> <description>Watchdog enabled in chip debug mode.</description> <value>0x1</value> </enumeratedValue> @@ -11270,22 +11271,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TST_0</name> + <name>DIS</name> <description>Watchdog test mode disabled.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TST_1</name> + <name>EN</name> <description>Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TST_2</name> + <name>EN_LOW</name> <description>Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>TST_3</name> + <name>EN_HIGH</name> <description>Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].</description> <value>0x3</value> </enumeratedValue> @@ -11299,12 +11300,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>UPDATE_0</name> + <name>DIS</name> <description>Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>UPDATE_1</name> + <name>EN</name> <description>Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.</description> <value>0x1</value> </enumeratedValue> @@ -11318,12 +11319,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>INT_0</name> + <name>DIS</name> <description>Watchdog interrupts are disabled. Watchdog resets are not delayed.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>INT_1</name> + <name>EN</name> <description>Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.</description> <value>0x1</value> </enumeratedValue> @@ -11337,12 +11338,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EN_0</name> + <name>DIS</name> <description>Watchdog disabled.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EN_1</name> + <name>EN</name> <description>Watchdog enabled.</description> <value>0x1</value> </enumeratedValue> @@ -11363,12 +11364,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>RCS_0</name> + <name>RECONFIG</name> <description>Reconfiguring WDOG.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RCS_1</name> + <name>SUCCESS</name> <description>Reconfiguration is successful.</description> <value>0x1</value> </enumeratedValue> @@ -11382,12 +11383,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>ULK_0</name> + <name>LOCK</name> <description>WDOG is locked.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ULK_1</name> + <name>UNLOCK</name> <description>WDOG is unlocked.</description> <value>0x1</value> </enumeratedValue> @@ -11401,12 +11402,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>PRES_0</name> + <name>DIS</name> <description>256 prescaler disabled.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>PRES_1</name> + <name>EN</name> <description>256 prescaler enabled.</description> <value>0x1</value> </enumeratedValue> @@ -11420,12 +11421,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CMD32EN_0</name> + <name>DIS</name> <description>Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CMD32EN_1</name> + <name>EN</name> <description>Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.</description> <value>0x1</value> </enumeratedValue> @@ -11440,12 +11441,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>FLG_0</name> + <name>NO</name> <description>No interrupt occurred.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>FLG_1</name> + <name>YES</name> <description>An interrupt occurred.</description> <value>0x1</value> </enumeratedValue> @@ -11459,12 +11460,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WIN_0</name> + <name>DIS</name> <description>Window mode disabled.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WIN_1</name> + <name>EN</name> <description>Window mode enabled.</description> <value>0x1</value> </enumeratedValue> @@ -11583,6 +11584,56 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>ADCH_0</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_1</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_2</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_3</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_4</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_5</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_6</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_7</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x7</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_8</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x8</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_9</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x9</value> + </enumeratedValue> + <enumeratedValue> <name>ADCH_16</name> <description>External channel selection from ADC_ETC</description> <value>0x10</value> @@ -11640,6 +11691,56 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> + <name>ADCH_0</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_1</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_2</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_3</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_4</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_5</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_6</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_7</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x7</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_8</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x8</value> + </enumeratedValue> + <enumeratedValue> + <name>ADCH_9</name> + <description>External channels 0 to 15 See External Signals for more information</description> + <value>0x9</value> + </enumeratedValue> + <enumeratedValue> <name>ADCH_16</name> <description>External channel selection from ADC_ETC</description> <value>0x10</value> @@ -16416,6 +16517,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>modify</modifiedWriteValues> <fields> <field> <name>MON_COUNTER</name> @@ -17810,7 +17912,7 @@ SPDX-License-Identifier: BSD-3-Clause </enumeratedValue> <enumeratedValue> <name>ENABLE_1</name> - <description>Soread spectrum modulation enabled</description> + <description>Spread spectrum modulation enabled</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -29825,6 +29927,28 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>MEASURE_FREQ_0</name> + <description>Defines a single measurement with no repeat.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_1</name> + <description>Updates the temperature value at a RTC clock rate.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_2</name> + <description>Updates the temperature value at a RTC/2 clock rate.</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_65535</name> + <description>Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.</description> + <value>0xFFFF</value> + </enumeratedValue> + </enumeratedValues> </field> </fields> </register> @@ -29843,6 +29967,28 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>MEASURE_FREQ_0</name> + <description>Defines a single measurement with no repeat.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_1</name> + <description>Updates the temperature value at a RTC clock rate.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_2</name> + <description>Updates the temperature value at a RTC/2 clock rate.</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_65535</name> + <description>Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.</description> + <value>0xFFFF</value> + </enumeratedValue> + </enumeratedValues> </field> </fields> </register> @@ -29861,6 +30007,28 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>MEASURE_FREQ_0</name> + <description>Defines a single measurement with no repeat.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_1</name> + <description>Updates the temperature value at a RTC clock rate.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_2</name> + <description>Updates the temperature value at a RTC/2 clock rate.</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_65535</name> + <description>Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.</description> + <value>0xFFFF</value> + </enumeratedValue> + </enumeratedValues> </field> </fields> </register> @@ -29879,6 +30047,28 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>MEASURE_FREQ_0</name> + <description>Defines a single measurement with no repeat.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_1</name> + <description>Updates the temperature value at a RTC clock rate.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_2</name> + <description>Updates the temperature value at a RTC/2 clock rate.</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>MEASURE_FREQ_65535</name> + <description>Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.</description> + <value>0xFFFF</value> + </enumeratedValue> + </enumeratedValues> </field> </fields> </register> @@ -41652,6 +41842,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>INT0</name> @@ -42303,6 +42494,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>ERR0</name> @@ -46306,47 +46498,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -47008,47 +47200,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -47710,47 +47902,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -48412,47 +48604,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -49114,47 +49306,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -49816,47 +50008,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -50518,47 +50710,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -51220,47 +51412,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -51922,47 +52114,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -52624,47 +52816,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -53326,47 +53518,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -54028,47 +54220,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -54730,47 +54922,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -55432,47 +55624,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -56134,47 +56326,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -56836,47 +57028,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -57538,47 +57730,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -58240,47 +58432,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -58942,47 +59134,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -59644,47 +59836,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -60346,47 +60538,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -61048,47 +61240,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -61750,47 +61942,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -62452,47 +62644,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -63154,47 +63346,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -63856,47 +64048,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -64558,47 +64750,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -65260,47 +65452,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -65962,47 +66154,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -66664,47 +66856,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -67366,47 +67558,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -68068,47 +68260,47 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_1</name> <description>Value defines address range used to set up circular data queue</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_2</name> <description>Value defines address range used to set up circular data queue</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_3</name> <description>Value defines address range used to set up circular data queue</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_4</name> <description>Value defines address range used to set up circular data queue</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_5</name> <description>Value defines address range used to set up circular data queue</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_6</name> <description>Value defines address range used to set up circular data queue</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_7</name> <description>Value defines address range used to set up circular data queue</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_8</name> <description>Value defines address range used to set up circular data queue</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>ENABLED</name> + <name>ENABLED_9</name> <description>Value defines address range used to set up circular data queue</description> <value>0x9</value> </enumeratedValue> @@ -74396,6 +74588,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>LRF_PLL</name> @@ -75907,7 +76100,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>CG10</name> - <description>sim_axbs_p_clk_enable</description> + <description>sim_per clock (sim_per_clk_enable) sim_axbs_p_clk_enable</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> @@ -78942,6 +79135,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SSF</name> @@ -78961,6 +79155,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SEF</name> @@ -78980,6 +79175,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TSF</name> @@ -79272,13 +79468,18 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> + <name>value01</name> + <description>Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on the configured shift edge when timer in stop condition</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> <name>value10</name> - <description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0</description> + <description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0, receiver/match store will also store receive data on the configured shift edge when timer in stop condition</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> <name>value11</name> - <description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1</description> + <description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1, receiver/match store will also store receive data on the configured shift edge when timer in stop condition</description> <value>0x3</value> </enumeratedValue> </enumeratedValues> @@ -80097,6 +80298,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SSF</name> @@ -80116,6 +80318,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SEF</name> @@ -80135,6 +80338,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TSF</name> @@ -80427,13 +80631,18 @@ SPDX-License-Identifier: BSD-3-Clause <value>0</value> </enumeratedValue> <enumeratedValue> + <name>value01</name> + <description>Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on the configured shift edge when timer in stop condition</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> <name>value10</name> - <description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0</description> + <description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0, receiver/match store will also store receive data on the configured shift edge when timer in stop condition</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> <name>value11</name> - <description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1</description> + <description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1, receiver/match store will also store receive data on the configured shift edge when timer in stop condition</description> <value>0x3</value> </enumeratedValue> </enumeratedValues> @@ -82118,6 +82327,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>ISR</name> @@ -82280,6 +82490,21 @@ SPDX-License-Identifier: BSD-3-Clause </interrupt> </peripheral> <peripheral derivedFrom="GPIO1"> + <name>GPIO10</name> + <description>GPIO</description> + <groupName>GPIO</groupName> + <baseAddress>0x401C8000</baseAddress> + <addressBlock> + <offset>0</offset> + <size>0x90</size> + <usage>registers</usage> + </addressBlock> + <interrupt> + <name>GPIO10_Combined_0_31</name> + <value>71</value> + </interrupt> + </peripheral> + <peripheral derivedFrom="GPIO1"> <name>GPIO6</name> <description>GPIO</description> <groupName>GPIO</groupName> @@ -85387,6 +85612,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>BUF63TO32I</name> @@ -85406,6 +85632,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>BUF0I</name> @@ -85959,7 +86186,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_CS</name> + <name>MB0_16B_CS_L</name> <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x80</addressOffset> @@ -86034,7 +86261,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_CS</name> + <name>MB0_32B_CS_L</name> <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x80</addressOffset> @@ -86109,7 +86336,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_CS</name> + <name>MB0_64B_CS_L</name> <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x80</addressOffset> @@ -86292,7 +86519,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_ID</name> + <name>MB0_16B_ID_L</name> <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x84</addressOffset> @@ -86325,7 +86552,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_ID</name> + <name>MB0_32B_ID_L</name> <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x84</addressOffset> @@ -86358,7 +86585,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_ID</name> + <name>MB0_64B_ID_L</name> <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x84</addressOffset> @@ -86424,7 +86651,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_WORD0</name> + <name>MB0_16B_WORD0_L</name> <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x88</addressOffset> @@ -86464,7 +86691,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD0</name> + <name>MB0_32B_WORD0_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x88</addressOffset> @@ -86504,7 +86731,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD0</name> + <name>MB0_64B_WORD0_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x88</addressOffset> @@ -86624,7 +86851,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_WORD1</name> + <name>MB0_16B_WORD1_L</name> <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x8C</addressOffset> @@ -86664,7 +86891,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD1</name> + <name>MB0_32B_WORD1_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x8C</addressOffset> @@ -86704,7 +86931,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD1</name> + <name>MB0_64B_WORD1_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x8C</addressOffset> @@ -86899,7 +87126,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_WORD2</name> + <name>MB0_16B_WORD2_L</name> <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x90</addressOffset> @@ -86939,7 +87166,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD2</name> + <name>MB0_32B_WORD2_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x90</addressOffset> @@ -86979,7 +87206,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD2</name> + <name>MB0_64B_WORD2_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x90</addressOffset> @@ -87127,7 +87354,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_16B_WORD3</name> + <name>MB0_16B_WORD3_L</name> <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x94</addressOffset> @@ -87167,7 +87394,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD3</name> + <name>MB0_32B_WORD3_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x94</addressOffset> @@ -87207,7 +87434,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD3</name> + <name>MB0_64B_WORD3_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x94</addressOffset> @@ -87280,7 +87507,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD4</name> + <name>MB0_32B_WORD4_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x98</addressOffset> @@ -87320,7 +87547,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD4</name> + <name>MB0_64B_WORD4_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x98</addressOffset> @@ -87360,7 +87587,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_CS</name> + <name>MB1_16B_CS_L</name> <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x98</addressOffset> @@ -87515,7 +87742,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD5</name> + <name>MB0_32B_WORD5_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x9C</addressOffset> @@ -87555,7 +87782,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD5</name> + <name>MB0_64B_WORD5_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x9C</addressOffset> @@ -87595,7 +87822,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_ID</name> + <name>MB1_16B_ID_L</name> <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x9C</addressOffset> @@ -87783,7 +88010,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD6</name> + <name>MB0_32B_WORD6_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA0</addressOffset> @@ -87823,7 +88050,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD6</name> + <name>MB0_64B_WORD6_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA0</addressOffset> @@ -87863,7 +88090,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_WORD0</name> + <name>MB1_16B_WORD0_L</name> <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA0</addressOffset> @@ -88011,7 +88238,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_32B_WORD7</name> + <name>MB0_32B_WORD7_L</name> <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA4</addressOffset> @@ -88051,7 +88278,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD7</name> + <name>MB0_64B_WORD7_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA4</addressOffset> @@ -88091,7 +88318,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_WORD1</name> + <name>MB1_16B_WORD1_L</name> <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA4</addressOffset> @@ -88164,7 +88391,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD8</name> + <name>MB0_64B_WORD8_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA8</addressOffset> @@ -88204,7 +88431,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_WORD2</name> + <name>MB1_16B_WORD2_L</name> <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA8</addressOffset> @@ -88244,7 +88471,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_CS</name> + <name>MB1_32B_CS_L</name> <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xA8</addressOffset> @@ -88399,7 +88626,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD9</name> + <name>MB0_64B_WORD9_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xAC</addressOffset> @@ -88439,7 +88666,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_16B_WORD3</name> + <name>MB1_16B_WORD3_L</name> <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xAC</addressOffset> @@ -88479,7 +88706,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_ID</name> + <name>MB1_32B_ID_L</name> <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xAC</addressOffset> @@ -88667,7 +88894,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD10</name> + <name>MB0_64B_WORD10_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB0</addressOffset> @@ -88707,7 +88934,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD0</name> + <name>MB1_32B_WORD0_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB0</addressOffset> @@ -88747,7 +88974,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_CS</name> + <name>MB2_16B_CS_L</name> <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB0</addressOffset> @@ -88930,7 +89157,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD11</name> + <name>MB0_64B_WORD11_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB4</addressOffset> @@ -88970,7 +89197,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD1</name> + <name>MB1_32B_WORD1_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB4</addressOffset> @@ -89010,7 +89237,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_ID</name> + <name>MB2_16B_ID_L</name> <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB4</addressOffset> @@ -89076,7 +89303,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD12</name> + <name>MB0_64B_WORD12_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB8</addressOffset> @@ -89116,7 +89343,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD2</name> + <name>MB1_32B_WORD2_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB8</addressOffset> @@ -89156,7 +89383,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_WORD0</name> + <name>MB2_16B_WORD0_L</name> <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xB8</addressOffset> @@ -89276,7 +89503,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD13</name> + <name>MB0_64B_WORD13_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xBC</addressOffset> @@ -89316,7 +89543,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD3</name> + <name>MB1_32B_WORD3_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xBC</addressOffset> @@ -89356,7 +89583,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_WORD1</name> + <name>MB2_16B_WORD1_L</name> <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xBC</addressOffset> @@ -89551,7 +89778,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD14</name> + <name>MB0_64B_WORD14_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC0</addressOffset> @@ -89591,7 +89818,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD4</name> + <name>MB1_32B_WORD4_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC0</addressOffset> @@ -89631,7 +89858,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_WORD2</name> + <name>MB2_16B_WORD2_L</name> <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC0</addressOffset> @@ -89779,7 +90006,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB0_64B_WORD15</name> + <name>MB0_64B_WORD15_L</name> <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC4</addressOffset> @@ -89819,7 +90046,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD5</name> + <name>MB1_32B_WORD5_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC4</addressOffset> @@ -89859,7 +90086,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_16B_WORD3</name> + <name>MB2_16B_WORD3_L</name> <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC4</addressOffset> @@ -89932,7 +90159,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD6</name> + <name>MB1_32B_WORD6_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC8</addressOffset> @@ -89972,7 +90199,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_CS</name> + <name>MB1_64B_CS_L</name> <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC8</addressOffset> @@ -90047,7 +90274,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_CS</name> + <name>MB3_16B_CS_L</name> <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xC8</addressOffset> @@ -90202,7 +90429,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_32B_WORD7</name> + <name>MB1_32B_WORD7_L</name> <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xCC</addressOffset> @@ -90242,7 +90469,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_ID</name> + <name>MB1_64B_ID_L</name> <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xCC</addressOffset> @@ -90275,7 +90502,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_ID</name> + <name>MB3_16B_ID_L</name> <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xCC</addressOffset> @@ -90463,7 +90690,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD0</name> + <name>MB1_64B_WORD0_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD0</addressOffset> @@ -90503,7 +90730,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_CS</name> + <name>MB2_32B_CS_L</name> <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD0</addressOffset> @@ -90578,7 +90805,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_WORD0</name> + <name>MB3_16B_WORD0_L</name> <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD0</addressOffset> @@ -90726,7 +90953,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD1</name> + <name>MB1_64B_WORD1_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD4</addressOffset> @@ -90766,7 +90993,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_ID</name> + <name>MB2_32B_ID_L</name> <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD4</addressOffset> @@ -90799,7 +91026,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_WORD1</name> + <name>MB3_16B_WORD1_L</name> <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD4</addressOffset> @@ -90872,7 +91099,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD2</name> + <name>MB1_64B_WORD2_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD8</addressOffset> @@ -90912,7 +91139,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD0</name> + <name>MB2_32B_WORD0_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD8</addressOffset> @@ -90952,7 +91179,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_WORD2</name> + <name>MB3_16B_WORD2_L</name> <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xD8</addressOffset> @@ -91072,7 +91299,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD3</name> + <name>MB1_64B_WORD3_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xDC</addressOffset> @@ -91112,7 +91339,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD1</name> + <name>MB2_32B_WORD1_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xDC</addressOffset> @@ -91152,7 +91379,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_16B_WORD3</name> + <name>MB3_16B_WORD3_L</name> <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xDC</addressOffset> @@ -91347,7 +91574,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD4</name> + <name>MB1_64B_WORD4_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE0</addressOffset> @@ -91387,7 +91614,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD2</name> + <name>MB2_32B_WORD2_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE0</addressOffset> @@ -91427,7 +91654,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_CS</name> + <name>MB4_16B_CS_L</name> <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE0</addressOffset> @@ -91610,7 +91837,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD5</name> + <name>MB1_64B_WORD5_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE4</addressOffset> @@ -91650,7 +91877,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD3</name> + <name>MB2_32B_WORD3_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE4</addressOffset> @@ -91690,7 +91917,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_ID</name> + <name>MB4_16B_ID_L</name> <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE4</addressOffset> @@ -91756,7 +91983,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD6</name> + <name>MB1_64B_WORD6_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE8</addressOffset> @@ -91796,7 +92023,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD4</name> + <name>MB2_32B_WORD4_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE8</addressOffset> @@ -91836,7 +92063,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_WORD0</name> + <name>MB4_16B_WORD0_L</name> <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xE8</addressOffset> @@ -91956,7 +92183,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD7</name> + <name>MB1_64B_WORD7_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xEC</addressOffset> @@ -91996,7 +92223,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD5</name> + <name>MB2_32B_WORD5_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xEC</addressOffset> @@ -92036,7 +92263,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_WORD1</name> + <name>MB4_16B_WORD1_L</name> <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xEC</addressOffset> @@ -92231,7 +92458,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD8</name> + <name>MB1_64B_WORD8_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF0</addressOffset> @@ -92271,7 +92498,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD6</name> + <name>MB2_32B_WORD6_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF0</addressOffset> @@ -92311,7 +92538,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_WORD2</name> + <name>MB4_16B_WORD2_L</name> <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF0</addressOffset> @@ -92459,7 +92686,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD9</name> + <name>MB1_64B_WORD9_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF4</addressOffset> @@ -92499,7 +92726,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_32B_WORD7</name> + <name>MB2_32B_WORD7_L</name> <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF4</addressOffset> @@ -92539,7 +92766,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_16B_WORD3</name> + <name>MB4_16B_WORD3_L</name> <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF4</addressOffset> @@ -92612,7 +92839,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD10</name> + <name>MB1_64B_WORD10_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF8</addressOffset> @@ -92652,7 +92879,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_CS</name> + <name>MB3_32B_CS_L</name> <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF8</addressOffset> @@ -92727,7 +92954,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_CS</name> + <name>MB5_16B_CS_L</name> <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xF8</addressOffset> @@ -92882,7 +93109,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD11</name> + <name>MB1_64B_WORD11_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xFC</addressOffset> @@ -92922,7 +93149,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_ID</name> + <name>MB3_32B_ID_L</name> <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xFC</addressOffset> @@ -92955,7 +93182,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_ID</name> + <name>MB5_16B_ID_L</name> <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0xFC</addressOffset> @@ -93143,7 +93370,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD12</name> + <name>MB1_64B_WORD12_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x100</addressOffset> @@ -93183,7 +93410,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD0</name> + <name>MB3_32B_WORD0_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x100</addressOffset> @@ -93223,7 +93450,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_WORD0</name> + <name>MB5_16B_WORD0_L</name> <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x100</addressOffset> @@ -93371,7 +93598,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD13</name> + <name>MB1_64B_WORD13_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x104</addressOffset> @@ -93411,7 +93638,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD1</name> + <name>MB3_32B_WORD1_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x104</addressOffset> @@ -93451,7 +93678,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_WORD1</name> + <name>MB5_16B_WORD1_L</name> <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x104</addressOffset> @@ -93524,7 +93751,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD14</name> + <name>MB1_64B_WORD14_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x108</addressOffset> @@ -93564,7 +93791,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD2</name> + <name>MB3_32B_WORD2_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x108</addressOffset> @@ -93604,7 +93831,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_WORD2</name> + <name>MB5_16B_WORD2_L</name> <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x108</addressOffset> @@ -93724,7 +93951,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB1_64B_WORD15</name> + <name>MB1_64B_WORD15_L</name> <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x10C</addressOffset> @@ -93764,7 +93991,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD3</name> + <name>MB3_32B_WORD3_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x10C</addressOffset> @@ -93804,7 +94031,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_16B_WORD3</name> + <name>MB5_16B_WORD3_L</name> <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x10C</addressOffset> @@ -93999,7 +94226,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_CS</name> + <name>MB2_64B_CS_L</name> <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x110</addressOffset> @@ -94074,7 +94301,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD4</name> + <name>MB3_32B_WORD4_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x110</addressOffset> @@ -94114,7 +94341,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_CS</name> + <name>MB6_16B_CS_L</name> <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x110</addressOffset> @@ -94297,7 +94524,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_ID</name> + <name>MB2_64B_ID_L</name> <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x114</addressOffset> @@ -94330,7 +94557,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD5</name> + <name>MB3_32B_WORD5_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x114</addressOffset> @@ -94370,7 +94597,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_ID</name> + <name>MB6_16B_ID_L</name> <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x114</addressOffset> @@ -94436,7 +94663,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD0</name> + <name>MB2_64B_WORD0_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x118</addressOffset> @@ -94476,7 +94703,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD6</name> + <name>MB3_32B_WORD6_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x118</addressOffset> @@ -94516,7 +94743,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_WORD0</name> + <name>MB6_16B_WORD0_L</name> <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x118</addressOffset> @@ -94636,7 +94863,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD1</name> + <name>MB2_64B_WORD1_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x11C</addressOffset> @@ -94676,7 +94903,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_32B_WORD7</name> + <name>MB3_32B_WORD7_L</name> <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x11C</addressOffset> @@ -94716,7 +94943,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_WORD1</name> + <name>MB6_16B_WORD1_L</name> <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x11C</addressOffset> @@ -94986,7 +95213,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD2</name> + <name>MB2_64B_WORD2_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x120</addressOffset> @@ -95026,7 +95253,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_CS</name> + <name>MB4_32B_CS_L</name> <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x120</addressOffset> @@ -95101,7 +95328,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_WORD2</name> + <name>MB6_16B_WORD2_L</name> <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x120</addressOffset> @@ -95207,7 +95434,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD3</name> + <name>MB2_64B_WORD3_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x124</addressOffset> @@ -95247,7 +95474,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_ID</name> + <name>MB4_32B_ID_L</name> <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x124</addressOffset> @@ -95280,7 +95507,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_16B_WORD3</name> + <name>MB6_16B_WORD3_L</name> <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x124</addressOffset> @@ -95360,7 +95587,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD4</name> + <name>MB2_64B_WORD4_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x128</addressOffset> @@ -95400,7 +95627,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD0</name> + <name>MB4_32B_WORD0_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x128</addressOffset> @@ -95440,7 +95667,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_CS</name> + <name>MB7_16B_CS_L</name> <description>Message Buffer 7 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x128</addressOffset> @@ -95595,7 +95822,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD5</name> + <name>MB2_64B_WORD5_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x12C</addressOffset> @@ -95635,7 +95862,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD1</name> + <name>MB4_32B_WORD1_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x12C</addressOffset> @@ -95675,7 +95902,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_ID</name> + <name>MB7_16B_ID_L</name> <description>Message Buffer 7 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x12C</addressOffset> @@ -95898,7 +96125,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD6</name> + <name>MB2_64B_WORD6_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x130</addressOffset> @@ -95938,7 +96165,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD2</name> + <name>MB4_32B_WORD2_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x130</addressOffset> @@ -95978,7 +96205,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_WORD0</name> + <name>MB7_16B_WORD0_L</name> <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x130</addressOffset> @@ -96084,7 +96311,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD7</name> + <name>MB2_64B_WORD7_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x134</addressOffset> @@ -96124,7 +96351,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD3</name> + <name>MB4_32B_WORD3_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x134</addressOffset> @@ -96164,7 +96391,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_WORD1</name> + <name>MB7_16B_WORD1_L</name> <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x134</addressOffset> @@ -96244,7 +96471,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD8</name> + <name>MB2_64B_WORD8_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x138</addressOffset> @@ -96284,7 +96511,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD4</name> + <name>MB4_32B_WORD4_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x138</addressOffset> @@ -96324,7 +96551,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_WORD2</name> + <name>MB7_16B_WORD2_L</name> <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x138</addressOffset> @@ -96444,7 +96671,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD9</name> + <name>MB2_64B_WORD9_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x13C</addressOffset> @@ -96484,7 +96711,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD5</name> + <name>MB4_32B_WORD5_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x13C</addressOffset> @@ -96524,7 +96751,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_16B_WORD3</name> + <name>MB7_16B_WORD3_L</name> <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x13C</addressOffset> @@ -96754,7 +96981,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD10</name> + <name>MB2_64B_WORD10_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x140</addressOffset> @@ -96794,7 +97021,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD6</name> + <name>MB4_32B_WORD6_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x140</addressOffset> @@ -96834,7 +97061,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_CS</name> + <name>MB8_16B_CS_L</name> <description>Message Buffer 8 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x140</addressOffset> @@ -96975,7 +97202,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD11</name> + <name>MB2_64B_WORD11_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x144</addressOffset> @@ -97015,7 +97242,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_32B_WORD7</name> + <name>MB4_32B_WORD7_L</name> <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x144</addressOffset> @@ -97055,7 +97282,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_ID</name> + <name>MB8_16B_ID_L</name> <description>Message Buffer 8 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x144</addressOffset> @@ -97128,7 +97355,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD12</name> + <name>MB2_64B_WORD12_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x148</addressOffset> @@ -97168,7 +97395,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_CS</name> + <name>MB5_32B_CS_L</name> <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x148</addressOffset> @@ -97243,7 +97470,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_WORD0</name> + <name>MB8_16B_WORD0_L</name> <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x148</addressOffset> @@ -97363,7 +97590,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD13</name> + <name>MB2_64B_WORD13_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x14C</addressOffset> @@ -97403,7 +97630,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_ID</name> + <name>MB5_32B_ID_L</name> <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x14C</addressOffset> @@ -97436,7 +97663,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_WORD1</name> + <name>MB8_16B_WORD1_L</name> <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x14C</addressOffset> @@ -97666,7 +97893,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD14</name> + <name>MB2_64B_WORD14_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x150</addressOffset> @@ -97706,7 +97933,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD0</name> + <name>MB5_32B_WORD0_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x150</addressOffset> @@ -97746,7 +97973,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_WORD2</name> + <name>MB8_16B_WORD2_L</name> <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x150</addressOffset> @@ -97852,7 +98079,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB2_64B_WORD15</name> + <name>MB2_64B_WORD15_L</name> <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x154</addressOffset> @@ -97892,7 +98119,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD1</name> + <name>MB5_32B_WORD1_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x154</addressOffset> @@ -97932,7 +98159,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_16B_WORD3</name> + <name>MB8_16B_WORD3_L</name> <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x154</addressOffset> @@ -98012,7 +98239,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_CS</name> + <name>MB3_64B_CS_L</name> <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x158</addressOffset> @@ -98087,7 +98314,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD2</name> + <name>MB5_32B_WORD2_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x158</addressOffset> @@ -98127,7 +98354,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_CS</name> + <name>MB9_16B_CS_L</name> <description>Message Buffer 9 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x158</addressOffset> @@ -98282,7 +98509,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_ID</name> + <name>MB3_64B_ID_L</name> <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x15C</addressOffset> @@ -98315,7 +98542,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD3</name> + <name>MB5_32B_WORD3_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x15C</addressOffset> @@ -98355,7 +98582,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_ID</name> + <name>MB9_16B_ID_L</name> <description>Message Buffer 9 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x15C</addressOffset> @@ -98578,7 +98805,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD0</name> + <name>MB3_64B_WORD0_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x160</addressOffset> @@ -98618,7 +98845,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD4</name> + <name>MB5_32B_WORD4_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x160</addressOffset> @@ -98658,7 +98885,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_WORD0</name> + <name>MB9_16B_WORD0_L</name> <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x160</addressOffset> @@ -98764,7 +98991,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD1</name> + <name>MB3_64B_WORD1_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x164</addressOffset> @@ -98804,7 +99031,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD5</name> + <name>MB5_32B_WORD5_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x164</addressOffset> @@ -98844,7 +99071,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_WORD1</name> + <name>MB9_16B_WORD1_L</name> <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x164</addressOffset> @@ -98924,7 +99151,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD2</name> + <name>MB3_64B_WORD2_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x168</addressOffset> @@ -98964,7 +99191,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD6</name> + <name>MB5_32B_WORD6_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x168</addressOffset> @@ -99004,7 +99231,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_WORD2</name> + <name>MB9_16B_WORD2_L</name> <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x168</addressOffset> @@ -99124,7 +99351,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD3</name> + <name>MB3_64B_WORD3_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x16C</addressOffset> @@ -99164,7 +99391,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_32B_WORD7</name> + <name>MB5_32B_WORD7_L</name> <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x16C</addressOffset> @@ -99204,7 +99431,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_16B_WORD3</name> + <name>MB9_16B_WORD3_L</name> <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x16C</addressOffset> @@ -99359,7 +99586,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_CS</name> + <name>MB10_16B_CS_L</name> <description>Message Buffer 10 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x170</addressOffset> @@ -99509,7 +99736,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD4</name> + <name>MB3_64B_WORD4_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x170</addressOffset> @@ -99549,7 +99776,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_CS</name> + <name>MB6_32B_CS_L</name> <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x170</addressOffset> @@ -99657,7 +99884,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_ID</name> + <name>MB10_16B_ID_L</name> <description>Message Buffer 10 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x174</addressOffset> @@ -99723,7 +99950,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD5</name> + <name>MB3_64B_WORD5_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x174</addressOffset> @@ -99763,7 +99990,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_ID</name> + <name>MB6_32B_ID_L</name> <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x174</addressOffset> @@ -99796,7 +100023,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_WORD0</name> + <name>MB10_16B_WORD0_L</name> <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x178</addressOffset> @@ -99876,7 +100103,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD6</name> + <name>MB3_64B_WORD6_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x178</addressOffset> @@ -99916,7 +100143,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD0</name> + <name>MB6_32B_WORD0_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x178</addressOffset> @@ -99996,7 +100223,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_WORD1</name> + <name>MB10_16B_WORD1_L</name> <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x17C</addressOffset> @@ -100076,7 +100303,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD7</name> + <name>MB3_64B_WORD7_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x17C</addressOffset> @@ -100116,7 +100343,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD1</name> + <name>MB6_32B_WORD1_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x17C</addressOffset> @@ -100271,7 +100498,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_WORD2</name> + <name>MB10_16B_WORD2_L</name> <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x180</addressOffset> @@ -100386,7 +100613,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD8</name> + <name>MB3_64B_WORD8_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x180</addressOffset> @@ -100426,7 +100653,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD2</name> + <name>MB6_32B_WORD2_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x180</addressOffset> @@ -100499,7 +100726,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_16B_WORD3</name> + <name>MB10_16B_WORD3_L</name> <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x184</addressOffset> @@ -100572,7 +100799,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD9</name> + <name>MB3_64B_WORD9_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x184</addressOffset> @@ -100612,7 +100839,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD3</name> + <name>MB6_32B_WORD3_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x184</addressOffset> @@ -100652,7 +100879,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_CS</name> + <name>MB11_16B_CS_L</name> <description>Message Buffer 11 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x188</addressOffset> @@ -100767,7 +100994,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD10</name> + <name>MB3_64B_WORD10_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x188</addressOffset> @@ -100807,7 +101034,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD4</name> + <name>MB6_32B_WORD4_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x188</addressOffset> @@ -100887,7 +101114,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_ID</name> + <name>MB11_16B_ID_L</name> <description>Message Buffer 11 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x18C</addressOffset> @@ -100960,7 +101187,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD11</name> + <name>MB3_64B_WORD11_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x18C</addressOffset> @@ -101000,7 +101227,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD5</name> + <name>MB6_32B_WORD5_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x18C</addressOffset> @@ -101155,7 +101382,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_WORD0</name> + <name>MB11_16B_WORD0_L</name> <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x190</addressOffset> @@ -101270,7 +101497,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD12</name> + <name>MB3_64B_WORD12_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x190</addressOffset> @@ -101310,7 +101537,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD6</name> + <name>MB6_32B_WORD6_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x190</addressOffset> @@ -101383,7 +101610,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_WORD1</name> + <name>MB11_16B_WORD1_L</name> <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x194</addressOffset> @@ -101456,7 +101683,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD13</name> + <name>MB3_64B_WORD13_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x194</addressOffset> @@ -101496,7 +101723,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_32B_WORD7</name> + <name>MB6_32B_WORD7_L</name> <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x194</addressOffset> @@ -101536,7 +101763,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_WORD2</name> + <name>MB11_16B_WORD2_L</name> <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x198</addressOffset> @@ -101616,7 +101843,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD14</name> + <name>MB3_64B_WORD14_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x198</addressOffset> @@ -101656,7 +101883,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_CS</name> + <name>MB7_32B_CS_L</name> <description>Message Buffer 7 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x198</addressOffset> @@ -101771,7 +101998,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_16B_WORD3</name> + <name>MB11_16B_WORD3_L</name> <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x19C</addressOffset> @@ -101851,7 +102078,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB3_64B_WORD15</name> + <name>MB3_64B_WORD15_L</name> <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x19C</addressOffset> @@ -101891,7 +102118,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_ID</name> + <name>MB7_32B_ID_L</name> <description>Message Buffer 7 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x19C</addressOffset> @@ -102039,7 +102266,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_CS</name> + <name>MB12_16B_CS_L</name> <description>Message Buffer 12 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A0</addressOffset> @@ -102189,7 +102416,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_CS</name> + <name>MB4_64B_CS_L</name> <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A0</addressOffset> @@ -102264,7 +102491,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD0</name> + <name>MB7_32B_WORD0_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A0</addressOffset> @@ -102337,7 +102564,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_ID</name> + <name>MB12_16B_ID_L</name> <description>Message Buffer 12 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A4</addressOffset> @@ -102403,7 +102630,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_ID</name> + <name>MB4_64B_ID_L</name> <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A4</addressOffset> @@ -102436,7 +102663,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD1</name> + <name>MB7_32B_WORD1_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A4</addressOffset> @@ -102476,7 +102703,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_WORD0</name> + <name>MB12_16B_WORD0_L</name> <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A8</addressOffset> @@ -102556,7 +102783,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD0</name> + <name>MB4_64B_WORD0_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A8</addressOffset> @@ -102596,7 +102823,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD2</name> + <name>MB7_32B_WORD2_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1A8</addressOffset> @@ -102676,7 +102903,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_WORD1</name> + <name>MB12_16B_WORD1_L</name> <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1AC</addressOffset> @@ -102756,7 +102983,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD1</name> + <name>MB4_64B_WORD1_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1AC</addressOffset> @@ -102796,7 +103023,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD3</name> + <name>MB7_32B_WORD3_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1AC</addressOffset> @@ -102951,7 +103178,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_WORD2</name> + <name>MB12_16B_WORD2_L</name> <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B0</addressOffset> @@ -103066,7 +103293,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD2</name> + <name>MB4_64B_WORD2_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B0</addressOffset> @@ -103106,7 +103333,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD4</name> + <name>MB7_32B_WORD4_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B0</addressOffset> @@ -103179,7 +103406,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_16B_WORD3</name> + <name>MB12_16B_WORD3_L</name> <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B4</addressOffset> @@ -103252,7 +103479,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD3</name> + <name>MB4_64B_WORD3_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B4</addressOffset> @@ -103292,7 +103519,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD5</name> + <name>MB7_32B_WORD5_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B4</addressOffset> @@ -103332,7 +103559,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_CS</name> + <name>MB13_16B_CS_L</name> <description>Message Buffer 13 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B8</addressOffset> @@ -103447,7 +103674,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD4</name> + <name>MB4_64B_WORD4_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B8</addressOffset> @@ -103487,7 +103714,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD6</name> + <name>MB7_32B_WORD6_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1B8</addressOffset> @@ -103567,7 +103794,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_ID</name> + <name>MB13_16B_ID_L</name> <description>Message Buffer 13 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1BC</addressOffset> @@ -103640,7 +103867,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD5</name> + <name>MB4_64B_WORD5_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1BC</addressOffset> @@ -103680,7 +103907,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_32B_WORD7</name> + <name>MB7_32B_WORD7_L</name> <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1BC</addressOffset> @@ -103835,7 +104062,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_WORD0</name> + <name>MB13_16B_WORD0_L</name> <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C0</addressOffset> @@ -103950,7 +104177,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD6</name> + <name>MB4_64B_WORD6_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C0</addressOffset> @@ -103990,7 +104217,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_CS</name> + <name>MB8_32B_CS_L</name> <description>Message Buffer 8 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C0</addressOffset> @@ -104098,7 +104325,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_WORD1</name> + <name>MB13_16B_WORD1_L</name> <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C4</addressOffset> @@ -104171,7 +104398,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD7</name> + <name>MB4_64B_WORD7_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C4</addressOffset> @@ -104211,7 +104438,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_ID</name> + <name>MB8_32B_ID_L</name> <description>Message Buffer 8 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C4</addressOffset> @@ -104244,7 +104471,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_WORD2</name> + <name>MB13_16B_WORD2_L</name> <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C8</addressOffset> @@ -104324,7 +104551,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD8</name> + <name>MB4_64B_WORD8_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C8</addressOffset> @@ -104364,7 +104591,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD0</name> + <name>MB8_32B_WORD0_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1C8</addressOffset> @@ -104444,7 +104671,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_16B_WORD3</name> + <name>MB13_16B_WORD3_L</name> <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1CC</addressOffset> @@ -104524,7 +104751,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD9</name> + <name>MB4_64B_WORD9_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1CC</addressOffset> @@ -104564,7 +104791,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD1</name> + <name>MB8_32B_WORD1_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1CC</addressOffset> @@ -104719,7 +104946,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_CS</name> + <name>MB14_16B_CS_L</name> <description>Message Buffer 14 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D0</addressOffset> @@ -104869,7 +105096,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD10</name> + <name>MB4_64B_WORD10_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D0</addressOffset> @@ -104909,7 +105136,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD2</name> + <name>MB8_32B_WORD2_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D0</addressOffset> @@ -104982,7 +105209,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_ID</name> + <name>MB14_16B_ID_L</name> <description>Message Buffer 14 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D4</addressOffset> @@ -105048,7 +105275,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD11</name> + <name>MB4_64B_WORD11_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D4</addressOffset> @@ -105088,7 +105315,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD3</name> + <name>MB8_32B_WORD3_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D4</addressOffset> @@ -105128,7 +105355,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_WORD0</name> + <name>MB14_16B_WORD0_L</name> <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D8</addressOffset> @@ -105208,7 +105435,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD12</name> + <name>MB4_64B_WORD12_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D8</addressOffset> @@ -105248,7 +105475,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD4</name> + <name>MB8_32B_WORD4_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1D8</addressOffset> @@ -105328,7 +105555,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_WORD1</name> + <name>MB14_16B_WORD1_L</name> <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1DC</addressOffset> @@ -105408,7 +105635,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD13</name> + <name>MB4_64B_WORD13_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1DC</addressOffset> @@ -105448,7 +105675,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD5</name> + <name>MB8_32B_WORD5_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1DC</addressOffset> @@ -105603,7 +105830,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_WORD2</name> + <name>MB14_16B_WORD2_L</name> <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E0</addressOffset> @@ -105718,7 +105945,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD14</name> + <name>MB4_64B_WORD14_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E0</addressOffset> @@ -105758,7 +105985,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD6</name> + <name>MB8_32B_WORD6_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E0</addressOffset> @@ -105831,7 +106058,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_16B_WORD3</name> + <name>MB14_16B_WORD3_L</name> <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E4</addressOffset> @@ -105904,7 +106131,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB4_64B_WORD15</name> + <name>MB4_64B_WORD15_L</name> <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E4</addressOffset> @@ -105944,7 +106171,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_32B_WORD7</name> + <name>MB8_32B_WORD7_L</name> <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E4</addressOffset> @@ -105984,7 +106211,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_CS</name> + <name>MB15_16B_CS_L</name> <description>Message Buffer 15 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E8</addressOffset> @@ -106099,7 +106326,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_CS</name> + <name>MB5_64B_CS_L</name> <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E8</addressOffset> @@ -106174,7 +106401,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_CS</name> + <name>MB9_32B_CS_L</name> <description>Message Buffer 9 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1E8</addressOffset> @@ -106289,7 +106516,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_ID</name> + <name>MB15_16B_ID_L</name> <description>Message Buffer 15 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1EC</addressOffset> @@ -106362,7 +106589,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_ID</name> + <name>MB5_64B_ID_L</name> <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1EC</addressOffset> @@ -106395,7 +106622,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_ID</name> + <name>MB9_32B_ID_L</name> <description>Message Buffer 9 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1EC</addressOffset> @@ -106543,7 +106770,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_WORD0</name> + <name>MB15_16B_WORD0_L</name> <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F0</addressOffset> @@ -106658,7 +106885,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD0</name> + <name>MB5_64B_WORD0_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F0</addressOffset> @@ -106698,7 +106925,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD0</name> + <name>MB9_32B_WORD0_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F0</addressOffset> @@ -106771,7 +106998,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_WORD1</name> + <name>MB15_16B_WORD1_L</name> <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F4</addressOffset> @@ -106844,7 +107071,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD1</name> + <name>MB5_64B_WORD1_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F4</addressOffset> @@ -106884,7 +107111,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD1</name> + <name>MB9_32B_WORD1_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F4</addressOffset> @@ -106924,7 +107151,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_WORD2</name> + <name>MB15_16B_WORD2_L</name> <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F8</addressOffset> @@ -107004,7 +107231,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD2</name> + <name>MB5_64B_WORD2_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F8</addressOffset> @@ -107044,7 +107271,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD2</name> + <name>MB9_32B_WORD2_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1F8</addressOffset> @@ -107124,7 +107351,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_16B_WORD3</name> + <name>MB15_16B_WORD3_L</name> <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1FC</addressOffset> @@ -107204,7 +107431,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD3</name> + <name>MB5_64B_WORD3_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1FC</addressOffset> @@ -107244,7 +107471,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD3</name> + <name>MB9_32B_WORD3_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x1FC</addressOffset> @@ -107399,7 +107626,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_CS</name> + <name>MB16_16B_CS_L</name> <description>Message Buffer 16 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x200</addressOffset> @@ -107549,7 +107776,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD4</name> + <name>MB5_64B_WORD4_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x200</addressOffset> @@ -107589,7 +107816,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD4</name> + <name>MB9_32B_WORD4_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x200</addressOffset> @@ -107662,7 +107889,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_ID</name> + <name>MB16_16B_ID_L</name> <description>Message Buffer 16 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x204</addressOffset> @@ -107728,7 +107955,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD5</name> + <name>MB5_64B_WORD5_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x204</addressOffset> @@ -107768,7 +107995,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD5</name> + <name>MB9_32B_WORD5_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x204</addressOffset> @@ -107808,7 +108035,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_WORD0</name> + <name>MB16_16B_WORD0_L</name> <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x208</addressOffset> @@ -107888,7 +108115,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD6</name> + <name>MB5_64B_WORD6_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x208</addressOffset> @@ -107928,7 +108155,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD6</name> + <name>MB9_32B_WORD6_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x208</addressOffset> @@ -108008,7 +108235,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_WORD1</name> + <name>MB16_16B_WORD1_L</name> <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x20C</addressOffset> @@ -108088,7 +108315,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD7</name> + <name>MB5_64B_WORD7_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x20C</addressOffset> @@ -108128,7 +108355,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_32B_WORD7</name> + <name>MB9_32B_WORD7_L</name> <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x20C</addressOffset> @@ -108283,7 +108510,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_CS</name> + <name>MB10_32B_CS_L</name> <description>Message Buffer 10 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x210</addressOffset> @@ -108358,7 +108585,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_WORD2</name> + <name>MB16_16B_WORD2_L</name> <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x210</addressOffset> @@ -108473,7 +108700,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD8</name> + <name>MB5_64B_WORD8_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x210</addressOffset> @@ -108546,7 +108773,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_ID</name> + <name>MB10_32B_ID_L</name> <description>Message Buffer 10 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x214</addressOffset> @@ -108579,7 +108806,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_16B_WORD3</name> + <name>MB16_16B_WORD3_L</name> <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x214</addressOffset> @@ -108652,7 +108879,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD9</name> + <name>MB5_64B_WORD9_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x214</addressOffset> @@ -108692,7 +108919,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD0</name> + <name>MB10_32B_WORD0_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x218</addressOffset> @@ -108732,7 +108959,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_CS</name> + <name>MB17_16B_CS_L</name> <description>Message Buffer 17 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x218</addressOffset> @@ -108847,7 +109074,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD10</name> + <name>MB5_64B_WORD10_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x218</addressOffset> @@ -108927,7 +109154,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD1</name> + <name>MB10_32B_WORD1_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x21C</addressOffset> @@ -108967,7 +109194,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_ID</name> + <name>MB17_16B_ID_L</name> <description>Message Buffer 17 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x21C</addressOffset> @@ -109040,7 +109267,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD11</name> + <name>MB5_64B_WORD11_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x21C</addressOffset> @@ -109195,7 +109422,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD2</name> + <name>MB10_32B_WORD2_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x220</addressOffset> @@ -109235,7 +109462,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_WORD0</name> + <name>MB17_16B_WORD0_L</name> <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x220</addressOffset> @@ -109350,7 +109577,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD12</name> + <name>MB5_64B_WORD12_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x220</addressOffset> @@ -109423,7 +109650,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD3</name> + <name>MB10_32B_WORD3_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x224</addressOffset> @@ -109463,7 +109690,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_WORD1</name> + <name>MB17_16B_WORD1_L</name> <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x224</addressOffset> @@ -109536,7 +109763,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD13</name> + <name>MB5_64B_WORD13_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x224</addressOffset> @@ -109576,7 +109803,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD4</name> + <name>MB10_32B_WORD4_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x228</addressOffset> @@ -109616,7 +109843,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_WORD2</name> + <name>MB17_16B_WORD2_L</name> <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x228</addressOffset> @@ -109696,7 +109923,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD14</name> + <name>MB5_64B_WORD14_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x228</addressOffset> @@ -109776,7 +110003,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD5</name> + <name>MB10_32B_WORD5_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x22C</addressOffset> @@ -109816,7 +110043,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_16B_WORD3</name> + <name>MB17_16B_WORD3_L</name> <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x22C</addressOffset> @@ -109896,7 +110123,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB5_64B_WORD15</name> + <name>MB5_64B_WORD15_L</name> <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x22C</addressOffset> @@ -110051,7 +110278,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD6</name> + <name>MB10_32B_WORD6_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x230</addressOffset> @@ -110091,7 +110318,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_CS</name> + <name>MB18_16B_CS_L</name> <description>Message Buffer 18 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x230</addressOffset> @@ -110241,7 +110468,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_CS</name> + <name>MB6_64B_CS_L</name> <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x230</addressOffset> @@ -110349,7 +110576,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_32B_WORD7</name> + <name>MB10_32B_WORD7_L</name> <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x234</addressOffset> @@ -110389,7 +110616,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_ID</name> + <name>MB18_16B_ID_L</name> <description>Message Buffer 18 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x234</addressOffset> @@ -110455,7 +110682,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_ID</name> + <name>MB6_64B_ID_L</name> <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x234</addressOffset> @@ -110488,7 +110715,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_CS</name> + <name>MB11_32B_CS_L</name> <description>Message Buffer 11 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x238</addressOffset> @@ -110563,7 +110790,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_WORD0</name> + <name>MB18_16B_WORD0_L</name> <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x238</addressOffset> @@ -110643,7 +110870,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD0</name> + <name>MB6_64B_WORD0_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x238</addressOffset> @@ -110723,7 +110950,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_ID</name> + <name>MB11_32B_ID_L</name> <description>Message Buffer 11 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x23C</addressOffset> @@ -110756,7 +110983,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_WORD1</name> + <name>MB18_16B_WORD1_L</name> <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x23C</addressOffset> @@ -110836,7 +111063,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD1</name> + <name>MB6_64B_WORD1_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x23C</addressOffset> @@ -110991,7 +111218,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD0</name> + <name>MB11_32B_WORD0_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x240</addressOffset> @@ -111031,7 +111258,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_WORD2</name> + <name>MB18_16B_WORD2_L</name> <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x240</addressOffset> @@ -111146,7 +111373,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD2</name> + <name>MB6_64B_WORD2_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x240</addressOffset> @@ -111219,7 +111446,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD1</name> + <name>MB11_32B_WORD1_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x244</addressOffset> @@ -111259,7 +111486,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_16B_WORD3</name> + <name>MB18_16B_WORD3_L</name> <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x244</addressOffset> @@ -111332,7 +111559,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD3</name> + <name>MB6_64B_WORD3_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x244</addressOffset> @@ -111372,7 +111599,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD2</name> + <name>MB11_32B_WORD2_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x248</addressOffset> @@ -111412,7 +111639,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_CS</name> + <name>MB19_16B_CS_L</name> <description>Message Buffer 19 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x248</addressOffset> @@ -111527,7 +111754,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD4</name> + <name>MB6_64B_WORD4_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x248</addressOffset> @@ -111607,7 +111834,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD3</name> + <name>MB11_32B_WORD3_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x24C</addressOffset> @@ -111647,7 +111874,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_ID</name> + <name>MB19_16B_ID_L</name> <description>Message Buffer 19 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x24C</addressOffset> @@ -111720,7 +111947,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD5</name> + <name>MB6_64B_WORD5_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x24C</addressOffset> @@ -111875,7 +112102,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD4</name> + <name>MB11_32B_WORD4_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x250</addressOffset> @@ -111915,7 +112142,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_WORD0</name> + <name>MB19_16B_WORD0_L</name> <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x250</addressOffset> @@ -112030,7 +112257,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD6</name> + <name>MB6_64B_WORD6_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x250</addressOffset> @@ -112103,7 +112330,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD5</name> + <name>MB11_32B_WORD5_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x254</addressOffset> @@ -112143,7 +112370,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_WORD1</name> + <name>MB19_16B_WORD1_L</name> <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x254</addressOffset> @@ -112216,7 +112443,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD7</name> + <name>MB6_64B_WORD7_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x254</addressOffset> @@ -112256,7 +112483,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD6</name> + <name>MB11_32B_WORD6_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x258</addressOffset> @@ -112296,7 +112523,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_WORD2</name> + <name>MB19_16B_WORD2_L</name> <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x258</addressOffset> @@ -112376,7 +112603,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD8</name> + <name>MB6_64B_WORD8_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x258</addressOffset> @@ -112456,7 +112683,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_32B_WORD7</name> + <name>MB11_32B_WORD7_L</name> <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x25C</addressOffset> @@ -112496,7 +112723,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_16B_WORD3</name> + <name>MB19_16B_WORD3_L</name> <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x25C</addressOffset> @@ -112576,7 +112803,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD9</name> + <name>MB6_64B_WORD9_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x25C</addressOffset> @@ -112731,82 +112958,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_CS</name> - <description>Message Buffer 12 CS Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x260</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> - <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_CS</name> + <name>MB20_16B_CS_L</name> <description>Message Buffer 20 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x260</addressOffset> @@ -112956,7 +113108,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD10</name> + <name>MB6_64B_WORD10_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x260</addressOffset> @@ -113029,40 +113181,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_ID</name> - <description>Message Buffer 12 ID Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x264</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> - <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> - <access>read-write</access> - </field> - <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> - <access>read-write</access> - </field> - <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_ID</name> + <name>MB20_16B_ID_L</name> <description>Message Buffer 20 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x264</addressOffset> @@ -113128,7 +113247,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD11</name> + <name>MB6_64B_WORD11_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x264</addressOffset> @@ -113168,47 +113287,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD0</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x268</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_WORD0</name> + <name>MB20_16B_WORD0_L</name> <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x268</addressOffset> @@ -113288,7 +113367,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD12</name> + <name>MB6_64B_WORD12_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x268</addressOffset> @@ -113368,47 +113447,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD1</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x26C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_WORD1</name> + <name>MB20_16B_WORD1_L</name> <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x26C</addressOffset> @@ -113488,7 +113527,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD13</name> + <name>MB6_64B_WORD13_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x26C</addressOffset> @@ -113643,47 +113682,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD2</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x270</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_WORD2</name> + <name>MB20_16B_WORD2_L</name> <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x270</addressOffset> @@ -113798,7 +113797,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD14</name> + <name>MB6_64B_WORD14_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x270</addressOffset> @@ -113871,47 +113870,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD3</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x274</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_16B_WORD3</name> + <name>MB20_16B_WORD3_L</name> <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x274</addressOffset> @@ -113984,7 +113943,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB6_64B_WORD15</name> + <name>MB6_64B_WORD15_L</name> <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x274</addressOffset> @@ -114024,8 +113983,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD4</name> - <description>Message Buffer 12 WORD_32B Register</description> + <name>MB31_8B_WORD0</name> + <description>Message Buffer 31 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x278</addressOffset> <size>32</size> @@ -114034,28 +113993,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -114064,8 +114023,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_16B_CS</name> - <description>Message Buffer 21 CS Register</description> + <name>WORD031</name> + <description>Message Buffer 31 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x278</addressOffset> <size>32</size> @@ -114074,103 +114033,108 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB31_8B_WORD1</name> + <description>Message Buffer 31 WORD_8B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x27C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB31_8B_WORD0</name> - <description>Message Buffer 31 WORD_8B Register</description> + <name>WORD131</name> + <description>Message Buffer 31 WORD1 Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x278</addressOffset> + <addressOffset>0x27C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -114179,10 +114143,10 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_CS</name> - <description>Message Buffer 7 CS Register</description> + <name>CS32</name> + <description>Message Buffer 32 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x278</addressOffset> + <addressOffset>0x280</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> @@ -114254,234 +114218,158 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>WORD031</name> - <description>Message Buffer 31 WORD0 Register</description> + <name>MB0_16B_CS_H</name> + <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x278</addressOffset> + <addressOffset>0x280</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB12_32B_WORD5</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x27C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_23</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB21_16B_ID</name> - <description>Message Buffer 21 ID Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x27C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> - <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB31_8B_WORD1</name> - <description>Message Buffer 31 WORD_8B Register</description> + <name>MB0_32B_CS_H</name> + <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x27C</addressOffset> + <addressOffset>0x280</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB7_64B_ID</name> - <description>Message Buffer 7 ID Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x27C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> - <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>WORD131</name> - <description>Message Buffer 31 WORD1 Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x27C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>CS32</name> - <description>Message Buffer 32 CS Register</description> + <name>MB0_64B_CS_H</name> + <description>Message Buffer 0 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x280</addressOffset> <size>32</size> @@ -114555,86 +114443,6 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD6</name> - <description>Message Buffer 12 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x280</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB21_16B_WORD0</name> - <description>Message Buffer 21 WORD_16B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x280</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> <name>MB32_8B_CS</name> <description>Message Buffer 32 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -114710,48 +114518,41 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD0</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>ID32</name> + <description>Message Buffer 32 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x280</addressOffset> + <addressOffset>0x284</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>ID32</name> - <description>Message Buffer 32 ID Register</description> + <name>MB0_16B_ID_H</name> + <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x284</addressOffset> <size>32</size> @@ -114783,8 +114584,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_32B_WORD7</name> - <description>Message Buffer 12 WORD_32B Register</description> + <name>MB0_32B_ID_H</name> + <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x284</addressOffset> <size>32</size> @@ -114793,38 +114594,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB21_16B_WORD1</name> - <description>Message Buffer 21 WORD_16B Register</description> + <name>MB0_64B_ID_H</name> + <description>Message Buffer 0 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x284</addressOffset> <size>32</size> @@ -114833,31 +114627,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -114896,38 +114683,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD1</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB0_16B_WORD0_H</name> + <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x284</addressOffset> + <addressOffset>0x288</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -114936,83 +114723,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_CS</name> - <description>Message Buffer 13 CS Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x288</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> - <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB21_16B_WORD2</name> - <description>Message Buffer 21 WORD_16B Register</description> + <name>MB0_32B_WORD0_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x288</addressOffset> <size>32</size> @@ -115021,28 +114733,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115051,8 +114763,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_8B_WORD0</name> - <description>Message Buffer 32 WORD_8B Register</description> + <name>MB0_64B_WORD0_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x288</addressOffset> <size>32</size> @@ -115091,8 +114803,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD2</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB32_8B_WORD0</name> + <description>Message Buffer 32 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x288</addressOffset> <size>32</size> @@ -115101,28 +114813,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115171,8 +114883,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_ID</name> - <description>Message Buffer 13 ID Register</description> + <name>MB0_16B_WORD1_H</name> + <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x28C</addressOffset> <size>32</size> @@ -115181,31 +114893,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB21_16B_WORD3</name> - <description>Message Buffer 21 WORD_16B Register</description> + <name>MB0_32B_WORD1_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x28C</addressOffset> <size>32</size> @@ -115214,28 +114933,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115244,8 +114963,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_8B_WORD1</name> - <description>Message Buffer 32 WORD_8B Register</description> + <name>MB0_64B_WORD1_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x28C</addressOffset> <size>32</size> @@ -115284,8 +115003,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD3</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB32_8B_WORD1</name> + <description>Message Buffer 32 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x28C</addressOffset> <size>32</size> @@ -115294,28 +115013,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115439,8 +115158,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD0</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_16B_WORD2_H</name> + <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x290</addressOffset> <size>32</size> @@ -115449,28 +115168,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115479,8 +115198,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_CS</name> - <description>Message Buffer 22 CS Register</description> + <name>MB0_32B_WORD2_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x290</addressOffset> <size>32</size> @@ -115489,66 +115208,71 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB0_64B_WORD2_H</name> + <description>Message Buffer 0 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x290</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -115629,48 +115353,41 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD4</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>ID33</name> + <description>Message Buffer 33 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x290</addressOffset> + <addressOffset>0x294</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_18</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>ID33</name> - <description>Message Buffer 33 ID Register</description> + <name>MB0_16B_WORD3_H</name> + <description>Message Buffer 0 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x294</addressOffset> <size>32</size> @@ -115679,31 +115396,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB13_32B_WORD1</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_32B_WORD3_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x294</addressOffset> <size>32</size> @@ -115712,28 +115436,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115742,8 +115466,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_ID</name> - <description>Message Buffer 22 ID Register</description> + <name>MB0_64B_WORD3_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x294</addressOffset> <size>32</size> @@ -115752,24 +115476,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -115808,38 +115539,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD5</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB0_32B_WORD4_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x294</addressOffset> + <addressOffset>0x298</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115848,8 +115579,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD2</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_64B_WORD4_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x298</addressOffset> <size>32</size> @@ -115858,28 +115589,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -115888,8 +115619,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_WORD0</name> - <description>Message Buffer 22 WORD_16B Register</description> + <name>MB1_16B_CS_H</name> + <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x298</addressOffset> <size>32</size> @@ -115898,78 +115629,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB33_8B_WORD0</name> - <description>Message Buffer 33 WORD_8B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x298</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB7_64B_WORD6</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB33_8B_WORD0</name> + <description>Message Buffer 33 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x298</addressOffset> <size>32</size> @@ -115978,28 +115704,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116048,8 +115774,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD3</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_32B_WORD5_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x29C</addressOffset> <size>32</size> @@ -116058,28 +115784,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116088,8 +115814,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_WORD1</name> - <description>Message Buffer 22 WORD_16B Register</description> + <name>MB0_64B_WORD5_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x29C</addressOffset> <size>32</size> @@ -116098,28 +115824,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116128,8 +115854,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_8B_WORD1</name> - <description>Message Buffer 33 WORD_8B Register</description> + <name>MB1_16B_ID_H</name> + <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x29C</addressOffset> <size>32</size> @@ -116138,38 +115864,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB7_64B_WORD7</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB33_8B_WORD1</name> + <description>Message Buffer 33 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x29C</addressOffset> <size>32</size> @@ -116178,28 +115897,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116323,8 +116042,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD4</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_32B_WORD6_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A0</addressOffset> <size>32</size> @@ -116333,28 +116052,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116363,8 +116082,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_WORD2</name> - <description>Message Buffer 22 WORD_16B Register</description> + <name>MB0_64B_WORD6_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A0</addressOffset> <size>32</size> @@ -116373,28 +116092,68 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>MB1_16B_WORD0_H</name> + <description>Message Buffer 1 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x2A0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116478,48 +116237,41 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD8</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>ID34</name> + <description>Message Buffer 34 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x2A0</addressOffset> + <addressOffset>0x2A4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_34</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>ID34</name> - <description>Message Buffer 34 ID Register</description> + <name>MB0_32B_WORD7_H</name> + <description>Message Buffer 0 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A4</addressOffset> <size>32</size> @@ -116528,31 +116280,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_31</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_30</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_29</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_28</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB13_32B_WORD5</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB0_64B_WORD7_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A4</addressOffset> <size>32</size> @@ -116561,28 +116320,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116591,8 +116350,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_16B_WORD3</name> - <description>Message Buffer 22 WORD_16B Register</description> + <name>MB1_16B_WORD1_H</name> + <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A4</addressOffset> <size>32</size> @@ -116601,28 +116360,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116664,38 +116423,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD9</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB0_64B_WORD8_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x2A4</addressOffset> + <addressOffset>0x2A8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_35</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_34</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_33</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_32</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116704,8 +116463,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD6</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB1_16B_WORD2_H</name> + <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A8</addressOffset> <size>32</size> @@ -116714,28 +116473,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116744,8 +116503,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_16B_CS</name> - <description>Message Buffer 23 CS Register</description> + <name>MB1_32B_CS_H</name> + <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A8</addressOffset> <size>32</size> @@ -116859,8 +116618,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD10</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>WORD034</name> + <description>Message Buffer 34 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2A8</addressOffset> <size>32</size> @@ -116869,28 +116628,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116899,38 +116658,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>WORD034</name> - <description>Message Buffer 34 WORD0 Register</description> + <name>MB0_64B_WORD9_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x2A8</addressOffset> + <addressOffset>0x2AC</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_39</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_38</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_37</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_36</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116939,8 +116698,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_32B_WORD7</name> - <description>Message Buffer 13 WORD_32B Register</description> + <name>MB1_16B_WORD3_H</name> + <description>Message Buffer 1 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2AC</addressOffset> <size>32</size> @@ -116949,28 +116708,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -116979,8 +116738,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_16B_ID</name> - <description>Message Buffer 23 ID Register</description> + <name>MB1_32B_ID_H</name> + <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2AC</addressOffset> <size>32</size> @@ -117052,46 +116811,6 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD11</name> - <description>Message Buffer 7 WORD_64B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x2AC</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_47</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_46</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_45</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_44</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> <name>WORD134</name> <description>Message Buffer 34 WORD1 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -117207,8 +116926,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_CS</name> - <description>Message Buffer 14 CS Register</description> + <name>MB0_64B_WORD10_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B0</addressOffset> <size>32</size> @@ -117217,73 +116936,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_43</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_42</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_41</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_40</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_16B_WORD0</name> - <description>Message Buffer 23 WORD_16B Register</description> + <name>MB1_32B_WORD0_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B0</addressOffset> <size>32</size> @@ -117322,8 +117006,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_8B_CS</name> - <description>Message Buffer 35 CS Register</description> + <name>MB2_16B_CS_H</name> + <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B0</addressOffset> <size>32</size> @@ -117397,8 +117081,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD12</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB35_8B_CS</name> + <description>Message Buffer 35 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B0</addressOffset> <size>32</size> @@ -117407,31 +117091,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -117470,8 +117189,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_ID</name> - <description>Message Buffer 14 ID Register</description> + <name>MB0_64B_WORD11_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B4</addressOffset> <size>32</size> @@ -117480,31 +117199,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_47</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_46</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_45</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_44</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_16B_WORD1</name> - <description>Message Buffer 23 WORD_16B Register</description> + <name>MB1_32B_WORD1_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B4</addressOffset> <size>32</size> @@ -117543,8 +117269,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_8B_ID</name> - <description>Message Buffer 35 ID Register</description> + <name>MB2_16B_ID_H</name> + <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B4</addressOffset> <size>32</size> @@ -117576,8 +117302,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD13</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB35_8B_ID</name> + <description>Message Buffer 35 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B4</addressOffset> <size>32</size> @@ -117586,38 +117312,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_54</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB14_32B_WORD0</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB0_64B_WORD12_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B8</addressOffset> <size>32</size> @@ -117626,28 +117345,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_51</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_50</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_49</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_48</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -117656,8 +117375,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_16B_WORD2</name> - <description>Message Buffer 23 WORD_16B Register</description> + <name>MB1_32B_WORD2_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B8</addressOffset> <size>32</size> @@ -117696,8 +117415,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_8B_WORD0</name> - <description>Message Buffer 35 WORD_8B Register</description> + <name>MB2_16B_WORD0_H</name> + <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B8</addressOffset> <size>32</size> @@ -117736,8 +117455,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD14</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB35_8B_WORD0</name> + <description>Message Buffer 35 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2B8</addressOffset> <size>32</size> @@ -117746,28 +117465,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -117816,8 +117535,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD1</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB0_64B_WORD13_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2BC</addressOffset> <size>32</size> @@ -117826,28 +117545,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_55</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_54</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_53</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_52</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -117856,8 +117575,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_16B_WORD3</name> - <description>Message Buffer 23 WORD_16B Register</description> + <name>MB1_32B_WORD3_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2BC</addressOffset> <size>32</size> @@ -117896,8 +117615,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_8B_WORD1</name> - <description>Message Buffer 35 WORD_8B Register</description> + <name>MB2_16B_WORD1_H</name> + <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2BC</addressOffset> <size>32</size> @@ -117936,8 +117655,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB7_64B_WORD15</name> - <description>Message Buffer 7 WORD_64B Register</description> + <name>MB35_8B_WORD1</name> + <description>Message Buffer 35 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2BC</addressOffset> <size>32</size> @@ -117946,28 +117665,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_62</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -118091,8 +117810,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD2</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB0_64B_WORD14_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C0</addressOffset> <size>32</size> @@ -118101,28 +117820,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_59</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_58</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_57</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_56</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -118131,8 +117850,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_CS</name> - <description>Message Buffer 24 CS Register</description> + <name>MB1_32B_WORD4_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C0</addressOffset> <size>32</size> @@ -118141,73 +117860,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB36_8B_CS</name> - <description>Message Buffer 36 CS Register</description> + <name>MB2_16B_WORD2_H</name> + <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C0</addressOffset> <size>32</size> @@ -118216,73 +117900,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB8_64B_CS</name> - <description>Message Buffer 8 CS Register</description> + <name>MB36_8B_CS</name> + <description>Message Buffer 36 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C0</addressOffset> <size>32</size> @@ -118389,8 +118038,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD3</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB0_64B_WORD15_H</name> + <description>Message Buffer 0 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C4</addressOffset> <size>32</size> @@ -118399,28 +118048,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_63</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_62</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_61</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_60</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -118429,8 +118078,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_ID</name> - <description>Message Buffer 24 ID Register</description> + <name>MB1_32B_WORD5_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C4</addressOffset> <size>32</size> @@ -118439,31 +118088,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_23</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_22</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_21</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_20</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB36_8B_ID</name> - <description>Message Buffer 36 ID Register</description> + <name>MB2_16B_WORD3_H</name> + <description>Message Buffer 2 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C4</addressOffset> <size>32</size> @@ -118472,31 +118128,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB8_64B_ID</name> - <description>Message Buffer 8 ID Register</description> + <name>MB36_8B_ID</name> + <description>Message Buffer 36 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C4</addressOffset> <size>32</size> @@ -118528,8 +118191,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD4</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB1_32B_WORD6_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C8</addressOffset> <size>32</size> @@ -118538,28 +118201,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -118568,8 +118231,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_WORD0</name> - <description>Message Buffer 24 WORD_16B Register</description> + <name>MB1_64B_CS_H</name> + <description>Message Buffer 1 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C8</addressOffset> <size>32</size> @@ -118578,31 +118241,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -118648,8 +118346,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD0</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_CS_H</name> + <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2C8</addressOffset> <size>32</size> @@ -118658,31 +118356,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -118728,8 +118461,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD5</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB1_32B_WORD7_H</name> + <description>Message Buffer 1 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2CC</addressOffset> <size>32</size> @@ -118738,28 +118471,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -118768,8 +118501,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_WORD1</name> - <description>Message Buffer 24 WORD_16B Register</description> + <name>MB1_64B_ID_H</name> + <description>Message Buffer 1 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2CC</addressOffset> <size>32</size> @@ -118778,31 +118511,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -118848,8 +118574,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD1</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_ID_H</name> + <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2CC</addressOffset> <size>32</size> @@ -118858,31 +118584,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -119003,8 +118722,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD6</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB1_64B_WORD0_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D0</addressOffset> <size>32</size> @@ -119013,28 +118732,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119043,8 +118762,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_WORD2</name> - <description>Message Buffer 24 WORD_16B Register</description> + <name>MB2_32B_CS_H</name> + <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D0</addressOffset> <size>32</size> @@ -119053,31 +118772,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -119158,8 +118912,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD2</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_WORD0_H</name> + <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D0</addressOffset> <size>32</size> @@ -119168,28 +118922,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119231,8 +118985,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB14_32B_WORD7</name> - <description>Message Buffer 14 WORD_32B Register</description> + <name>MB1_64B_WORD1_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D4</addressOffset> <size>32</size> @@ -119241,28 +118995,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119271,8 +119025,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB24_16B_WORD3</name> - <description>Message Buffer 24 WORD_16B Register</description> + <name>MB2_32B_ID_H</name> + <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D4</addressOffset> <size>32</size> @@ -119281,31 +119035,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -119344,8 +119091,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD3</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_WORD1_H</name> + <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D4</addressOffset> <size>32</size> @@ -119354,28 +119101,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119384,8 +119131,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_CS</name> - <description>Message Buffer 15 CS Register</description> + <name>MB1_64B_WORD2_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D8</addressOffset> <size>32</size> @@ -119394,73 +119141,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB25_16B_CS</name> - <description>Message Buffer 25 CS Register</description> + <name>MB2_32B_WORD0_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D8</addressOffset> <size>32</size> @@ -119469,66 +119181,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -119574,8 +119251,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD4</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_WORD2_H</name> + <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2D8</addressOffset> <size>32</size> @@ -119584,28 +119261,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119654,8 +119331,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_ID</name> - <description>Message Buffer 15 ID Register</description> + <name>MB1_64B_WORD3_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2DC</addressOffset> <size>32</size> @@ -119664,31 +119341,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB25_16B_ID</name> - <description>Message Buffer 25 ID Register</description> + <name>MB2_32B_WORD1_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2DC</addressOffset> <size>32</size> @@ -119697,24 +119381,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -119760,8 +119451,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD5</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB3_16B_WORD3_H</name> + <description>Message Buffer 3 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2DC</addressOffset> <size>32</size> @@ -119770,28 +119461,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119915,8 +119606,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD0</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD4_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E0</addressOffset> <size>32</size> @@ -119925,28 +119616,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -119955,8 +119646,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB25_16B_WORD0</name> - <description>Message Buffer 25 WORD_16B Register</description> + <name>MB2_32B_WORD2_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E0</addressOffset> <size>32</size> @@ -119965,28 +119656,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120070,8 +119761,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD6</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_CS_H</name> + <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E0</addressOffset> <size>32</size> @@ -120080,31 +119771,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -120143,8 +119869,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD1</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD5_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E4</addressOffset> <size>32</size> @@ -120153,28 +119879,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120183,8 +119909,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB25_16B_WORD1</name> - <description>Message Buffer 25 WORD_16B Register</description> + <name>MB2_32B_WORD3_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E4</addressOffset> <size>32</size> @@ -120193,28 +119919,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120256,8 +119982,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD7</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_ID_H</name> + <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E4</addressOffset> <size>32</size> @@ -120266,38 +119992,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB15_32B_WORD2</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD6_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E8</addressOffset> <size>32</size> @@ -120306,28 +120025,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120336,8 +120055,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB25_16B_WORD2</name> - <description>Message Buffer 25 WORD_16B Register</description> + <name>MB2_32B_WORD4_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E8</addressOffset> <size>32</size> @@ -120346,28 +120065,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120416,8 +120135,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD8</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_WORD0_H</name> + <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2E8</addressOffset> <size>32</size> @@ -120426,28 +120145,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120496,8 +120215,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD3</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD7_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2EC</addressOffset> <size>32</size> @@ -120506,28 +120225,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120536,8 +120255,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB25_16B_WORD3</name> - <description>Message Buffer 25 WORD_16B Register</description> + <name>MB2_32B_WORD5_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2EC</addressOffset> <size>32</size> @@ -120546,28 +120265,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120616,8 +120335,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD9</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_WORD1_H</name> + <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2EC</addressOffset> <size>32</size> @@ -120626,28 +120345,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120771,8 +120490,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD4</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD8_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F0</addressOffset> <size>32</size> @@ -120781,28 +120500,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_35</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_34</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_33</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_32</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -120811,8 +120530,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB26_16B_CS</name> - <description>Message Buffer 26 CS Register</description> + <name>MB2_32B_WORD6_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F0</addressOffset> <size>32</size> @@ -120821,66 +120540,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -120961,8 +120645,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD10</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_WORD2_H</name> + <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F0</addressOffset> <size>32</size> @@ -120971,28 +120655,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121034,8 +120718,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD5</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD9_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F4</addressOffset> <size>32</size> @@ -121044,28 +120728,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_39</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_38</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_37</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_36</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121074,8 +120758,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB26_16B_ID</name> - <description>Message Buffer 26 ID Register</description> + <name>MB2_32B_WORD7_H</name> + <description>Message Buffer 2 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F4</addressOffset> <size>32</size> @@ -121084,24 +120768,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_31</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_30</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_29</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_28</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -121140,8 +120831,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD11</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB4_16B_WORD3_H</name> + <description>Message Buffer 4 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F4</addressOffset> <size>32</size> @@ -121150,28 +120841,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_46</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121180,8 +120871,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD6</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD10_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F8</addressOffset> <size>32</size> @@ -121190,28 +120881,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_43</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_42</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_41</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_40</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121220,8 +120911,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB26_16B_WORD0</name> - <description>Message Buffer 26 WORD_16B Register</description> + <name>MB39_8B_WORD0</name> + <description>Message Buffer 39 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F8</addressOffset> <size>32</size> @@ -121260,8 +120951,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_8B_WORD0</name> - <description>Message Buffer 39 WORD_8B Register</description> + <name>MB3_32B_CS_H</name> + <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F8</addressOffset> <size>32</size> @@ -121270,38 +120961,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB8_64B_WORD12</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB5_16B_CS_H</name> + <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2F8</addressOffset> <size>32</size> @@ -121310,31 +121036,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -121380,8 +121141,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB15_32B_WORD7</name> - <description>Message Buffer 15 WORD_32B Register</description> + <name>MB1_64B_WORD11_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2FC</addressOffset> <size>32</size> @@ -121390,28 +121151,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121420,8 +121181,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB26_16B_WORD1</name> - <description>Message Buffer 26 WORD_16B Register</description> + <name>MB39_8B_WORD1</name> + <description>Message Buffer 39 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2FC</addressOffset> <size>32</size> @@ -121460,8 +121221,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_8B_WORD1</name> - <description>Message Buffer 39 WORD_8B Register</description> + <name>MB3_32B_ID_H</name> + <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2FC</addressOffset> <size>32</size> @@ -121470,38 +121231,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB8_64B_WORD13</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB5_16B_ID_H</name> + <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x2FC</addressOffset> <size>32</size> @@ -121510,31 +121264,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_54</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -121655,8 +121402,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_CS</name> - <description>Message Buffer 16 CS Register</description> + <name>MB1_64B_WORD12_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x300</addressOffset> <size>32</size> @@ -121665,73 +121412,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_51</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_50</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_49</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_48</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB26_16B_WORD2</name> - <description>Message Buffer 26 WORD_16B Register</description> + <name>MB3_32B_WORD0_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x300</addressOffset> <size>32</size> @@ -121740,28 +121452,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121845,8 +121557,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD14</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB5_16B_WORD0_H</name> + <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x300</addressOffset> <size>32</size> @@ -121855,28 +121567,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -121918,8 +121630,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_ID</name> - <description>Message Buffer 16 ID Register</description> + <name>MB1_64B_WORD13_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x304</addressOffset> <size>32</size> @@ -121928,31 +121640,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_55</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_54</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_53</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_52</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB26_16B_WORD3</name> - <description>Message Buffer 26 WORD_16B Register</description> + <name>MB3_32B_WORD1_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x304</addressOffset> <size>32</size> @@ -121961,28 +121680,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122024,8 +121743,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB8_64B_WORD15</name> - <description>Message Buffer 8 WORD_64B Register</description> + <name>MB5_16B_WORD1_H</name> + <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x304</addressOffset> <size>32</size> @@ -122034,28 +121753,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_62</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122064,8 +121783,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD0</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB1_64B_WORD14_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x308</addressOffset> <size>32</size> @@ -122074,28 +121793,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_59</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_58</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_57</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_56</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122104,8 +121823,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB27_16B_CS</name> - <description>Message Buffer 27 CS Register</description> + <name>MB3_32B_WORD2_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x308</addressOffset> <size>32</size> @@ -122114,66 +121833,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -122219,8 +121903,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_CS</name> - <description>Message Buffer 9 CS Register</description> + <name>MB5_16B_WORD2_H</name> + <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x308</addressOffset> <size>32</size> @@ -122229,66 +121913,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -122334,8 +121983,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD1</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB1_64B_WORD15_H</name> + <description>Message Buffer 1 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x30C</addressOffset> <size>32</size> @@ -122344,28 +121993,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_63</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_62</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_61</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_60</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122374,8 +122023,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB27_16B_ID</name> - <description>Message Buffer 27 ID Register</description> + <name>MB3_32B_WORD3_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x30C</addressOffset> <size>32</size> @@ -122384,24 +122033,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -122447,8 +122103,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_ID</name> - <description>Message Buffer 9 ID Register</description> + <name>MB5_16B_WORD3_H</name> + <description>Message Buffer 5 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x30C</addressOffset> <size>32</size> @@ -122457,24 +122113,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -122595,8 +122258,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD2</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_CS_H</name> + <description>Message Buffer 2 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x310</addressOffset> <size>32</size> @@ -122605,38 +122268,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB27_16B_WORD0</name> - <description>Message Buffer 27 WORD_16B Register</description> + <name>MB3_32B_WORD4_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x310</addressOffset> <size>32</size> @@ -122645,28 +122343,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122750,8 +122448,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD0</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_CS_H</name> + <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x310</addressOffset> <size>32</size> @@ -122760,31 +122458,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -122823,8 +122556,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD3</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_ID_H</name> + <description>Message Buffer 2 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x314</addressOffset> <size>32</size> @@ -122833,38 +122566,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB27_16B_WORD1</name> - <description>Message Buffer 27 WORD_16B Register</description> + <name>MB3_32B_WORD5_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x314</addressOffset> <size>32</size> @@ -122873,28 +122599,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -122936,8 +122662,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD1</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_ID_H</name> + <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x314</addressOffset> <size>32</size> @@ -122946,38 +122672,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB16_32B_WORD4</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_WORD0_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x318</addressOffset> <size>32</size> @@ -122986,28 +122705,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123016,8 +122735,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB27_16B_WORD2</name> - <description>Message Buffer 27 WORD_16B Register</description> + <name>MB3_32B_WORD6_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x318</addressOffset> <size>32</size> @@ -123026,28 +122745,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123096,8 +122815,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD2</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_WORD0_H</name> + <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x318</addressOffset> <size>32</size> @@ -123106,28 +122825,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123176,8 +122895,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD5</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_WORD1_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x31C</addressOffset> <size>32</size> @@ -123186,28 +122905,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123216,8 +122935,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB27_16B_WORD3</name> - <description>Message Buffer 27 WORD_16B Register</description> + <name>MB3_32B_WORD7_H</name> + <description>Message Buffer 3 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x31C</addressOffset> <size>32</size> @@ -123226,28 +122945,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123296,8 +123015,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD3</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_WORD1_H</name> + <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x31C</addressOffset> <size>32</size> @@ -123306,28 +123025,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123451,8 +123170,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD6</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_WORD2_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x320</addressOffset> <size>32</size> @@ -123461,28 +123180,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123491,8 +123210,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB28_16B_CS</name> - <description>Message Buffer 28 CS Register</description> + <name>MB42_8B_CS</name> + <description>Message Buffer 42 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x320</addressOffset> <size>32</size> @@ -123566,8 +123285,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB42_8B_CS</name> - <description>Message Buffer 42 CS Register</description> + <name>MB4_32B_CS_H</name> + <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x320</addressOffset> <size>32</size> @@ -123641,8 +123360,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD4</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_WORD2_H</name> + <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x320</addressOffset> <size>32</size> @@ -123651,28 +123370,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123714,8 +123433,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB16_32B_WORD7</name> - <description>Message Buffer 16 WORD_32B Register</description> + <name>MB2_64B_WORD3_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x324</addressOffset> <size>32</size> @@ -123724,28 +123443,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123754,8 +123473,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB28_16B_ID</name> - <description>Message Buffer 28 ID Register</description> + <name>MB42_8B_ID</name> + <description>Message Buffer 42 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x324</addressOffset> <size>32</size> @@ -123787,8 +123506,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB42_8B_ID</name> - <description>Message Buffer 42 ID Register</description> + <name>MB4_32B_ID_H</name> + <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x324</addressOffset> <size>32</size> @@ -123820,8 +123539,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD5</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB6_16B_WORD3_H</name> + <description>Message Buffer 6 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x324</addressOffset> <size>32</size> @@ -123830,28 +123549,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -123860,8 +123579,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_CS</name> - <description>Message Buffer 17 CS Register</description> + <name>MB2_64B_WORD4_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x328</addressOffset> <size>32</size> @@ -123870,73 +123589,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB28_16B_WORD0</name> - <description>Message Buffer 28 WORD_16B Register</description> + <name>MB42_8B_WORD0</name> + <description>Message Buffer 42 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x328</addressOffset> <size>32</size> @@ -123975,8 +123659,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB42_8B_WORD0</name> - <description>Message Buffer 42 WORD_8B Register</description> + <name>MB4_32B_WORD0_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x328</addressOffset> <size>32</size> @@ -124015,8 +123699,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD6</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB7_16B_CS_H</name> + <description>Message Buffer 7 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x328</addressOffset> <size>32</size> @@ -124025,31 +123709,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -124095,8 +123814,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_ID</name> - <description>Message Buffer 17 ID Register</description> + <name>MB2_64B_WORD5_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x32C</addressOffset> <size>32</size> @@ -124105,31 +123824,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_23</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_22</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_21</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_20</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB28_16B_WORD1</name> - <description>Message Buffer 28 WORD_16B Register</description> + <name>MB42_8B_WORD1</name> + <description>Message Buffer 42 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x32C</addressOffset> <size>32</size> @@ -124168,8 +123894,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB42_8B_WORD1</name> - <description>Message Buffer 42 WORD_8B Register</description> + <name>MB4_32B_WORD1_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x32C</addressOffset> <size>32</size> @@ -124208,8 +123934,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD7</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB7_16B_ID_H</name> + <description>Message Buffer 7 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x32C</addressOffset> <size>32</size> @@ -124218,31 +123944,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -124363,48 +124082,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD0</name> - <description>Message Buffer 17 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x330</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB28_16B_WORD2</name> - <description>Message Buffer 28 WORD_16B Register</description> + <name>MB2_64B_WORD6_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x330</addressOffset> <size>32</size> @@ -124413,28 +124092,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124518,8 +124197,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD8</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB4_32B_WORD2_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x330</addressOffset> <size>32</size> @@ -124528,28 +124207,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124558,41 +124237,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID43</name> - <description>Message Buffer 43 ID Register</description> + <name>MB7_16B_WORD0_H</name> + <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x334</addressOffset> + <addressOffset>0x330</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB17_32B_WORD1</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>ID43</name> + <description>Message Buffer 43 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x334</addressOffset> <size>32</size> @@ -124601,38 +124287,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB28_16B_WORD3</name> - <description>Message Buffer 28 WORD_16B Register</description> + <name>MB2_64B_WORD7_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x334</addressOffset> <size>32</size> @@ -124641,28 +124320,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124704,8 +124383,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD9</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB4_32B_WORD3_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x334</addressOffset> <size>32</size> @@ -124714,28 +124393,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124744,38 +124423,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD2</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>MB7_16B_WORD1_H</name> + <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x338</addressOffset> + <addressOffset>0x334</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124784,8 +124463,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB29_16B_CS</name> - <description>Message Buffer 29 CS Register</description> + <name>MB2_64B_WORD8_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x338</addressOffset> <size>32</size> @@ -124794,73 +124473,78 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_35</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_34</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_33</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_32</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB43_8B_WORD0</name> + <description>Message Buffer 43 WORD_8B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x338</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB43_8B_WORD0</name> - <description>Message Buffer 43 WORD_8B Register</description> + <name>MB4_32B_WORD4_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x338</addressOffset> <size>32</size> @@ -124869,28 +124553,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124899,8 +124583,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD10</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB7_16B_WORD2_H</name> + <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x338</addressOffset> <size>32</size> @@ -124909,28 +124593,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -124979,8 +124663,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD3</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>MB2_64B_WORD9_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x33C</addressOffset> <size>32</size> @@ -124989,28 +124673,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_39</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_38</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_37</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_36</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125019,8 +124703,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB29_16B_ID</name> - <description>Message Buffer 29 ID Register</description> + <name>MB43_8B_WORD1</name> + <description>Message Buffer 43 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x33C</addressOffset> <size>32</size> @@ -125029,31 +124713,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB43_8B_WORD1</name> - <description>Message Buffer 43 WORD_8B Register</description> + <name>MB4_32B_WORD5_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x33C</addressOffset> <size>32</size> @@ -125062,28 +124753,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125092,8 +124783,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD11</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB7_16B_WORD3_H</name> + <description>Message Buffer 7 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x33C</addressOffset> <size>32</size> @@ -125102,28 +124793,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_46</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125247,48 +124938,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD4</name> - <description>Message Buffer 17 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x340</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_19</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_18</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_17</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_16</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB29_16B_WORD0</name> - <description>Message Buffer 29 WORD_16B Register</description> + <name>MB2_64B_WORD10_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x340</addressOffset> <size>32</size> @@ -125297,28 +124948,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_43</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_42</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_41</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_40</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125402,8 +125053,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD12</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB4_32B_WORD6_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x340</addressOffset> <size>32</size> @@ -125412,28 +125063,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125442,41 +125093,83 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID44</name> - <description>Message Buffer 44 ID Register</description> + <name>MB8_16B_CS_H</name> + <description>Message Buffer 8 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x344</addressOffset> + <addressOffset>0x340</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB17_32B_WORD5</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>ID44</name> + <description>Message Buffer 44 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x344</addressOffset> <size>32</size> @@ -125485,38 +125178,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_22</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB29_16B_WORD1</name> - <description>Message Buffer 29 WORD_16B Register</description> + <name>MB2_64B_WORD11_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x344</addressOffset> <size>32</size> @@ -125525,28 +125211,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125588,8 +125274,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD13</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB4_32B_WORD7_H</name> + <description>Message Buffer 4 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x344</addressOffset> <size>32</size> @@ -125598,28 +125284,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_54</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125628,48 +125314,41 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD6</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>MB8_16B_ID_H</name> + <description>Message Buffer 8 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x348</addressOffset> + <addressOffset>0x344</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB29_16B_WORD2</name> - <description>Message Buffer 29 WORD_16B Register</description> + <name>MB2_64B_WORD12_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x348</addressOffset> <size>32</size> @@ -125678,28 +125357,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_51</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_50</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_49</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_48</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125748,8 +125427,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD14</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB5_32B_CS_H</name> + <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x348</addressOffset> <size>32</size> @@ -125758,38 +125437,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>WORD044</name> - <description>Message Buffer 44 WORD0 Register</description> + <name>MB8_16B_WORD0_H</name> + <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x348</addressOffset> <size>32</size> @@ -125828,38 +125542,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB17_32B_WORD7</name> - <description>Message Buffer 17 WORD_32B Register</description> + <name>WORD044</name> + <description>Message Buffer 44 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x34C</addressOffset> + <addressOffset>0x348</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125868,8 +125582,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB29_16B_WORD3</name> - <description>Message Buffer 29 WORD_16B Register</description> + <name>MB2_64B_WORD13_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x34C</addressOffset> <size>32</size> @@ -125878,28 +125592,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_55</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_54</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_53</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_52</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -125948,8 +125662,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB9_64B_WORD15</name> - <description>Message Buffer 9 WORD_64B Register</description> + <name>MB5_32B_ID_H</name> + <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x34C</addressOffset> <size>32</size> @@ -125958,28 +125672,61 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> + <bitOffset>0</bitOffset> + <bitWidth>18</bitWidth> + <access>read-write</access> + </field> + <field> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> + <access>read-write</access> + </field> + <field> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>MB8_16B_WORD1_H</name> + <description>Message Buffer 8 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x34C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_62</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -126103,8 +125850,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_CS</name> - <description>Message Buffer 10 CS Register</description> + <name>MB2_64B_WORD14_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x350</addressOffset> <size>32</size> @@ -126113,73 +125860,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_59</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_58</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_57</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_56</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_CS</name> - <description>Message Buffer 18 CS Register</description> + <name>MB45_8B_CS</name> + <description>Message Buffer 45 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x350</addressOffset> <size>32</size> @@ -126253,8 +125965,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB30_16B_CS</name> - <description>Message Buffer 30 CS Register</description> + <name>MB5_32B_WORD0_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x350</addressOffset> <size>32</size> @@ -126263,73 +125975,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB45_8B_CS</name> - <description>Message Buffer 45 CS Register</description> + <name>MB8_16B_WORD2_H</name> + <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x350</addressOffset> <size>32</size> @@ -126338,66 +126015,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -126436,8 +126078,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_ID</name> - <description>Message Buffer 10 ID Register</description> + <name>MB2_64B_WORD15_H</name> + <description>Message Buffer 2 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x354</addressOffset> <size>32</size> @@ -126446,31 +126088,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_63</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_62</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_61</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_60</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_ID</name> - <description>Message Buffer 18 ID Register</description> + <name>MB45_8B_ID</name> + <description>Message Buffer 45 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x354</addressOffset> <size>32</size> @@ -126502,8 +126151,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB30_16B_ID</name> - <description>Message Buffer 30 ID Register</description> + <name>MB5_32B_WORD1_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x354</addressOffset> <size>32</size> @@ -126512,31 +126161,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB45_8B_ID</name> - <description>Message Buffer 45 ID Register</description> + <name>MB8_16B_WORD3_H</name> + <description>Message Buffer 8 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x354</addressOffset> <size>32</size> @@ -126545,31 +126201,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB10_64B_WORD0</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB3_64B_CS_H</name> + <description>Message Buffer 3 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x358</addressOffset> <size>32</size> @@ -126578,38 +126241,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_WORD0</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB45_8B_WORD0</name> + <description>Message Buffer 45 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x358</addressOffset> <size>32</size> @@ -126648,8 +126346,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB30_16B_WORD0</name> - <description>Message Buffer 30 WORD_16B Register</description> + <name>MB5_32B_WORD2_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x358</addressOffset> <size>32</size> @@ -126658,28 +126356,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -126688,8 +126386,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB45_8B_WORD0</name> - <description>Message Buffer 45 WORD_8B Register</description> + <name>MB9_16B_CS_H</name> + <description>Message Buffer 9 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x358</addressOffset> <size>32</size> @@ -126698,31 +126396,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -126768,8 +126501,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD1</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB3_64B_ID_H</name> + <description>Message Buffer 3 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x35C</addressOffset> <size>32</size> @@ -126778,38 +126511,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_WORD1</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB45_8B_WORD1</name> + <description>Message Buffer 45 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x35C</addressOffset> <size>32</size> @@ -126848,8 +126574,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB30_16B_WORD1</name> - <description>Message Buffer 30 WORD_16B Register</description> + <name>MB5_32B_WORD3_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x35C</addressOffset> <size>32</size> @@ -126858,28 +126584,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -126888,8 +126614,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB45_8B_WORD1</name> - <description>Message Buffer 45 WORD_8B Register</description> + <name>MB9_16B_ID_H</name> + <description>Message Buffer 9 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x35C</addressOffset> <size>32</size> @@ -126898,31 +126624,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -127043,88 +126762,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD2</name> - <description>Message Buffer 10 WORD_64B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x360</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB18_32B_WORD2</name> - <description>Message Buffer 18 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x360</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB30_16B_WORD2</name> - <description>Message Buffer 30 WORD_16B Register</description> + <name>MB3_64B_WORD0_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x360</addressOffset> <size>32</size> @@ -127133,28 +126772,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127238,71 +126877,78 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID46</name> - <description>Message Buffer 46 ID Register</description> + <name>MB5_32B_WORD4_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x364</addressOffset> + <addressOffset>0x360</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB10_64B_WORD3</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB9_16B_WORD0_H</name> + <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x364</addressOffset> + <addressOffset>0x360</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127311,8 +126957,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_32B_WORD3</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>ID46</name> + <description>Message Buffer 46 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x364</addressOffset> <size>32</size> @@ -127321,38 +126967,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB30_16B_WORD3</name> - <description>Message Buffer 30 WORD_16B Register</description> + <name>MB3_64B_WORD1_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x364</addressOffset> <size>32</size> @@ -127361,28 +127000,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127424,38 +127063,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD4</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB5_32B_WORD5_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x368</addressOffset> + <addressOffset>0x364</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127464,38 +127103,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_32B_WORD4</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB9_16B_WORD1_H</name> + <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x368</addressOffset> + <addressOffset>0x364</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127504,8 +127143,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB31_16B_CS</name> - <description>Message Buffer 31 CS Register</description> + <name>MB3_64B_WORD2_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x368</addressOffset> <size>32</size> @@ -127514,73 +127153,118 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB46_8B_WORD0</name> + <description>Message Buffer 46 WORD_8B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x368</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>MB5_32B_WORD6_H</name> + <description>Message Buffer 5 WORD_32B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x368</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB46_8B_WORD0</name> - <description>Message Buffer 46 WORD_8B Register</description> + <name>MB9_16B_WORD2_H</name> + <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x368</addressOffset> <size>32</size> @@ -127589,28 +127273,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127659,8 +127343,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD5</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB3_64B_WORD3_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x36C</addressOffset> <size>32</size> @@ -127669,28 +127353,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127699,8 +127383,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB18_32B_WORD5</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB46_8B_WORD1</name> + <description>Message Buffer 46 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x36C</addressOffset> <size>32</size> @@ -127709,28 +127393,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127739,8 +127423,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB31_16B_ID</name> - <description>Message Buffer 31 ID Register</description> + <name>MB5_32B_WORD7_H</name> + <description>Message Buffer 5 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x36C</addressOffset> <size>32</size> @@ -127749,31 +127433,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_31</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_30</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_29</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_28</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB46_8B_WORD1</name> - <description>Message Buffer 46 WORD_8B Register</description> + <name>MB9_16B_WORD3_H</name> + <description>Message Buffer 9 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x36C</addressOffset> <size>32</size> @@ -127782,28 +127473,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -127927,8 +127618,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD6</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_CS_H</name> + <description>Message Buffer 10 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x370</addressOffset> <size>32</size> @@ -127937,38 +127628,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_WORD6</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB3_64B_WORD4_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x370</addressOffset> <size>32</size> @@ -127977,28 +127703,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128007,8 +127733,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB31_16B_WORD0</name> - <description>Message Buffer 31 WORD_16B Register</description> + <name>MB47_8B_CS</name> + <description>Message Buffer 47 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x370</addressOffset> <size>32</size> @@ -128017,38 +127743,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB47_8B_CS</name> - <description>Message Buffer 47 CS Register</description> + <name>MB6_32B_CS_H</name> + <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x370</addressOffset> <size>32</size> @@ -128155,8 +127916,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD7</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_ID_H</name> + <description>Message Buffer 10 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x374</addressOffset> <size>32</size> @@ -128165,38 +127926,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB18_32B_WORD7</name> - <description>Message Buffer 18 WORD_32B Register</description> + <name>MB3_64B_WORD5_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x374</addressOffset> <size>32</size> @@ -128205,28 +127959,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128235,8 +127989,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB31_16B_WORD1</name> - <description>Message Buffer 31 WORD_16B Register</description> + <name>MB47_8B_ID</name> + <description>Message Buffer 47 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x374</addressOffset> <size>32</size> @@ -128245,38 +127999,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB47_8B_ID</name> - <description>Message Buffer 47 ID Register</description> + <name>MB6_32B_ID_H</name> + <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x374</addressOffset> <size>32</size> @@ -128308,8 +128055,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD8</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_WORD0_H</name> + <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x378</addressOffset> <size>32</size> @@ -128318,28 +128065,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128348,8 +128095,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_32B_CS</name> - <description>Message Buffer 19 CS Register</description> + <name>MB3_64B_WORD6_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x378</addressOffset> <size>32</size> @@ -128358,73 +128105,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB31_16B_WORD2</name> - <description>Message Buffer 31 WORD_16B Register</description> + <name>MB47_8B_WORD0</name> + <description>Message Buffer 47 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x378</addressOffset> <size>32</size> @@ -128433,28 +128145,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128463,8 +128175,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB47_8B_WORD0</name> - <description>Message Buffer 47 WORD_8B Register</description> + <name>MB6_32B_WORD0_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x378</addressOffset> <size>32</size> @@ -128543,8 +128255,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD9</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_WORD1_H</name> + <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x37C</addressOffset> <size>32</size> @@ -128553,28 +128265,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128583,8 +128295,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_32B_ID</name> - <description>Message Buffer 19 ID Register</description> + <name>MB3_64B_WORD7_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x37C</addressOffset> <size>32</size> @@ -128593,31 +128305,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_31</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_30</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_29</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_28</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB31_16B_WORD3</name> - <description>Message Buffer 31 WORD_16B Register</description> + <name>MB47_8B_WORD1</name> + <description>Message Buffer 47 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x37C</addressOffset> <size>32</size> @@ -128626,28 +128345,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128656,8 +128375,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB47_8B_WORD1</name> - <description>Message Buffer 47 WORD_8B Register</description> + <name>MB6_32B_WORD1_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x37C</addressOffset> <size>32</size> @@ -128811,8 +128530,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD10</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_WORD2_H</name> + <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x380</addressOffset> <size>32</size> @@ -128821,28 +128540,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128851,8 +128570,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_32B_WORD0</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB3_64B_WORD8_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x380</addressOffset> <size>32</size> @@ -128861,28 +128580,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_35</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_34</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_33</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_32</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -128891,8 +128610,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_CS</name> - <description>Message Buffer 32 CS Register</description> + <name>MB48_8B_CS</name> + <description>Message Buffer 48 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x380</addressOffset> <size>32</size> @@ -128966,8 +128685,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB48_8B_CS</name> - <description>Message Buffer 48 CS Register</description> + <name>MB6_32B_WORD2_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x380</addressOffset> <size>32</size> @@ -128976,66 +128695,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -129074,8 +128758,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD11</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB10_16B_WORD3_H</name> + <description>Message Buffer 10 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x384</addressOffset> <size>32</size> @@ -129084,28 +128768,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_46</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129114,8 +128798,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB19_32B_WORD1</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB3_64B_WORD9_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x384</addressOffset> <size>32</size> @@ -129124,28 +128808,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_39</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_38</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_37</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_36</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129154,8 +128838,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_ID</name> - <description>Message Buffer 32 ID Register</description> + <name>MB48_8B_ID</name> + <description>Message Buffer 48 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x384</addressOffset> <size>32</size> @@ -129187,8 +128871,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB48_8B_ID</name> - <description>Message Buffer 48 ID Register</description> + <name>MB6_32B_WORD3_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x384</addressOffset> <size>32</size> @@ -129197,31 +128881,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB10_64B_WORD12</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB11_16B_CS_H</name> + <description>Message Buffer 11 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x388</addressOffset> <size>32</size> @@ -129230,38 +128921,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB19_32B_WORD2</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB3_64B_WORD10_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x388</addressOffset> <size>32</size> @@ -129270,28 +128996,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_43</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_42</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_41</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_40</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129300,8 +129026,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_WORD0</name> - <description>Message Buffer 32 WORD_16B Register</description> + <name>MB48_8B_WORD0</name> + <description>Message Buffer 48 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x388</addressOffset> <size>32</size> @@ -129340,8 +129066,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB48_8B_WORD0</name> - <description>Message Buffer 48 WORD_8B Register</description> + <name>MB6_32B_WORD4_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x388</addressOffset> <size>32</size> @@ -129350,28 +129076,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129420,8 +129146,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD13</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>MB11_16B_ID_H</name> + <description>Message Buffer 11 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x38C</addressOffset> <size>32</size> @@ -129430,38 +129156,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_54</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB19_32B_WORD3</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB3_64B_WORD11_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x38C</addressOffset> <size>32</size> @@ -129470,28 +129189,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129500,8 +129219,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_WORD1</name> - <description>Message Buffer 32 WORD_16B Register</description> + <name>MB48_8B_WORD1</name> + <description>Message Buffer 48 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x38C</addressOffset> <size>32</size> @@ -129540,8 +129259,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB48_8B_WORD1</name> - <description>Message Buffer 48 WORD_8B Register</description> + <name>MB6_32B_WORD5_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x38C</addressOffset> <size>32</size> @@ -129550,28 +129269,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129695,48 +129414,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB10_64B_WORD14</name> - <description>Message Buffer 10 WORD_64B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x390</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_59</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_58</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_57</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_56</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB19_32B_WORD4</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB11_16B_WORD0_H</name> + <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x390</addressOffset> <size>32</size> @@ -129745,28 +129424,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129775,8 +129454,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_WORD2</name> - <description>Message Buffer 32 WORD_16B Register</description> + <name>MB3_64B_WORD12_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x390</addressOffset> <size>32</size> @@ -129785,28 +129464,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_51</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_50</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_49</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_48</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -129890,41 +129569,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID49</name> - <description>Message Buffer 49 ID Register</description> + <name>MB6_32B_WORD6_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x394</addressOffset> + <addressOffset>0x390</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB10_64B_WORD15</name> - <description>Message Buffer 10 WORD_64B Register</description> + <name>ID49</name> + <description>Message Buffer 49 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x394</addressOffset> <size>32</size> @@ -129933,38 +129619,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_62</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB19_32B_WORD5</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB11_16B_WORD1_H</name> + <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x394</addressOffset> <size>32</size> @@ -129973,28 +129652,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -130003,8 +129682,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB32_16B_WORD3</name> - <description>Message Buffer 32 WORD_16B Register</description> + <name>MB3_64B_WORD13_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x394</addressOffset> <size>32</size> @@ -130013,28 +129692,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_55</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_54</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_53</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_52</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -130076,83 +129755,128 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_CS</name> - <description>Message Buffer 11 CS Register</description> + <name>MB6_32B_WORD7_H</name> + <description>Message Buffer 6 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x398</addressOffset> + <addressOffset>0x394</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_31</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> + <name>DATA_BYTE_30</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_29</name> + <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_28</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB11_16B_WORD2_H</name> + <description>Message Buffer 11 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x398</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB3_64B_WORD14_H</name> + <description>Message Buffer 3 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x398</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_59</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_58</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_57</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_56</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB19_32B_WORD6</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB49_8B_WORD0</name> + <description>Message Buffer 49 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x398</addressOffset> <size>32</size> @@ -130161,28 +129885,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -130191,8 +129915,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_CS</name> - <description>Message Buffer 33 CS Register</description> + <name>MB7_32B_CS_H</name> + <description>Message Buffer 7 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x398</addressOffset> <size>32</size> @@ -130266,8 +129990,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB49_8B_WORD0</name> - <description>Message Buffer 49 WORD_8B Register</description> + <name>WORD049</name> + <description>Message Buffer 49 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x398</addressOffset> <size>32</size> @@ -130306,38 +130030,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>WORD049</name> - <description>Message Buffer 49 WORD0 Register</description> + <name>MB11_16B_WORD3_H</name> + <description>Message Buffer 11 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x398</addressOffset> + <addressOffset>0x39C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -130346,8 +130070,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_ID</name> - <description>Message Buffer 11 ID Register</description> + <name>MB3_64B_WORD15_H</name> + <description>Message Buffer 3 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x39C</addressOffset> <size>32</size> @@ -130356,31 +130080,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_63</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_62</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_61</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_60</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB19_32B_WORD7</name> - <description>Message Buffer 19 WORD_32B Register</description> + <name>MB49_8B_WORD1</name> + <description>Message Buffer 49 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x39C</addressOffset> <size>32</size> @@ -130389,28 +130120,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -130419,8 +130150,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_ID</name> - <description>Message Buffer 33 ID Register</description> + <name>MB7_32B_ID_H</name> + <description>Message Buffer 7 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x39C</addressOffset> <size>32</size> @@ -130452,46 +130183,6 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB49_8B_WORD1</name> - <description>Message Buffer 49 WORD_8B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x39C</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> <name>WORD149</name> <description>Message Buffer 49 WORD1 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -130607,48 +130298,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD0</name> - <description>Message Buffer 11 WORD_64B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3A0</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB20_32B_CS</name> - <description>Message Buffer 20 CS Register</description> + <name>MB12_16B_CS_H</name> + <description>Message Buffer 12 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A0</addressOffset> <size>32</size> @@ -130722,8 +130373,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_WORD0</name> - <description>Message Buffer 33 WORD_16B Register</description> + <name>MB4_64B_CS_H</name> + <description>Message Buffer 4 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A0</addressOffset> <size>32</size> @@ -130732,31 +130383,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -130837,41 +130523,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID50</name> - <description>Message Buffer 50 ID Register</description> + <name>MB7_32B_WORD0_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3A4</addressOffset> + <addressOffset>0x3A0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB11_64B_WORD1</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>ID50</name> + <description>Message Buffer 50 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A4</addressOffset> <size>32</size> @@ -130880,38 +130573,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB20_32B_ID</name> - <description>Message Buffer 20 ID Register</description> + <name>MB12_16B_ID_H</name> + <description>Message Buffer 12 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A4</addressOffset> <size>32</size> @@ -130943,8 +130629,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_WORD1</name> - <description>Message Buffer 33 WORD_16B Register</description> + <name>MB4_64B_ID_H</name> + <description>Message Buffer 4 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A4</addressOffset> <size>32</size> @@ -130953,31 +130639,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -131016,38 +130695,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD2</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB7_32B_WORD1_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3A8</addressOffset> + <addressOffset>0x3A4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131056,8 +130735,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD0</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB12_16B_WORD0_H</name> + <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A8</addressOffset> <size>32</size> @@ -131096,8 +130775,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_WORD2</name> - <description>Message Buffer 33 WORD_16B Register</description> + <name>MB4_64B_WORD0_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3A8</addressOffset> <size>32</size> @@ -131106,28 +130785,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131176,6 +130855,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB7_32B_WORD2_H</name> + <description>Message Buffer 7 WORD_32B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x3A8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD050</name> <description>Message Buffer 50 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -131216,8 +130935,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD3</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB12_16B_WORD1_H</name> + <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3AC</addressOffset> <size>32</size> @@ -131226,28 +130945,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131256,8 +130975,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD1</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD1_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3AC</addressOffset> <size>32</size> @@ -131296,8 +131015,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB33_16B_WORD3</name> - <description>Message Buffer 33 WORD_16B Register</description> + <name>MB50_8B_WORD1</name> + <description>Message Buffer 50 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3AC</addressOffset> <size>32</size> @@ -131306,28 +131025,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131336,8 +131055,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB50_8B_WORD1</name> - <description>Message Buffer 50 WORD_8B Register</description> + <name>MB7_32B_WORD3_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3AC</addressOffset> <size>32</size> @@ -131346,28 +131065,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131491,8 +131210,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD4</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB12_16B_WORD2_H</name> + <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B0</addressOffset> <size>32</size> @@ -131501,28 +131220,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131531,8 +131250,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD2</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD2_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B0</addressOffset> <size>32</size> @@ -131571,8 +131290,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_CS</name> - <description>Message Buffer 34 CS Register</description> + <name>MB51_8B_CS</name> + <description>Message Buffer 51 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B0</addressOffset> <size>32</size> @@ -131646,8 +131365,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB51_8B_CS</name> - <description>Message Buffer 51 CS Register</description> + <name>MB7_32B_WORD4_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B0</addressOffset> <size>32</size> @@ -131656,66 +131375,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -131754,8 +131438,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD5</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB12_16B_WORD3_H</name> + <description>Message Buffer 12 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B4</addressOffset> <size>32</size> @@ -131764,28 +131448,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -131794,8 +131478,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD3</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD3_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B4</addressOffset> <size>32</size> @@ -131834,8 +131518,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_ID</name> - <description>Message Buffer 34 ID Register</description> + <name>MB51_8B_ID</name> + <description>Message Buffer 51 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B4</addressOffset> <size>32</size> @@ -131867,8 +131551,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB51_8B_ID</name> - <description>Message Buffer 51 ID Register</description> + <name>MB7_32B_WORD5_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B4</addressOffset> <size>32</size> @@ -131877,31 +131561,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_23</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_22</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_21</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_20</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB11_64B_WORD6</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_CS_H</name> + <description>Message Buffer 13 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B8</addressOffset> <size>32</size> @@ -131910,38 +131601,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB20_32B_WORD4</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD4_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B8</addressOffset> <size>32</size> @@ -131980,8 +131706,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_WORD0</name> - <description>Message Buffer 34 WORD_16B Register</description> + <name>MB51_8B_WORD0</name> + <description>Message Buffer 51 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B8</addressOffset> <size>32</size> @@ -132020,8 +131746,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB51_8B_WORD0</name> - <description>Message Buffer 51 WORD_8B Register</description> + <name>MB7_32B_WORD6_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3B8</addressOffset> <size>32</size> @@ -132030,28 +131756,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -132100,8 +131826,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD7</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_ID_H</name> + <description>Message Buffer 13 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3BC</addressOffset> <size>32</size> @@ -132110,38 +131836,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB20_32B_WORD5</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD5_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3BC</addressOffset> <size>32</size> @@ -132180,8 +131899,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_WORD1</name> - <description>Message Buffer 34 WORD_16B Register</description> + <name>MB51_8B_WORD1</name> + <description>Message Buffer 51 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3BC</addressOffset> <size>32</size> @@ -132220,8 +131939,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB51_8B_WORD1</name> - <description>Message Buffer 51 WORD_8B Register</description> + <name>MB7_32B_WORD7_H</name> + <description>Message Buffer 7 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3BC</addressOffset> <size>32</size> @@ -132230,28 +131949,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -132375,8 +132094,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD8</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_WORD0_H</name> + <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C0</addressOffset> <size>32</size> @@ -132385,28 +132104,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -132415,8 +132134,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD6</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD6_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C0</addressOffset> <size>32</size> @@ -132455,8 +132174,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_WORD2</name> - <description>Message Buffer 34 WORD_16B Register</description> + <name>MB52_8B_CS</name> + <description>Message Buffer 52 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C0</addressOffset> <size>32</size> @@ -132465,38 +132184,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB52_8B_CS</name> - <description>Message Buffer 52 CS Register</description> + <name>MB8_32B_CS_H</name> + <description>Message Buffer 8 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C0</addressOffset> <size>32</size> @@ -132603,8 +132357,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD9</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_WORD1_H</name> + <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C4</addressOffset> <size>32</size> @@ -132613,28 +132367,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -132643,8 +132397,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB20_32B_WORD7</name> - <description>Message Buffer 20 WORD_32B Register</description> + <name>MB4_64B_WORD7_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C4</addressOffset> <size>32</size> @@ -132683,8 +132437,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB34_16B_WORD3</name> - <description>Message Buffer 34 WORD_16B Register</description> + <name>MB52_8B_ID</name> + <description>Message Buffer 52 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C4</addressOffset> <size>32</size> @@ -132693,38 +132447,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB52_8B_ID</name> - <description>Message Buffer 52 ID Register</description> + <name>MB8_32B_ID_H</name> + <description>Message Buffer 8 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C4</addressOffset> <size>32</size> @@ -132756,8 +132503,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD10</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_WORD2_H</name> + <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C8</addressOffset> <size>32</size> @@ -132766,28 +132513,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -132796,8 +132543,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_CS</name> - <description>Message Buffer 21 CS Register</description> + <name>MB4_64B_WORD8_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C8</addressOffset> <size>32</size> @@ -132806,73 +132553,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_35</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_34</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_33</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_32</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB35_16B_CS</name> - <description>Message Buffer 35 CS Register</description> + <name>MB52_8B_WORD0</name> + <description>Message Buffer 52 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C8</addressOffset> <size>32</size> @@ -132881,73 +132593,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB52_8B_WORD0</name> - <description>Message Buffer 52 WORD_8B Register</description> + <name>MB8_32B_WORD0_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3C8</addressOffset> <size>32</size> @@ -133026,8 +132703,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD11</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB13_16B_WORD3_H</name> + <description>Message Buffer 13 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3CC</addressOffset> <size>32</size> @@ -133036,28 +132713,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_46</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133066,8 +132743,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_ID</name> - <description>Message Buffer 21 ID Register</description> + <name>MB4_64B_WORD9_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3CC</addressOffset> <size>32</size> @@ -133076,31 +132753,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_39</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_38</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_37</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_36</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB35_16B_ID</name> - <description>Message Buffer 35 ID Register</description> + <name>MB52_8B_WORD1</name> + <description>Message Buffer 52 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3CC</addressOffset> <size>32</size> @@ -133109,31 +132793,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB52_8B_WORD1</name> - <description>Message Buffer 52 WORD_8B Register</description> + <name>MB8_32B_WORD1_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3CC</addressOffset> <size>32</size> @@ -133287,8 +132978,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD12</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB14_16B_CS_H</name> + <description>Message Buffer 14 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D0</addressOffset> <size>32</size> @@ -133297,78 +132988,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB21_32B_WORD0</name> - <description>Message Buffer 21 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3D0</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB35_16B_WORD0</name> - <description>Message Buffer 35 WORD_16B Register</description> + <name>MB4_64B_WORD10_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D0</addressOffset> <size>32</size> @@ -133377,28 +133063,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_43</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_42</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_41</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_40</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133482,41 +133168,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID53</name> - <description>Message Buffer 53 ID Register</description> + <name>MB8_32B_WORD2_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3D4</addressOffset> + <addressOffset>0x3D0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB11_64B_WORD13</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>ID53</name> + <description>Message Buffer 53 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D4</addressOffset> <size>32</size> @@ -133525,38 +133218,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_54</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB21_32B_WORD1</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB14_16B_ID_H</name> + <description>Message Buffer 14 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D4</addressOffset> <size>32</size> @@ -133565,38 +133251,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB35_16B_WORD1</name> - <description>Message Buffer 35 WORD_16B Register</description> + <name>MB4_64B_WORD11_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D4</addressOffset> <size>32</size> @@ -133605,28 +133284,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133668,38 +133347,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD14</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>MB8_32B_WORD3_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3D8</addressOffset> + <addressOffset>0x3D4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133708,8 +133387,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD2</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB14_16B_WORD0_H</name> + <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D8</addressOffset> <size>32</size> @@ -133718,28 +133397,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133748,8 +133427,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_16B_WORD2</name> - <description>Message Buffer 35 WORD_16B Register</description> + <name>MB4_64B_WORD12_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D8</addressOffset> <size>32</size> @@ -133758,28 +133437,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_51</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_50</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_49</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_48</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133828,8 +133507,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>WORD053</name> - <description>Message Buffer 53 WORD0 Register</description> + <name>MB8_32B_WORD4_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3D8</addressOffset> <size>32</size> @@ -133838,28 +133517,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133868,38 +133547,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB11_64B_WORD15</name> - <description>Message Buffer 11 WORD_64B Register</description> + <name>WORD053</name> + <description>Message Buffer 53 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3DC</addressOffset> + <addressOffset>0x3D8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_62</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133908,8 +133587,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD3</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB14_16B_WORD1_H</name> + <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3DC</addressOffset> <size>32</size> @@ -133918,28 +133597,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -133948,8 +133627,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB35_16B_WORD3</name> - <description>Message Buffer 35 WORD_16B Register</description> + <name>MB4_64B_WORD13_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3DC</addressOffset> <size>32</size> @@ -133958,28 +133637,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_55</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_54</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_53</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_52</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134028,8 +133707,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>WORD153</name> - <description>Message Buffer 53 WORD1 Register</description> + <name>MB8_32B_WORD5_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3DC</addressOffset> <size>32</size> @@ -134038,28 +133717,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134068,83 +133747,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>CS54</name> - <description>Message Buffer 54 CS Register</description> + <name>WORD153</name> + <description>Message Buffer 53 WORD1 Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3E0</addressOffset> + <addressOffset>0x3DC</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_CS</name> - <description>Message Buffer 12 CS Register</description> + <name>CS54</name> + <description>Message Buffer 54 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E0</addressOffset> <size>32</size> @@ -134218,8 +133862,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD4</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB14_16B_WORD2_H</name> + <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E0</addressOffset> <size>32</size> @@ -134228,28 +133872,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134258,8 +133902,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB36_16B_CS</name> - <description>Message Buffer 36 CS Register</description> + <name>MB4_64B_WORD14_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E0</addressOffset> <size>32</size> @@ -134268,66 +133912,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_59</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_58</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_57</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_56</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -134408,41 +134017,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID54</name> - <description>Message Buffer 54 ID Register</description> + <name>MB8_32B_WORD6_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3E4</addressOffset> + <addressOffset>0x3E0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_ID</name> - <description>Message Buffer 12 ID Register</description> + <name>ID54</name> + <description>Message Buffer 54 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E4</addressOffset> <size>32</size> @@ -134474,8 +134090,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD5</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB14_16B_WORD3_H</name> + <description>Message Buffer 14 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E4</addressOffset> <size>32</size> @@ -134484,28 +134100,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134514,8 +134130,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB36_16B_ID</name> - <description>Message Buffer 36 ID Register</description> + <name>MB4_64B_WORD15_H</name> + <description>Message Buffer 4 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E4</addressOffset> <size>32</size> @@ -134524,24 +134140,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_63</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_62</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_61</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_60</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -134580,38 +134203,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD0</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB8_32B_WORD7_H</name> + <description>Message Buffer 8 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3E8</addressOffset> + <addressOffset>0x3E4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134620,8 +134243,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD6</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB15_16B_CS_H</name> + <description>Message Buffer 15 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E8</addressOffset> <size>32</size> @@ -134630,38 +134253,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB36_16B_WORD0</name> - <description>Message Buffer 36 WORD_16B Register</description> + <name>MB54_8B_WORD0</name> + <description>Message Buffer 54 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E8</addressOffset> <size>32</size> @@ -134700,8 +134358,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB54_8B_WORD0</name> - <description>Message Buffer 54 WORD_8B Register</description> + <name>MB5_64B_CS_H</name> + <description>Message Buffer 5 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E8</addressOffset> <size>32</size> @@ -134710,38 +134368,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>WORD054</name> - <description>Message Buffer 54 WORD0 Register</description> + <name>MB9_32B_CS_H</name> + <description>Message Buffer 9 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3E8</addressOffset> <size>32</size> @@ -134750,68 +134443,103 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_WORD1</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>WORD054</name> + <description>Message Buffer 54 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x3EC</addressOffset> + <addressOffset>0x3E8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -134820,8 +134548,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB21_32B_WORD7</name> - <description>Message Buffer 21 WORD_32B Register</description> + <name>MB15_16B_ID_H</name> + <description>Message Buffer 15 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3EC</addressOffset> <size>32</size> @@ -134830,38 +134558,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_30</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB36_16B_WORD1</name> - <description>Message Buffer 36 WORD_16B Register</description> + <name>MB54_8B_WORD1</name> + <description>Message Buffer 54 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3EC</addressOffset> <size>32</size> @@ -134900,8 +134621,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB54_8B_WORD1</name> - <description>Message Buffer 54 WORD_8B Register</description> + <name>MB5_64B_ID_H</name> + <description>Message Buffer 5 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3EC</addressOffset> <size>32</size> @@ -134910,31 +134631,57 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB9_32B_ID_H</name> + <description>Message Buffer 9 ID Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x3EC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> + <bitOffset>0</bitOffset> + <bitWidth>18</bitWidth> + <access>read-write</access> + </field> + <field> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> + <access>read-write</access> + </field> + <field> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -135055,8 +134802,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD2</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB15_16B_WORD0_H</name> + <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F0</addressOffset> <size>32</size> @@ -135065,28 +134812,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135095,8 +134842,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_CS</name> - <description>Message Buffer 22 CS Register</description> + <name>MB55_8B_CS</name> + <description>Message Buffer 55 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F0</addressOffset> <size>32</size> @@ -135170,8 +134917,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB36_16B_WORD2</name> - <description>Message Buffer 36 WORD_16B Register</description> + <name>MB5_64B_WORD0_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F0</addressOffset> <size>32</size> @@ -135180,28 +134927,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135210,8 +134957,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB55_8B_CS</name> - <description>Message Buffer 55 CS Register</description> + <name>MB9_32B_WORD0_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F0</addressOffset> <size>32</size> @@ -135220,66 +134967,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -135318,8 +135030,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD3</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB15_16B_WORD1_H</name> + <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F4</addressOffset> <size>32</size> @@ -135328,28 +135040,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135358,8 +135070,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_ID</name> - <description>Message Buffer 22 ID Register</description> + <name>MB55_8B_ID</name> + <description>Message Buffer 55 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F4</addressOffset> <size>32</size> @@ -135391,8 +135103,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB36_16B_WORD3</name> - <description>Message Buffer 36 WORD_16B Register</description> + <name>MB5_64B_WORD1_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F4</addressOffset> <size>32</size> @@ -135401,28 +135113,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135431,8 +135143,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB55_8B_ID</name> - <description>Message Buffer 55 ID Register</description> + <name>MB9_32B_WORD1_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F4</addressOffset> <size>32</size> @@ -135441,31 +135153,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_WORD4</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB15_16B_WORD2_H</name> + <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F8</addressOffset> <size>32</size> @@ -135474,28 +135193,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135504,8 +135223,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_WORD0</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB55_8B_WORD0</name> + <description>Message Buffer 55 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F8</addressOffset> <size>32</size> @@ -135544,8 +135263,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB37_16B_CS</name> - <description>Message Buffer 37 CS Register</description> + <name>MB5_64B_WORD2_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F8</addressOffset> <size>32</size> @@ -135554,73 +135273,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB55_8B_WORD0</name> - <description>Message Buffer 55 WORD_8B Register</description> + <name>MB9_32B_WORD2_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3F8</addressOffset> <size>32</size> @@ -135629,28 +135313,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135699,8 +135383,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD5</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB15_16B_WORD3_H</name> + <description>Message Buffer 15 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3FC</addressOffset> <size>32</size> @@ -135709,28 +135393,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135739,8 +135423,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_WORD1</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB55_8B_WORD1</name> + <description>Message Buffer 55 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3FC</addressOffset> <size>32</size> @@ -135779,8 +135463,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB37_16B_ID</name> - <description>Message Buffer 37 ID Register</description> + <name>MB5_64B_WORD3_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3FC</addressOffset> <size>32</size> @@ -135789,31 +135473,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB55_8B_WORD1</name> - <description>Message Buffer 55 WORD_8B Register</description> + <name>MB9_32B_WORD3_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x3FC</addressOffset> <size>32</size> @@ -135822,28 +135513,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -135967,8 +135658,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD6</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB16_16B_CS_H</name> + <description>Message Buffer 16 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x400</addressOffset> <size>32</size> @@ -135977,111 +135668,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_26</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> - <description>Data byte 2 of Rx/Tx frame.</description> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_24</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB22_32B_WORD2</name> - <description>Message Buffer 22 WORD_32B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x400</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>MB37_16B_WORD0</name> - <description>Message Buffer 37 WORD_16B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x400</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -136162,71 +135808,78 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID56</name> - <description>Message Buffer 56 ID Register</description> + <name>MB5_64B_WORD4_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x404</addressOffset> + <addressOffset>0x400</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_WORD7</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB9_32B_WORD4_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x404</addressOffset> + <addressOffset>0x400</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136235,8 +135888,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_WORD3</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>ID56</name> + <description>Message Buffer 56 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x404</addressOffset> <size>32</size> @@ -136245,38 +135898,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB37_16B_WORD1</name> - <description>Message Buffer 37 WORD_16B Register</description> + <name>MB16_16B_ID_H</name> + <description>Message Buffer 16 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x404</addressOffset> <size>32</size> @@ -136285,31 +135931,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -136348,38 +135987,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD8</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB5_64B_WORD5_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x408</addressOffset> + <addressOffset>0x404</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136388,38 +136027,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_WORD4</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB9_32B_WORD5_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x408</addressOffset> + <addressOffset>0x404</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136428,8 +136067,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB37_16B_WORD2</name> - <description>Message Buffer 37 WORD_16B Register</description> + <name>MB16_16B_WORD0_H</name> + <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x408</addressOffset> <size>32</size> @@ -136438,28 +136077,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136508,6 +136147,86 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB5_64B_WORD6_H</name> + <description>Message Buffer 5 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x408</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>MB9_32B_WORD6_H</name> + <description>Message Buffer 9 WORD_32B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x408</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD056</name> <description>Message Buffer 56 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -136548,8 +136267,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD9</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB16_16B_WORD1_H</name> + <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x40C</addressOffset> <size>32</size> @@ -136558,28 +136277,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136588,8 +136307,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB22_32B_WORD5</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB56_8B_WORD1</name> + <description>Message Buffer 56 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x40C</addressOffset> <size>32</size> @@ -136598,28 +136317,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136628,8 +136347,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB37_16B_WORD3</name> - <description>Message Buffer 37 WORD_16B Register</description> + <name>MB5_64B_WORD7_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x40C</addressOffset> <size>32</size> @@ -136638,28 +136357,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136668,8 +136387,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB56_8B_WORD1</name> - <description>Message Buffer 56 WORD_8B Register</description> + <name>MB9_32B_WORD7_H</name> + <description>Message Buffer 9 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x40C</addressOffset> <size>32</size> @@ -136678,28 +136397,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136823,8 +136542,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD10</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB10_32B_CS_H</name> + <description>Message Buffer 10 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x410</addressOffset> <size>32</size> @@ -136833,38 +136552,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB22_32B_WORD6</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB16_16B_WORD2_H</name> + <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x410</addressOffset> <size>32</size> @@ -136873,28 +136627,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -136903,8 +136657,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_CS</name> - <description>Message Buffer 38 CS Register</description> + <name>MB57_8B_CS</name> + <description>Message Buffer 57 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x410</addressOffset> <size>32</size> @@ -136978,8 +136732,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB57_8B_CS</name> - <description>Message Buffer 57 CS Register</description> + <name>MB5_64B_WORD8_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x410</addressOffset> <size>32</size> @@ -136988,66 +136742,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_35</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_34</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_33</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_32</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -137086,8 +136805,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD11</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB10_32B_ID_H</name> + <description>Message Buffer 10 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x414</addressOffset> <size>32</size> @@ -137096,38 +136815,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_46</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB22_32B_WORD7</name> - <description>Message Buffer 22 WORD_32B Register</description> + <name>MB16_16B_WORD3_H</name> + <description>Message Buffer 16 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x414</addressOffset> <size>32</size> @@ -137136,28 +136848,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137166,8 +136878,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_ID</name> - <description>Message Buffer 38 ID Register</description> + <name>MB57_8B_ID</name> + <description>Message Buffer 57 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x414</addressOffset> <size>32</size> @@ -137199,8 +136911,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB57_8B_ID</name> - <description>Message Buffer 57 ID Register</description> + <name>MB5_64B_WORD9_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x414</addressOffset> <size>32</size> @@ -137209,31 +136921,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_39</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_38</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_37</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_36</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_WORD12</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB10_32B_WORD0_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x418</addressOffset> <size>32</size> @@ -137242,28 +136961,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137272,8 +136991,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_32B_CS</name> - <description>Message Buffer 23 CS Register</description> + <name>MB17_16B_CS_H</name> + <description>Message Buffer 17 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x418</addressOffset> <size>32</size> @@ -137347,8 +137066,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_WORD0</name> - <description>Message Buffer 38 WORD_16B Register</description> + <name>MB57_8B_WORD0</name> + <description>Message Buffer 57 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x418</addressOffset> <size>32</size> @@ -137387,8 +137106,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB57_8B_WORD0</name> - <description>Message Buffer 57 WORD_8B Register</description> + <name>MB5_64B_WORD10_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x418</addressOffset> <size>32</size> @@ -137397,28 +137116,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_43</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_42</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_41</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_40</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137467,8 +137186,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD13</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB10_32B_WORD1_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x41C</addressOffset> <size>32</size> @@ -137477,28 +137196,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_54</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137507,8 +137226,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_32B_ID</name> - <description>Message Buffer 23 ID Register</description> + <name>MB17_16B_ID_H</name> + <description>Message Buffer 17 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x41C</addressOffset> <size>32</size> @@ -137540,8 +137259,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_WORD1</name> - <description>Message Buffer 38 WORD_16B Register</description> + <name>MB57_8B_WORD1</name> + <description>Message Buffer 57 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x41C</addressOffset> <size>32</size> @@ -137580,8 +137299,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB57_8B_WORD1</name> - <description>Message Buffer 57 WORD_8B Register</description> + <name>MB5_64B_WORD11_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x41C</addressOffset> <size>32</size> @@ -137590,28 +137309,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137735,8 +137454,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB12_64B_WORD14</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>MB10_32B_WORD2_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x420</addressOffset> <size>32</size> @@ -137745,28 +137464,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -137775,8 +137494,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_32B_WORD0</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB17_16B_WORD0_H</name> + <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x420</addressOffset> <size>32</size> @@ -137815,46 +137534,6 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_WORD2</name> - <description>Message Buffer 38 WORD_16B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x420</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> <name>MB58_8B_CS</name> <description>Message Buffer 58 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -137930,41 +137609,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID58</name> - <description>Message Buffer 58 ID Register</description> + <name>MB5_64B_WORD12_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x424</addressOffset> + <addressOffset>0x420</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_51</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_50</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_49</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_48</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB12_64B_WORD15</name> - <description>Message Buffer 12 WORD_64B Register</description> + <name>ID58</name> + <description>Message Buffer 58 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x424</addressOffset> <size>32</size> @@ -137973,38 +137659,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_62</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_32B_WORD1</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB10_32B_WORD3_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x424</addressOffset> <size>32</size> @@ -138013,28 +137692,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138043,8 +137722,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB38_16B_WORD3</name> - <description>Message Buffer 38 WORD_16B Register</description> + <name>MB17_16B_WORD1_H</name> + <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x424</addressOffset> <size>32</size> @@ -138053,28 +137732,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138116,83 +137795,88 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_CS</name> - <description>Message Buffer 13 CS Register</description> + <name>MB5_64B_WORD13_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x428</addressOffset> + <addressOffset>0x424</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_55</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_54</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_53</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_52</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB10_32B_WORD4_H</name> + <description>Message Buffer 10 WORD_32B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x428</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_32B_WORD2</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB17_16B_WORD2_H</name> + <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x428</addressOffset> <size>32</size> @@ -138231,8 +137915,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_16B_CS</name> - <description>Message Buffer 39 CS Register</description> + <name>MB58_8B_WORD0</name> + <description>Message Buffer 58 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x428</addressOffset> <size>32</size> @@ -138241,73 +137925,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_3</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_2</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_1</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_0</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB58_8B_WORD0</name> - <description>Message Buffer 58 WORD_8B Register</description> + <name>MB5_64B_WORD14_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x428</addressOffset> <size>32</size> @@ -138316,28 +137965,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_59</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_58</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_57</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_56</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138386,8 +138035,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_ID</name> - <description>Message Buffer 13 ID Register</description> + <name>MB10_32B_WORD5_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x42C</addressOffset> <size>32</size> @@ -138396,31 +138045,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_23</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_22</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_21</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_20</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_32B_WORD3</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB17_16B_WORD3_H</name> + <description>Message Buffer 17 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x42C</addressOffset> <size>32</size> @@ -138459,8 +138115,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_16B_ID</name> - <description>Message Buffer 39 ID Register</description> + <name>MB58_8B_WORD1</name> + <description>Message Buffer 58 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x42C</addressOffset> <size>32</size> @@ -138469,31 +138125,38 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_7</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_6</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_5</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_4</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB58_8B_WORD1</name> - <description>Message Buffer 58 WORD_8B Register</description> + <name>MB5_64B_WORD15_H</name> + <description>Message Buffer 5 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x42C</addressOffset> <size>32</size> @@ -138502,28 +138165,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_63</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_62</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_61</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_60</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138647,8 +138310,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD0</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB10_32B_WORD6_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x430</addressOffset> <size>32</size> @@ -138657,28 +138320,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_27</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_26</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_25</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_24</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138687,8 +138350,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_32B_WORD4</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB18_16B_CS_H</name> + <description>Message Buffer 18 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x430</addressOffset> <size>32</size> @@ -138697,38 +138360,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB39_16B_WORD0</name> - <description>Message Buffer 39 WORD_16B Register</description> + <name>MB59_8B_CS</name> + <description>Message Buffer 59 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x430</addressOffset> <size>32</size> @@ -138737,38 +138435,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB59_8B_CS</name> - <description>Message Buffer 59 CS Register</description> + <name>MB6_64B_CS_H</name> + <description>Message Buffer 6 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x430</addressOffset> <size>32</size> @@ -138875,8 +138608,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD1</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB10_32B_WORD7_H</name> + <description>Message Buffer 10 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x434</addressOffset> <size>32</size> @@ -138885,28 +138618,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -138915,8 +138648,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB23_32B_WORD5</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB18_16B_ID_H</name> + <description>Message Buffer 18 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x434</addressOffset> <size>32</size> @@ -138925,38 +138658,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_22</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB39_16B_WORD1</name> - <description>Message Buffer 39 WORD_16B Register</description> + <name>MB59_8B_ID</name> + <description>Message Buffer 59 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x434</addressOffset> <size>32</size> @@ -138965,38 +138691,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB59_8B_ID</name> - <description>Message Buffer 59 ID Register</description> + <name>MB6_64B_ID_H</name> + <description>Message Buffer 6 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x434</addressOffset> <size>32</size> @@ -139028,8 +138747,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD2</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_CS_H</name> + <description>Message Buffer 11 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x438</addressOffset> <size>32</size> @@ -139038,38 +138757,73 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> - <description>Data byte 3 of Rx/Tx frame.</description> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_32B_WORD6</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB18_16B_WORD0_H</name> + <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x438</addressOffset> <size>32</size> @@ -139078,28 +138832,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139108,8 +138862,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_16B_WORD2</name> - <description>Message Buffer 39 WORD_16B Register</description> + <name>MB59_8B_WORD0</name> + <description>Message Buffer 59 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x438</addressOffset> <size>32</size> @@ -139118,28 +138872,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139148,8 +138902,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB59_8B_WORD0</name> - <description>Message Buffer 59 WORD_8B Register</description> + <name>MB6_64B_WORD0_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x438</addressOffset> <size>32</size> @@ -139228,8 +138982,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD3</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_ID_H</name> + <description>Message Buffer 11 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x43C</addressOffset> <size>32</size> @@ -139238,38 +138992,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_14</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB23_32B_WORD7</name> - <description>Message Buffer 23 WORD_32B Register</description> + <name>MB18_16B_WORD1_H</name> + <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x43C</addressOffset> <size>32</size> @@ -139278,28 +139025,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139308,8 +139055,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB39_16B_WORD3</name> - <description>Message Buffer 39 WORD_16B Register</description> + <name>MB59_8B_WORD1</name> + <description>Message Buffer 59 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x43C</addressOffset> <size>32</size> @@ -139318,28 +139065,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139348,8 +139095,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB59_8B_WORD1</name> - <description>Message Buffer 59 WORD_8B Register</description> + <name>MB6_64B_WORD1_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x43C</addressOffset> <size>32</size> @@ -139503,8 +139250,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD4</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD0_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x440</addressOffset> <size>32</size> @@ -139513,28 +139260,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_19</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_18</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_17</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_16</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139543,8 +139290,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_CS</name> - <description>Message Buffer 40 CS Register</description> + <name>MB18_16B_WORD2_H</name> + <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x440</addressOffset> <size>32</size> @@ -139553,66 +139300,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> - <access>read-write</access> - </field> - <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> - <access>read-write</access> - </field> - <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -139693,6 +139405,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD2_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x440</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>ID60</name> <description>Message Buffer 60 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -139726,8 +139478,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD5</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD1_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x444</addressOffset> <size>32</size> @@ -139736,28 +139488,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_23</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_22</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_21</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_20</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139766,8 +139518,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_ID</name> - <description>Message Buffer 40 ID Register</description> + <name>MB18_16B_WORD3_H</name> + <description>Message Buffer 18 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x444</addressOffset> <size>32</size> @@ -139776,24 +139528,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -139832,38 +139591,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD6</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB6_64B_WORD3_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x448</addressOffset> + <addressOffset>0x444</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_27</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_26</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_25</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_24</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139872,8 +139631,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_WORD0</name> - <description>Message Buffer 40 WORD_16B Register</description> + <name>MB11_32B_WORD2_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x448</addressOffset> <size>32</size> @@ -139882,28 +139641,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_3</name> + <name>DATA_BYTE_11</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> + <name>DATA_BYTE_10</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> + <name>DATA_BYTE_9</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> + <name>DATA_BYTE_8</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -139912,6 +139671,81 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB19_16B_CS_H</name> + <description>Message Buffer 19 CS Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x448</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <bitOffset>0</bitOffset> + <bitWidth>16</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>MB60_8B_WORD0</name> <description>Message Buffer 60 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -139952,6 +139786,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD4_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x448</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_19</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_18</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_17</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_16</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD060</name> <description>Message Buffer 60 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -139992,8 +139866,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD7</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD3_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x44C</addressOffset> <size>32</size> @@ -140002,28 +139876,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_31</name> + <name>DATA_BYTE_15</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_30</name> + <name>DATA_BYTE_14</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_29</name> + <name>DATA_BYTE_13</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_28</name> + <name>DATA_BYTE_12</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140032,8 +139906,41 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_WORD1</name> - <description>Message Buffer 40 WORD_16B Register</description> + <name>MB19_16B_ID_H</name> + <description>Message Buffer 19 ID Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x44C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> + <bitOffset>0</bitOffset> + <bitWidth>18</bitWidth> + <access>read-write</access> + </field> + <field> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> + <access>read-write</access> + </field> + <field> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>MB60_8B_WORD1</name> + <description>Message Buffer 60 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x44C</addressOffset> <size>32</size> @@ -140072,8 +139979,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB60_8B_WORD1</name> - <description>Message Buffer 60 WORD_8B Register</description> + <name>MB6_64B_WORD5_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x44C</addressOffset> <size>32</size> @@ -140082,28 +139989,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140227,8 +140134,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD8</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD4_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x450</addressOffset> <size>32</size> @@ -140237,28 +140144,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_35</name> + <name>DATA_BYTE_19</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_34</name> + <name>DATA_BYTE_18</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_33</name> + <name>DATA_BYTE_17</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_32</name> + <name>DATA_BYTE_16</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140267,8 +140174,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_WORD2</name> - <description>Message Buffer 40 WORD_16B Register</description> + <name>MB19_16B_WORD0_H</name> + <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x450</addressOffset> <size>32</size> @@ -140277,28 +140184,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140382,6 +140289,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD6_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x450</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>ID61</name> <description>Message Buffer 61 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -140415,8 +140362,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD9</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD5_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x454</addressOffset> <size>32</size> @@ -140425,28 +140372,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_39</name> + <name>DATA_BYTE_23</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_38</name> + <name>DATA_BYTE_22</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_37</name> + <name>DATA_BYTE_21</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_36</name> + <name>DATA_BYTE_20</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140455,8 +140402,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB40_16B_WORD3</name> - <description>Message Buffer 40 WORD_16B Register</description> + <name>MB19_16B_WORD1_H</name> + <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x454</addressOffset> <size>32</size> @@ -140465,28 +140412,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140528,38 +140475,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD10</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB6_64B_WORD7_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x458</addressOffset> + <addressOffset>0x454</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_43</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_42</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_41</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_40</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140568,8 +140515,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB41_16B_CS</name> - <description>Message Buffer 41 CS Register</description> + <name>MB11_32B_WORD6_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x458</addressOffset> <size>32</size> @@ -140578,66 +140525,71 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>TIME_STAMP</name> - <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> + <name>DATA_BYTE_27</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>16</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DLC</name> - <description>Length of the data to be stored/transmitted.</description> - <bitOffset>16</bitOffset> - <bitWidth>4</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>RTR</name> - <description>Remote Transmission Request. One/zero for remote/data frame.</description> - <bitOffset>20</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_26</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>IDE</name> - <description>ID Extended. One/zero for extended/standard format frame.</description> - <bitOffset>21</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_25</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>SRR</name> - <description>Substitute Remote Request. Contains a fixed recessive bit.</description> - <bitOffset>22</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_24</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> + </fields> + </register> + <register> + <name>MB19_16B_WORD2_H</name> + <description>Message Buffer 19 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x458</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> <field> - <name>CODE</name> - <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> - <bitOffset>24</bitOffset> - <bitWidth>4</bitWidth> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>ESI</name> - <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> - <bitOffset>29</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>BRS</name> - <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> - <bitOffset>30</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>EDL</name> - <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> - <bitOffset>31</bitOffset> - <bitWidth>1</bitWidth> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -140683,6 +140635,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD8_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x458</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_35</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_34</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_33</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_32</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD061</name> <description>Message Buffer 61 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -140723,8 +140715,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD11</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB11_32B_WORD7_H</name> + <description>Message Buffer 11 WORD_32B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x45C</addressOffset> <size>32</size> @@ -140733,28 +140725,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_47</name> + <name>DATA_BYTE_31</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_46</name> + <name>DATA_BYTE_30</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_45</name> + <name>DATA_BYTE_29</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_44</name> + <name>DATA_BYTE_28</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -140763,8 +140755,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB41_16B_ID</name> - <description>Message Buffer 41 ID Register</description> + <name>MB19_16B_WORD3_H</name> + <description>Message Buffer 19 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x45C</addressOffset> <size>32</size> @@ -140773,24 +140765,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> @@ -140836,6 +140835,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD9_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x45C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_39</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_38</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_37</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_36</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD161</name> <description>Message Buffer 61 WORD1 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -140951,8 +140990,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD12</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB20_16B_CS_H</name> + <description>Message Buffer 20 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x460</addressOffset> <size>32</size> @@ -140961,71 +141000,66 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_51</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>TIME_STAMP</name> + <description>Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_50</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>DLC</name> + <description>Length of the data to be stored/transmitted.</description> + <bitOffset>16</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_49</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>RTR</name> + <description>Remote Transmission Request. One/zero for remote/data frame.</description> + <bitOffset>20</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_48</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>IDE</name> + <description>ID Extended. One/zero for extended/standard format frame.</description> + <bitOffset>21</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> - </fields> - </register> - <register> - <name>MB41_16B_WORD0</name> - <description>Message Buffer 41 WORD_16B Register</description> - <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x460</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> <field> - <name>DATA_BYTE_3</name> - <description>Data byte 0 of Rx/Tx frame.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> + <name>SRR</name> + <description>Substitute Remote Request. Contains a fixed recessive bit.</description> + <bitOffset>22</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_2</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <name>CODE</name> + <description>Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.</description> + <bitOffset>24</bitOffset> + <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_1</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>ESI</name> + <description>Error State Indicator. This bit indicates if the transmitting node is error active or error passive.</description> + <bitOffset>29</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_0</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>BRS</name> + <description>Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.</description> + <bitOffset>30</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>EDL</name> + <description>Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.</description> + <bitOffset>31</bitOffset> + <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> @@ -141106,41 +141140,48 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ID62</name> - <description>Message Buffer 62 ID Register</description> + <name>MB6_64B_WORD10_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x464</addressOffset> + <addressOffset>0x460</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>EXT</name> - <description>Contains extended (LOW word) identifier of message buffer.</description> + <name>DATA_BYTE_43</name> + <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> - <bitWidth>18</bitWidth> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>STD</name> - <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> - <bitOffset>18</bitOffset> - <bitWidth>11</bitWidth> + <name>DATA_BYTE_42</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>PRIO</name> - <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> - <bitOffset>29</bitOffset> - <bitWidth>3</bitWidth> + <name>DATA_BYTE_41</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_40</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB13_64B_WORD13</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>ID62</name> + <description>Message Buffer 62 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x464</addressOffset> <size>32</size> @@ -141149,38 +141190,31 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_55</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_54</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_53</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_52</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> - <name>MB41_16B_WORD1</name> - <description>Message Buffer 41 WORD_16B Register</description> + <name>MB20_16B_ID_H</name> + <description>Message Buffer 20 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x464</addressOffset> <size>32</size> @@ -141189,31 +141223,24 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> - <description>Data byte 0 of Rx/Tx frame.</description> + <name>EXT</name> + <description>Contains extended (LOW word) identifier of message buffer.</description> <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - <access>read-write</access> - </field> - <field> - <name>DATA_BYTE_6</name> - <description>Data byte 1 of Rx/Tx frame.</description> - <bitOffset>8</bitOffset> - <bitWidth>8</bitWidth> + <bitWidth>18</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> - <description>Data byte 2 of Rx/Tx frame.</description> - <bitOffset>16</bitOffset> - <bitWidth>8</bitWidth> + <name>STD</name> + <description>Contains standard/extended (HIGH word) identifier of message buffer.</description> + <bitOffset>18</bitOffset> + <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> - <description>Data byte 3 of Rx/Tx frame.</description> - <bitOffset>24</bitOffset> - <bitWidth>8</bitWidth> + <name>PRIO</name> + <description>Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.</description> + <bitOffset>29</bitOffset> + <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> @@ -141252,38 +141279,38 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD14</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB6_64B_WORD11_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> - <addressOffset>0x468</addressOffset> + <addressOffset>0x464</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_59</name> + <name>DATA_BYTE_47</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_58</name> + <name>DATA_BYTE_46</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_57</name> + <name>DATA_BYTE_45</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_56</name> + <name>DATA_BYTE_44</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -141292,8 +141319,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB41_16B_WORD2</name> - <description>Message Buffer 41 WORD_16B Register</description> + <name>MB20_16B_WORD0_H</name> + <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x468</addressOffset> <size>32</size> @@ -141302,28 +141329,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_11</name> + <name>DATA_BYTE_3</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_10</name> + <name>DATA_BYTE_2</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_9</name> + <name>DATA_BYTE_1</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_8</name> + <name>DATA_BYTE_0</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -141372,6 +141399,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD12_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x468</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_51</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_50</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_49</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_48</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>WORD062</name> <description>Message Buffer 62 WORD0 Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -141412,8 +141479,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB13_64B_WORD15</name> - <description>Message Buffer 13 WORD_64B Register</description> + <name>MB20_16B_WORD1_H</name> + <description>Message Buffer 20 WORD_16B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x46C</addressOffset> <size>32</size> @@ -141422,28 +141489,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_63</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_62</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_61</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_60</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -141452,8 +141519,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB41_16B_WORD3</name> - <description>Message Buffer 41 WORD_16B Register</description> + <name>MB62_8B_WORD1</name> + <description>Message Buffer 62 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x46C</addressOffset> <size>32</size> @@ -141462,28 +141529,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_15</name> + <name>DATA_BYTE_7</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_14</name> + <name>DATA_BYTE_6</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_13</name> + <name>DATA_BYTE_5</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_12</name> + <name>DATA_BYTE_4</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -141492,8 +141559,8 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>MB62_8B_WORD1</name> - <description>Message Buffer 62 WORD_8B Register</description> + <name>MB6_64B_WORD13_H</name> + <description>Message Buffer 6 WORD_64B Register</description> <alternateGroup>MB_SIZE</alternateGroup> <addressOffset>0x46C</addressOffset> <size>32</size> @@ -141502,28 +141569,28 @@ SPDX-License-Identifier: BSD-3-Clause <resetMask>0xFFFFFFFF</resetMask> <fields> <field> - <name>DATA_BYTE_7</name> + <name>DATA_BYTE_55</name> <description>Data byte 0 of Rx/Tx frame.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_6</name> + <name>DATA_BYTE_54</name> <description>Data byte 1 of Rx/Tx frame.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_5</name> + <name>DATA_BYTE_53</name> <description>Data byte 2 of Rx/Tx frame.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> - <name>DATA_BYTE_4</name> + <name>DATA_BYTE_52</name> <description>Data byte 3 of Rx/Tx frame.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> @@ -141647,6 +141714,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB20_16B_WORD2_H</name> + <description>Message Buffer 20 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x470</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_11</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_10</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_9</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_8</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>MB63_8B_CS</name> <description>Message Buffer 63 CS Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -141722,6 +141829,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD14_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x470</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_59</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_58</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_57</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_56</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>ID63</name> <description>Message Buffer 63 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -141755,6 +141902,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB20_16B_WORD3_H</name> + <description>Message Buffer 20 WORD_16B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x474</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_15</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_14</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_13</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_12</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>MB63_8B_ID</name> <description>Message Buffer 63 ID Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -141788,6 +141975,46 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>MB6_64B_WORD15_H</name> + <description>Message Buffer 6 WORD_64B Register</description> + <alternateGroup>MB_SIZE</alternateGroup> + <addressOffset>0x474</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>DATA_BYTE_63</name> + <description>Data byte 0 of Rx/Tx frame.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_62</name> + <description>Data byte 1 of Rx/Tx frame.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_61</name> + <description>Data byte 2 of Rx/Tx frame.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>DATA_BYTE_60</name> + <description>Data byte 3 of Rx/Tx frame.</description> + <bitOffset>24</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>MB63_8B_WORD0</name> <description>Message Buffer 63 WORD_8B Register</description> <alternateGroup>MB_SIZE</alternateGroup> @@ -145786,7 +146013,6 @@ SPDX-License-Identifier: BSD-3-Clause <name>GPT1</name> <description>GPT</description> <groupName>GPT</groupName> - <prependToName>GPT1_</prependToName> <headerStructName>GPT</headerStructName> <baseAddress>0x401EC000</baseAddress> <addressBlock> @@ -145816,70 +146042,70 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EN_0</name> - <description>GPT is disabled.</description> + <name>DISABLE</name> + <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EN_1</name> - <description>GPT is enabled.</description> + <name>ENABLE</name> + <description>Enable</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>ENMOD</name> - <description>GPT Enable mode</description> + <description>GPT Enable Mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ENMOD_0</name> - <description>GPT counter will retain its value when it is disabled.</description> + <name>RESUME_COUNT</name> + <description>Restart counting from their frozen values after GPT is enabled (EN=1).</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ENMOD_1</name> - <description>GPT counter value is reset to 0 when it is disabled.</description> + <name>ZERO_COUNT</name> + <description>Reset counting from 0 after GPT is enabled (EN=1).</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>DBGEN</name> - <description>GPT debug mode enable</description> + <description>GPT Debug Mode Enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DBGEN_0</name> - <description>GPT is disabled in debug mode.</description> + <name>DEBUG_DIS</name> + <description>Disable in Debug mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DBGEN_1</name> - <description>GPT is enabled in debug mode.</description> + <name>DEBUG_EN</name> + <description>Enable in Debug mode</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>WAITEN</name> - <description>GPT Wait Mode enable</description> + <description>GPT Wait Mode Enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WAITEN_0</name> - <description>GPT is disabled in wait mode.</description> + <name>WAIT_DIS</name> + <description>Disable in Wait mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WAITEN_1</name> - <description>GPT is enabled in wait mode.</description> + <name>WAIT_EN</name> + <description>Enable in Wait mode</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -145892,245 +146118,345 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DOZEEN_0</name> - <description>GPT is disabled in doze mode.</description> + <name>DOZE_DIS</name> + <description>Disable in Doze mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DOZEEN_1</name> - <description>GPT is enabled in doze mode.</description> + <name>DOZE_EN</name> + <description>Enable in Doze mode</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>STOPEN</name> - <description>GPT Stop Mode enable</description> + <description>GPT Stop Mode Enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>STOPEN_0</name> - <description>GPT is disabled in Stop mode.</description> + <name>STOP_DIS</name> + <description>Disable in Stop mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>STOPEN_1</name> - <description>GPT is enabled in Stop mode.</description> + <name>STOP_EN</name> + <description>Enable in Stop mode</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>CLKSRC</name> - <description>Clock Source select</description> + <description>Clock Source Select</description> <bitOffset>6</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CLKSRC_0</name> + <name>NO_CLOCK</name> <description>No clock</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CLKSRC_1</name> + <name>CLOCK_001</name> <description>Peripheral Clock (ipg_clk)</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>CLKSRC_2</name> + <name>CLOCK_010</name> <description>High Frequency Reference Clock (ipg_clk_highfreq)</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>CLKSRC_3</name> + <name>CLOCK_011</name> <description>External Clock</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>CLKSRC_4</name> + <name>CLOCK_100</name> <description>Low Frequency Reference Clock (ipg_clk_32k)</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>CLKSRC_5</name> - <description>Crystal oscillator as Reference Clock (ipg_clk_24M)</description> + <name>CLOCK_101</name> + <description>Oscillator as Reference Clock (ipg_clk_24M)</description> <value>0x5</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>FRR</name> - <description>Free-Run or Restart mode</description> + <description>Free-Run or Restart Mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>FRR_0</name> - <description>Restart mode</description> + <name>RESTART</name> + <description>Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>FRR_1</name> - <description>Free-Run mode</description> + <name>FREE_RUN</name> + <description>Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>EN_24M</name> - <description>Enable 24 MHz clock input from crystal</description> + <description>Enable Oscillator Clock Input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EN_24M_0</name> - <description>24M clock disabled</description> + <name>DISABLE</name> + <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EN_24M_1</name> - <description>24M clock enabled</description> + <name>ENABLE</name> + <description>Enable</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>SWR</name> - <description>Software reset</description> + <description>Software Reset</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SWR_0</name> - <description>GPT is not in reset state</description> + <name>NOT_SWRESET</name> + <description>GPT is not in software reset state</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SWR_1</name> - <description>GPT is in reset state</description> + <name>SWRESET</name> + <description>GPT is in software reset state</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>IM1</name> - <description>See IM2</description> + <description>Input Capture Operating Mode for Channel 1</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Capture disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>RISING</name> + <description>Capture on rising edge only</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>FALLING</name> + <description>Capture on falling edge only</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>BOTH</name> + <description>Capture on both edges</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>IM2</name> - <description>IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event</description> + <description>Input Capture Operating Mode for Channel 2</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>IM2_0</name> - <description>capture disabled</description> + <name>DISABLED</name> + <description>Capture disabled</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IM2_1</name> - <description>capture on rising edge only</description> + <name>RISING</name> + <description>Capture on rising edge only</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>IM2_2</name> - <description>capture on falling edge only</description> + <name>FALLING</name> + <description>Capture on falling edge only</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>IM2_3</name> - <description>capture on both edges</description> + <name>BOTH</name> + <description>Capture on both edges</description> <value>0x3</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>OM1</name> - <description>See OM3</description> + <description>Output Compare Operating Mode for Channel 1</description> <bitOffset>20</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Output disabled. No response on pin.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>TOGGLE</name> + <description>Toggle output pin</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>CLEAR</name> + <description>Clear output pin</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SET</name> + <description>Set output pin</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PULSE</name> + <description>Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.</description> + <value>#1xx</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OM2</name> - <description>See OM3</description> + <description>Output Compare Operating Mode for Channel 2</description> <bitOffset>23</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Output disabled. No response on pin.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>TOGGLE</name> + <description>Toggle output pin</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>CLEAR</name> + <description>Clear output pin</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SET</name> + <description>Set output pin</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PULSE</name> + <description>Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.</description> + <value>#1xx</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OM3</name> - <description>OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode</description> + <description>Output Compare Operating Mode for Channel 3</description> <bitOffset>26</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>OM3_0</name> - <description>Output disconnected. No response on pin.</description> + <name>DISABLED</name> + <description>Output disabled. No response on pin.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>OM3_1</name> + <name>TOGGLE</name> <description>Toggle output pin</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>OM3_2</name> + <name>CLEAR</name> <description>Clear output pin</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>OM3_3</name> + <name>SET</name> <description>Set output pin</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>OM3_4</name> - <description>Generate an active low pulse (that is one input clock wide) on the output pin.</description> + <name>PULSE</name> + <description>Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.</description> <value>#1xx</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>FO1</name> - <description>See F03</description> + <description>Force Output Compare for Channel 1</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_FORCE</name> + <description>No effect</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>FORCE</name> + <description>Trigger the programmed response on the pin</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>FO2</name> - <description>See F03</description> + <description>Force Output Compare for Channel 2</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_FORCE</name> + <description>No effect</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>FORCE</name> + <description>Trigger the programmed response on the pin</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>FO3</name> - <description>FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)</description> + <description>Force Output Compare for Channel 3</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>FO3_0</name> - <description>Writing a 0 has no effect.</description> + <name>NO_FORCE</name> + <description>No effect</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>FO3_1</name> - <description>Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.</description> + <name>FORCE</name> + <description>Trigger the programmed response on the pin</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -146148,23 +146474,23 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>PRESCALER</name> - <description>Prescaler bits</description> + <description>Prescaler divide value</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>PRESCALER_0</name> + <name>DIV_BY_1</name> <description>Divide by 1</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>PRESCALER_1</name> + <name>DIV_BY_2</name> <description>Divide by 2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>PRESCALER_4095</name> + <name>DIV_BY_4096</name> <description>Divide by 4096</description> <value>0xFFF</value> </enumeratedValue> @@ -146172,23 +146498,23 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>PRESCALER24M</name> - <description>Prescaler bits</description> + <description>Prescaler divide value for the oscillator clock</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>PRESCALER24M_0</name> + <name>DIV_BY_1</name> <description>Divide by 1</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>PRESCALER24M_1</name> + <name>DIV_BY_2</name> <description>Divide by 2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>PRESCALER24M_15</name> + <name>DIV_BY_16</name> <description>Divide by 16</description> <value>0xF</value> </enumeratedValue> @@ -146204,38 +146530,63 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>OF1</name> - <description>See OF3</description> + <description>Output Compare Flag for Channel 1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> + <enumeratedValues> + <enumeratedValue> + <name>NO_EVENT</name> + <description>Compare event has not occurred.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EVENT</name> + <description>Compare event has occurred.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OF2</name> - <description>See OF3</description> + <description>Output Compare Flag for Channel 2</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> + <enumeratedValues> + <enumeratedValue> + <name>NO_EVENT</name> + <description>Compare event has not occurred.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EVENT</name> + <description>Compare event has occurred.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OF3</name> - <description>OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n</description> + <description>Output Compare Flag for Channel 3</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>OF3_0</name> + <name>NO_EVENT</name> <description>Compare event has not occurred.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>OF3_1</name> + <name>EVENT</name> <description>Compare event has occurred.</description> <value>0x1</value> </enumeratedValue> @@ -146243,27 +146594,39 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>IF1</name> - <description>See IF2</description> + <description>Input Capture Flag for Channel 1</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> + <enumeratedValues> + <enumeratedValue> + <name>NO_EVENT</name> + <description>Capture event has not occurred.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EVENT</name> + <description>Capture event has occurred.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>IF2</name> - <description>IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n</description> + <description>Input Capture Flag for Channel 2</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>IF2_0</name> + <name>NO_EVENT</name> <description>Capture event has not occurred.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IF2_1</name> + <name>EVENT</name> <description>Capture event has occurred.</description> <value>0x1</value> </enumeratedValue> @@ -146278,12 +146641,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>ROV_0</name> + <name>NO_ROLLOVER</name> <description>Rollover has not occurred.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ROV_1</name> + <name>ROLLOVER</name> <description>Rollover has occurred.</description> <value>0x1</value> </enumeratedValue> @@ -146302,78 +146665,114 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>OF1IE</name> - <description>See OF3IE</description> + <description>Output Compare Flag for Channel 1 Interrupt Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLE</name> + <description>Disable</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLE</name> + <description>Enable</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OF2IE</name> - <description>See OF3IE</description> + <description>Output Compare Flag for Channel 2 Interrupt Enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLE</name> + <description>Disable</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLE</name> + <description>Enable</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>OF3IE</name> - <description>OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt</description> + <description>Output Compare Flag for Channel 3 Interrupt Enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>OF3IE_0</name> - <description>Output Compare Channel n interrupt is disabled.</description> + <name>DISABLE</name> + <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>OF3IE_1</name> - <description>Output Compare Channel n interrupt is enabled.</description> + <name>ENABLE</name> + <description>Enable</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>IF1IE</name> - <description>See IF2IE</description> + <description>Input Capture Flag for Channel 1 Interrupt Enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLE</name> + <description>Disable</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLE</name> + <description>Enable</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>IF2IE</name> - <description>IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable</description> + <description>Input Capture Flag for Channel 2 Interrupt Enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>IF2IE_0</name> - <description>IF2IE Input Capture n Interrupt Enable is disabled.</description> + <name>DISABLE</name> + <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IF2IE_1</name> - <description>IF2IE Input Capture n Interrupt Enable is enabled.</description> + <name>ENABLE</name> + <description>Enable</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>ROVIE</name> - <description>Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt.</description> + <description>Rollover Interrupt Enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ROVIE_0</name> - <description>Rollover interrupt is disabled.</description> + <name>DISABLE</name> + <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ROVIE_1</name> - <description>Rollover interrupt enabled.</description> + <name>ENABLE</name> + <description>Enable</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -146381,8 +146780,11 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>OCR1</name> - <description>GPT Output Compare Register 1</description> + <dim>3</dim> + <dimIncrement>0x4</dimIncrement> + <dimIndex>1,2,3</dimIndex> + <name>OCR%s</name> + <description>GPT Output Compare Register</description> <addressOffset>0x10</addressOffset> <size>32</size> <access>read-write</access> @@ -146399,44 +146801,11 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>OCR2</name> - <description>GPT Output Compare Register 2</description> - <addressOffset>0x14</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0xFFFFFFFF</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>COMP</name> - <description>Compare Value</description> - <bitOffset>0</bitOffset> - <bitWidth>32</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>OCR3</name> - <description>GPT Output Compare Register 3</description> - <addressOffset>0x18</addressOffset> - <size>32</size> - <access>read-write</access> - <resetValue>0xFFFFFFFF</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>COMP</name> - <description>Compare Value</description> - <bitOffset>0</bitOffset> - <bitWidth>32</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> - <register> - <name>ICR1</name> - <description>GPT Input Capture Register 1</description> + <dim>2</dim> + <dimIncrement>0x4</dimIncrement> + <dimIndex>1,2</dimIndex> + <name>ICR%s</name> + <description>GPT Input Capture Register</description> <addressOffset>0x1C</addressOffset> <size>32</size> <access>read-only</access> @@ -146453,24 +146822,6 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <name>ICR2</name> - <description>GPT Input Capture Register 2</description> - <addressOffset>0x20</addressOffset> - <size>32</size> - <access>read-only</access> - <resetValue>0</resetValue> - <resetMask>0xFFFFFFFF</resetMask> - <fields> - <field> - <name>CAPT</name> - <description>Capture Value</description> - <bitOffset>0</bitOffset> - <bitWidth>32</bitWidth> - <access>read-only</access> - </field> - </fields> - </register> - <register> <name>CNT</name> <description>GPT Counter Register</description> <addressOffset>0x24</addressOffset> @@ -146481,7 +146832,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>COUNT</name> - <description>Counter Value. The COUNT bits show the current count value of the GPT counter.</description> + <description>Counter Value</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> <access>read-only</access> @@ -146494,7 +146845,6 @@ SPDX-License-Identifier: BSD-3-Clause <name>GPT2</name> <description>GPT</description> <groupName>GPT</groupName> - <prependToName>GPT2_</prependToName> <baseAddress>0x401F0000</baseAddress> <addressBlock> <offset>0</offset> @@ -146619,6 +146969,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToSet</modifiedWriteValues> <fields> <field> <name>ADDR</name> @@ -146670,6 +147021,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>ADDR</name> @@ -146721,6 +147073,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToToggle</modifiedWriteValues> <fields> <field> <name>ADDR</name> @@ -146970,6 +147323,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToSet</modifiedWriteValues> <fields> <field> <name>HAB_JDE</name> @@ -147005,6 +147359,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>HAB_JDE</name> @@ -147040,6 +147395,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToToggle</modifiedWriteValues> <fields> <field> <name>HAB_JDE</name> @@ -189163,6 +189519,5755 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_00</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register</description> + <addressOffset>0x65C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO00 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_00</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_01</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_01 SW MUX Control Register</description> + <addressOffset>0x660</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO01 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_01</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_02</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_02 SW MUX Control Register</description> + <addressOffset>0x664</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO02 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_02</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_03</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_03 SW MUX Control Register</description> + <addressOffset>0x668</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA02 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO03 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_03</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_04</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_04 SW MUX Control Register</description> + <addressOffset>0x66C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO04 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_04</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_05</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_05 SW MUX Control Register</description> + <addressOffset>0x670</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO05 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_05</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_06</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_06 SW MUX Control Register</description> + <addressOffset>0x674</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO06 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_06</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_07</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_07 SW MUX Control Register</description> + <addressOffset>0x678</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA01 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO07 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_07</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_08</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_08 SW MUX Control Register</description> + <addressOffset>0x67C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO08 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_08</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_09</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_09 SW MUX Control Register</description> + <addressOffset>0x680</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO09 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_09</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_10</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_10 SW MUX Control Register</description> + <addressOffset>0x684</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO10 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_10</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_11</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_11 SW MUX Control Register</description> + <addressOffset>0x688</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA00 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO11 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_11</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_12</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_12 SW MUX Control Register</description> + <addressOffset>0x68C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO12 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_12</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B0_13</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B0_13 SW MUX Control Register</description> + <addressOffset>0x690</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO13 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B0_13</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_00</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_00 SW MUX Control Register</description> + <addressOffset>0x694</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO14 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_00</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_01</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_01 SW MUX Control Register</description> + <addressOffset>0x698</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO15 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_01</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_02</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_02 SW MUX Control Register</description> + <addressOffset>0x69C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO16 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_02</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_03</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_03 SW MUX Control Register</description> + <addressOffset>0x6A0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO17 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_03</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_04</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_04 SW MUX Control Register</description> + <addressOffset>0x6A4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO18 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_04</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_05</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_05 SW MUX Control Register</description> + <addressOffset>0x6A8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO19 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_05</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_06</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_06 SW MUX Control Register</description> + <addressOffset>0x6AC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x5</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT0</name> + <description>Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO20 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_06</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_MUX_CTL_PAD_GPIO_SPI_B1_07</name> + <description>SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register</description> + <addressOffset>0x6B0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>MUX_MODE</name> + <description>MUX Mode Select Field.</description> + <bitOffset>0</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ALT5</name> + <description>Select mux mode: ALT5 mux port: GPIO10_IO21 of instance: gpio10</description> + <value>0x5</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SION</name> + <description>Software Input On Field.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>Input Path is determined by functionality</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>Force input path of pad GPIO_SPI_B1_07</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_00</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register</description> + <addressOffset>0x6B4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_01</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_01 SW PAD Control Register</description> + <addressOffset>0x6B8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_02</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_02 SW PAD Control Register</description> + <addressOffset>0x6BC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_03</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_03 SW PAD Control Register</description> + <addressOffset>0x6C0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_04</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_04 SW PAD Control Register</description> + <addressOffset>0x6C4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_05</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_05 SW PAD Control Register</description> + <addressOffset>0x6C8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_06</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_06 SW PAD Control Register</description> + <addressOffset>0x6CC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_07</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_07 SW PAD Control Register</description> + <addressOffset>0x6D0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_08</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_08 SW PAD Control Register</description> + <addressOffset>0x6D4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_09</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_09 SW PAD Control Register</description> + <addressOffset>0x6D8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_10</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_10 SW PAD Control Register</description> + <addressOffset>0x6DC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_11</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_11 SW PAD Control Register</description> + <addressOffset>0x6E0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_12</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_12 SW PAD Control Register</description> + <addressOffset>0x6E4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B0_13</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B0_13 SW PAD Control Register</description> + <addressOffset>0x6E8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_00</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_00 SW PAD Control Register</description> + <addressOffset>0x6EC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_01</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_01 SW PAD Control Register</description> + <addressOffset>0x6F0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_02</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_02 SW PAD Control Register</description> + <addressOffset>0x6F4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_03</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_03 SW PAD Control Register</description> + <addressOffset>0x6F8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_04</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_04 SW PAD Control Register</description> + <addressOffset>0x6FC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_05</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_05 SW PAD Control Register</description> + <addressOffset>0x700</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_06</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_06 SW PAD Control Register</description> + <addressOffset>0x704</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>SW_PAD_CTL_PAD_GPIO_SPI_B1_07</name> + <description>SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register</description> + <addressOffset>0x708</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x10B0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>SRE</name> + <description>Slew Rate Field</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SRE_0_Slow_Slew_Rate</name> + <description>Slow Slew Rate</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SRE_1_Fast_Slew_Rate</name> + <description>Fast Slew Rate</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>DSE</name> + <description>Drive Strength Field</description> + <bitOffset>3</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DSE_0_output_driver_disabled_</name> + <description>output driver disabled;</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_</name> + <description>R0(150 Ohm @ 3.3V, 260 [email protected])</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_2_R0_2</name> + <description>R0/2</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_3_R0_3</name> + <description>R0/3</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_4_R0_4</name> + <description>R0/4</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_5_R0_5</name> + <description>R0/5</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_6_R0_6</name> + <description>R0/6</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>DSE_7_R0_7</name> + <description>R0/7</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SPEED</name> + <description>Speed Field</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>SPEED_0_low_50MHz</name> + <description>low(50MHz)</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_1_medium_100MHz</name> + <description>medium(100MHz)</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_2_fast_150MHz</name> + <description>fast(150MHz)</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>SPEED_3_max_200MHz</name> + <description>max(200MHz)</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ODE</name> + <description>Open Drain Enable Field</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ODE_0_Open_Drain_Disabled</name> + <description>Open Drain Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ODE_1_Open_Drain_Enabled</name> + <description>Open Drain Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PKE</name> + <description>Pull / Keep Enable Field</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PKE_0_Pull_Keeper_Disabled</name> + <description>Pull/Keeper Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PKE_1_Pull_Keeper_Enabled</name> + <description>Pull/Keeper Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUE</name> + <description>Pull / Keep Select Field</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUE_0_Keeper</name> + <description>Keeper</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUE_1_Pull</name> + <description>Pull</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PUS</name> + <description>Pull Up / Down Config. Field</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PUS_0_100K_Ohm_Pull_Down</name> + <description>100K Ohm Pull Down</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_1_47K_Ohm_Pull_Up</name> + <description>47K Ohm Pull Up</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_2_100K_Ohm_Pull_Up</name> + <description>100K Ohm Pull Up</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PUS_3_22K_Ohm_Pull_Up</name> + <description>22K Ohm Pull Up</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HYS</name> + <description>Hyst. Enable Field</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HYS_0_Hysteresis_Disabled</name> + <description>Hysteresis Disabled</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HYS_1_Hysteresis_Enabled</name> + <description>Hysteresis Enabled</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> <name>ENET2_IPG_CLK_RMII_SELECT_INPUT</name> <description>ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register</description> <addressOffset>0x70C</addressOffset> @@ -190231,9 +196336,8 @@ SPDX-License-Identifier: BSD-3-Clause </peripheral> <peripheral> <name>KPP</name> - <description>KPP Registers</description> + <description>KPP</description> <groupName>KPP</groupName> - <prependToName>KPP_</prependToName> <baseAddress>0x401FC000</baseAddress> <addressBlock> <offset>0</offset> @@ -190256,7 +196360,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>KRE</name> - <description>Keypad Row Enable</description> + <description>KRE</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190275,7 +196379,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KCO</name> - <description>Keypad Column Strobe Open-Drain Enable</description> + <description>KCO</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190300,12 +196404,12 @@ SPDX-License-Identifier: BSD-3-Clause <addressOffset>0x2</addressOffset> <size>16</size> <access>read-write</access> - <resetValue>0x400</resetValue> + <resetValue>0x2</resetValue> <resetMask>0xFFFF</resetMask> <fields> <field> <name>KPKD</name> - <description>Keypad Key Depress</description> + <description>KPKD</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190325,7 +196429,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KPKR</name> - <description>Keypad Key Release</description> + <description>KPKR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190345,7 +196449,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KDSC</name> - <description>Key Depress Synchronizer Clear</description> + <description>KDSC</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190364,7 +196468,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KRSS</name> - <description>Key Release Synchronizer Set</description> + <description>KRSS</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190383,7 +196487,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KDIE</name> - <description>Keypad Key Depress Interrupt Enable</description> + <description>KDIE</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190402,7 +196506,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KRIE</name> - <description>Keypad Release Interrupt Enable</description> + <description>KRIE</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190432,7 +196536,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>KRDD</name> - <description>Keypad Row Data Direction</description> + <description>KRDD</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190451,7 +196555,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>KCDD</name> - <description>Keypad Column Data Direction Register</description> + <description>KCDD</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190481,14 +196585,14 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>KRD</name> - <description>Keypad Row Data</description> + <description>KRD</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> </field> <field> <name>KCD</name> - <description>Keypad Column Data</description> + <description>KCD</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190519,7 +196623,7 @@ SPDX-License-Identifier: BSD-3-Clause <addressOffset>0</addressOffset> <size>32</size> <access>read-write</access> - <resetValue>0xFFFF80C2</resetValue> + <resetValue>0xFFFF8002</resetValue> <resetMask>0xFFFFFFFF</resetMask> <fields> <field> @@ -190544,17 +196648,17 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RXCLKSRC_0</name> + <name>val0</name> <description>Dummy Read strobe generated by FlexSPI Controller and loopback internally.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RXCLKSRC_1</name> + <name>val1</name> <description>Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>RXCLKSRC_3</name> + <name>val3</name> <description>Flash provided Read strobe and input from DQS pad</description> <value>0x3</value> </enumeratedValue> @@ -190568,12 +196672,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ARDFEN_0</name> + <name>val0</name> <description>IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ARDFEN_1</name> + <name>val1</name> <description>IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.</description> <value>0x1</value> </enumeratedValue> @@ -190587,12 +196691,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ATDFEN_0</name> + <name>val0</name> <description>IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ATDFEN_1</name> + <name>val1</name> <description>IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.</description> <value>0x1</value> </enumeratedValue> @@ -190600,48 +196704,48 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>SERCLKDIV</name> - <description>The serial root clock could be divided inside FlexSPI . See Clocks section for more details on clocking.</description> + <description>Serial root clock</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SERCLKDIV_0</name> + <name>val0</name> <description>Divided by 1</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_1</name> + <name>val1</name> <description>Divided by 2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_2</name> + <name>val2</name> <description>Divided by 3</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_3</name> + <name>val3</name> <description>Divided by 4</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_4</name> + <name>val4</name> <description>Divided by 5</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_5</name> + <name>val5</name> <description>Divided by 6</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_6</name> + <name>val6</name> <description>Divided by 7</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>SERCLKDIV_7</name> + <name>val7</name> <description>Divided by 8</description> <value>0x7</value> </enumeratedValue> @@ -190649,18 +196753,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>HSEN</name> - <description>Half Speed Serial Flash access Enable.</description> + <description>Half Speed Serial Flash Access Enable.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>HSEN_0</name> + <name>val0</name> <description>Disable divide by 2 of serial flash clock for half speed commands.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>HSEN_1</name> + <name>val1</name> <description>Enable divide by 2 of serial flash clock for half speed commands.</description> <value>0x1</value> </enumeratedValue> @@ -190674,12 +196778,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DOZEEN_0</name> + <name>val0</name> <description>Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DOZEEN_1</name> + <name>val1</name> <description>Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.</description> <value>0x1</value> </enumeratedValue> @@ -190706,7 +196810,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>SCKFREERUNEN</name> - <description>This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).</description> + <description>This bit is used to enable SCLK output free-running. For FPGA applications, the external device may use SCLK as reference clock to its internal PLL.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190725,7 +196829,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>IPGRANTWAIT</name> - <description>Time out wait cycle for IP command grant.</description> + <description>Timeout wait cycle for IP command grant.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> @@ -190750,14 +196854,14 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>AHBBUSWAIT</name> - <description>AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response</description> + <description>AHB Bus wait</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>SEQWAIT</name> - <description>Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles</description> + <description>Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is ignored by arbitrator.</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> @@ -190775,38 +196879,38 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>CLRAHBBUFOPT</name> - <description>This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.</description> + <description>Clear AHB buffer</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CLRAHBBUFOPT_0</name> - <description>AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.</description> + <name>val0</name> + <description>AHB RX/TX Buffer will not be cleared automatically when FlexSPI returns Stop mode ACK.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CLRAHBBUFOPT_1</name> - <description>AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.</description> + <name>val1</name> + <description>AHB RX/TX Buffer will be cleared automatically when FlexSPI returns Stop mode ACK.</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>SAMEDEVICEEN</name> - <description>All external devices are same devices (both in types and size) for A1/A2/B1/B2.</description> + <description>All external devices are same devices (both in type and size) for A1/A2/B1/B2.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> <name>individual_parallel</name> - <description>In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored.</description> + <description>In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register setting will be ignored.</description> <value>0</value> </enumeratedValue> <enumeratedValue> <name>ENABLE</name> - <description>FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.</description> + <description>FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register setting will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -190819,12 +196923,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SCKBDIFFOPT_0</name> + <name>val1</name> <description>B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SCKBDIFFOPT_1</name> + <name>val0</name> <description>B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.</description> <value>0x1</value> </enumeratedValue> @@ -190850,7 +196954,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>APAREN</name> - <description>Parallel mode enabled for AHB triggered Command (both read and write) .</description> + <description>Parallel mode enabled for AHB triggered Command (both read and write).</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190876,7 +196980,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>CLRAHBTXBUF</name> - <description>Clear the status/pointers of AHB TX Buffer. Auto-cleared. For internal use only.</description> + <description>Clear the status/pointers of AHB TX Buffer. Auto-cleared.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -190889,12 +196993,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CACHABLEEN_0</name> + <name>val0</name> <description>Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CACHABLEEN_1</name> + <name>val1</name> <description>Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.</description> <value>0x1</value> </enumeratedValue> @@ -190902,18 +197006,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>BUFFERABLEEN</name> - <description>Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.</description> + <description>Enable AHB bus bufferable write access support.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BUFFERABLEEN_0</name> - <description>Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished.</description> + <name>val0</name> + <description>Disabled. For all AHB write accesses (bufferable or non-bufferable), FlexSPI will return AHB Bus ready after all data is transmitted to external device and AHB command finished.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BUFFERABLEEN_1</name> + <name>val1</name> <description>Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.</description> <value>0x1</value> </enumeratedValue> @@ -190928,18 +197032,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>READADDROPT</name> - <description>AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.</description> + <description>AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation.</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>READADDROPT_0</name> + <name>val0</name> <description>There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>READADDROPT_1</name> + <name>val1</name> <description>There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement.</description> <value>0x1</value> </enumeratedValue> @@ -190953,12 +197057,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>READSZALIGN_0</name> + <name>val0</name> <description>AHB read size will be decided by other register setting like PREFETCH_EN</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>READSZALIGN_1</name> + <name>val1</name> <description>AHB read size to up size to 8 bytes aligned, no prefetching</description> <value>0x1</value> </enumeratedValue> @@ -191040,14 +197144,14 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>AHBBUSTIMEOUTEN</name> - <description>AHB Bus timeout interrupt.Refer Interrupts chapter for more details.</description> + <description>AHB Bus timeout interrupt.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SEQTIMEOUTEN</name> - <description>Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.</description> + <description>Sequence execution timeout interrupt enable.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191062,6 +197166,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>IPCMDDONE</name> @@ -191137,7 +197242,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>AHBBUSTIMEOUT</name> - <description>AHB Bus timeout interrupt.Refer Interrupts chapter for more details.</description> + <description>AHB Bus timeout interrupt.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191228,7 +197333,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>REGIONEN</name> - <description>AHB RX Buffer address region funciton enable</description> + <description>AHB RX Buffer address region function enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191274,7 +197379,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>REGIONEN</name> - <description>AHB RX Buffer address region funciton enable</description> + <description>AHB RX Buffer address region function enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191320,7 +197425,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>REGIONEN</name> - <description>AHB RX Buffer address region funciton enable</description> + <description>AHB RX Buffer address region function enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191366,7 +197471,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>REGIONEN</name> - <description>AHB RX Buffer address region funciton enable</description> + <description>AHB RX Buffer address region function enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191500,12 +197605,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CSINTERVALUNIT_0</name> + <name>val0</name> <description>The CS interval unit is 1 serial clock cycle</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CSINTERVALUNIT_1</name> + <name>val1</name> <description>The CS interval unit is 256 serial clock cycle</description> <value>0x1</value> </enumeratedValue> @@ -191513,7 +197618,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>CSINTERVAL</name> - <description>This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.</description> + <description>This field is used to set the minimum interval between flash device chip select deassertion and flash device chip select assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> @@ -191562,7 +197667,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>AWRWAIT</name> - <description>For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface</description> + <description>For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> <access>read-write</access> @@ -191575,50 +197680,50 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AWRWAITUNIT_0</name> - <description>The AWRWAIT unit is 2 ahb clock cycle</description> + <name>val0</name> + <description>The AWRWAIT unit is 2 AHB clock cycle</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_1</name> - <description>The AWRWAIT unit is 8 ahb clock cycle</description> + <name>val1</name> + <description>The AWRWAIT unit is 8 AHB clock cycle</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_2</name> - <description>The AWRWAIT unit is 32 ahb clock cycle</description> + <name>val2</name> + <description>The AWRWAIT unit is 32 AHB clock cycle</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_3</name> - <description>The AWRWAIT unit is 128 ahb clock cycle</description> + <name>val3</name> + <description>The AWRWAIT unit is 128 AHB clock cycle</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_4</name> - <description>The AWRWAIT unit is 512 ahb clock cycle</description> + <name>val4</name> + <description>The AWRWAIT unit is 512 AHB clock cycle</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_5</name> - <description>The AWRWAIT unit is 2048 ahb clock cycle</description> + <name>val5</name> + <description>The AWRWAIT unit is 2048 AHB clock cycle</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_6</name> - <description>The AWRWAIT unit is 8192 ahb clock cycle</description> + <name>val6</name> + <description>The AWRWAIT unit is 8192 AHB clock cycle</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>AWRWAITUNIT_7</name> - <description>The AWRWAIT unit is 32768 ahb clock cycle</description> + <name>val7</name> + <description>The AWRWAIT unit is 32768 AHB clock cycle</description> <value>0x7</value> </enumeratedValue> </enumeratedValues> </field> <field> <name>CLRINSTRPTR</name> - <description>Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.</description> + <description>Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191636,19 +197741,19 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>WMOPT1</name> - <description>Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.</description> + <description>Write mask option bit 1. This option bit could be used to remove AHB and IP write burst start address alignment limitation.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> <name>DISABLE</name> - <description>DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode.</description> + <description>DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB/IP write burst start address alignment when flash is accessed in individual mode.</description> <value>0</value> </enumeratedValue> <enumeratedValue> <name>ENABLE</name> - <description>DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.</description> + <description>DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB/IP write burst start address alignment when flash is accessed in individual mode.</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -191661,12 +197766,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WMENA_0</name> - <description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.</description> + <name>val0</name> + <description>Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WMENA_1</name> + <name>val1</name> <description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.</description> <value>0x1</value> </enumeratedValue> @@ -191680,12 +197785,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WMENB_0</name> - <description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.</description> + <name>val0</name> + <description>Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WMENB_1</name> + <name>val1</name> <description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.</description> <value>0x1</value> </enumeratedValue> @@ -191804,12 +197909,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RXDMAEN_0</name> + <name>val0</name> <description>IP RX FIFO would be read by processor.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RXDMAEN_1</name> + <name>val1</name> <description>IP RX FIFO would be read by DMA.</description> <value>0x1</value> </enumeratedValue> @@ -191817,7 +197922,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RXWMRK</name> - <description>Watermark level is (RXWMRK+1)*64 Bits.</description> + <description>Watermark level is (RXWMRK+1)*64 bits.</description> <bitOffset>2</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> @@ -191848,12 +197953,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TXDMAEN_0</name> + <name>val0</name> <description>IP TX FIFO would be filled by processor.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TXDMAEN_1</name> + <name>val1</name> <description>IP TX FIFO would be filled by DMA.</description> <value>0x1</value> </enumeratedValue> @@ -191889,7 +197994,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>DLLRESET</name> - <description>Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).</description> + <description>DLL reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -191948,22 +198053,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>ARBCMDSRC_0</name> - <description>Triggered by AHB read command (triggered by AHB read).</description> + <name>val0</name> + <description>Triggered by AHB read command.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ARBCMDSRC_1</name> - <description>Triggered by AHB write command (triggered by AHB Write).</description> + <name>val1</name> + <description>Triggered by AHB write command.</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ARBCMDSRC_2</name> - <description>Triggered by IP command (triggered by setting register bit IPCMD.TRG).</description> + <name>val2</name> + <description>Triggered by IP command (triggered by setting register bit IPCMD[TRG]).</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>ARBCMDSRC_3</name> + <name>val3</name> <description>Triggered by suspended command (resumed).</description> <value>0x3</value> </enumeratedValue> @@ -191995,32 +198100,32 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AHBCMDERRCODE_0</name> + <name>val0</name> <description>No error.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AHBCMDERRCODE_2</name> + <name>val2</name> <description>AHB Write command with JMP_ON_CS instruction used in the sequence.</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>AHBCMDERRCODE_3</name> + <name>val3</name> <description>There is unknown instruction opcode in the sequence.</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>AHBCMDERRCODE_4</name> + <name>val4</name> <description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>AHBCMDERRCODE_5</name> + <name>val5</name> <description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>AHBCMDERRCODE_14</name> + <name>val6</name> <description>Sequence execution timeout.</description> <value>0xE</value> </enumeratedValue> @@ -192028,7 +198133,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>IPCMDERRID</name> - <description>Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).</description> + <description>Indicates the sequence Index when IP command error detected.</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> <access>read-only</access> @@ -192041,42 +198146,42 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>IPCMDERRCODE_0</name> + <name>val0</name> <description>No error.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_2</name> + <name>val2</name> <description>IP command with JMP_ON_CS instruction used in the sequence.</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_3</name> + <name>val3</name> <description>There is unknown instruction opcode in the sequence.</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_4</name> + <name>val4</name> <description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_5</name> + <name>val5</name> <description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_6</name> + <name>val6</name> <description>Flash access start address exceed the whole flash address range (A1/A2/B1/B2).</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_14</name> + <name>val7</name> <description>Sequence execution timeout.</description> <value>0xE</value> </enumeratedValue> <enumeratedValue> - <name>IPCMDERRCODE_15</name> + <name>val8</name> <description>Flash boundary crossed.</description> <value>0xF</value> </enumeratedValue> @@ -203230,6 +209335,58 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>HSC_0</name> + <description>Number of pixels to skip minus 1</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_1</name> + <description>Number of pixels to skip minus 1</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_2</name> + <description>Number of pixels to skip minus 1</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_3</name> + <description>Number of pixels to skip minus 1</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_4</name> + <description>Number of pixels to skip minus 1</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_5</name> + <description>Number of pixels to skip minus 1</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_6</name> + <description>Number of pixels to skip minus 1</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_7</name> + <description>Number of pixels to skip minus 1</description> + <value>0x7</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_8</name> + <description>Number of pixels to skip minus 1</description> + <value>0x8</value> + </enumeratedValue> + <enumeratedValue> + <name>HSC_9</name> + <description>Number of pixels to skip minus 1</description> + <value>0x9</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>VSC</name> @@ -203237,6 +209394,58 @@ SPDX-License-Identifier: BSD-3-Clause <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>VSC_0</name> + <description>Number of rows to skip minus 1</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_1</name> + <description>Number of rows to skip minus 1</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_2</name> + <description>Number of rows to skip minus 1</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_3</name> + <description>Number of rows to skip minus 1</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_4</name> + <description>Number of rows to skip minus 1</description> + <value>0x4</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_5</name> + <description>Number of rows to skip minus 1</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_6</name> + <description>Number of rows to skip minus 1</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_7</name> + <description>Number of rows to skip minus 1</description> + <value>0x7</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_8</name> + <description>Number of rows to skip minus 1</description> + <value>0x8</value> + </enumeratedValue> + <enumeratedValue> + <name>VSC_9</name> + <description>Number of rows to skip minus 1</description> + <value>0x9</value> + </enumeratedValue> + </enumeratedValues> </field> <field> <name>LVRM</name> @@ -204506,47 +210715,47 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BLKSIZE_0</name> + <name>BLK_ATT_i</name> <description>No data transfer</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_1</name> + <name>BLK_ATT_h</name> <description>1 byte</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_2</name> + <name>BLK_ATT_g</name> <description>2 bytes</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_3</name> + <name>BLK_ATT_f</name> <description>3 bytes</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_4</name> + <name>BLK_ATT_e</name> <description>4 bytes</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_511</name> + <name>BLK_ATT_d</name> <description>511 bytes</description> <value>0x1FF</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_512</name> + <name>BLK_ATT_c</name> <description>512 bytes</description> <value>0x200</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_2048</name> + <name>BLK_ATT_b</name> <description>2048 bytes</description> <value>0x800</value> </enumeratedValue> <enumeratedValue> - <name>BLKSIZE_4096</name> + <name>BLK_ATT_a</name> <description>4096 bytes</description> <value>0x1000</value> </enumeratedValue> @@ -204560,22 +210769,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BLKCNT_0</name> + <name>BLKCNT_d</name> <description>Stop count</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BLKCNT_1</name> + <name>BLKCNT_c</name> <description>1 block</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>BLKCNT_2</name> + <name>BLKCNT_b</name> <description>2 blocks</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>BLKCNT_65535</name> + <name>BLKCNT_a</name> <description>65535 blocks</description> <value>0xFFFF</value> </enumeratedValue> @@ -204618,22 +210827,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RSPTYP_0</name> + <name>RSPTYP_a</name> <description>No response</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RSPTYP_1</name> + <name>RSPTYP_b</name> <description>Response length 136</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>RSPTYP_2</name> + <name>RSPTYP_c</name> <description>Response length 48</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>RSPTYP_3</name> + <name>RSPTYP_d</name> <description>Response length 48, check busy after response</description> <value>0x3</value> </enumeratedValue> @@ -204647,12 +210856,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CCCEN_0</name> + <name>CCCEN_b</name> <description>Disables command CRC check</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCCEN_1</name> + <name>CCCEN_a</name> <description>Enables command CRC check</description> <value>0x1</value> </enumeratedValue> @@ -204666,12 +210875,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CICEN_0</name> + <name>CICEN_b</name> <description>Disable command index check</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CICEN_1</name> + <name>CICEN_a</name> <description>Enables command index check</description> <value>0x1</value> </enumeratedValue> @@ -204685,12 +210894,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DPSEL_0</name> + <name>DPSEL_b</name> <description>No data present</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DPSEL_1</name> + <name>DPSEL_a</name> <description>Data present</description> <value>0x1</value> </enumeratedValue> @@ -204704,22 +210913,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CMDTYP_0</name> + <name>CMDTYP_d</name> <description>Normal other commands</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CMDTYP_1</name> + <name>CMDTYP_c</name> <description>Suspend CMD52 for writing bus suspend in CCCR</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>CMDTYP_2</name> + <name>CMDTYP_b</name> <description>Resume CMD52 for writing function select in CCCR</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>CMDTYP_3</name> + <name>CMDTYP_a</name> <description>Abort CMD12, CMD52 for writing I/O Abort in CCCR</description> <value>0x3</value> </enumeratedValue> @@ -204841,12 +211050,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>CIHB_0</name> + <name>CIHB_a</name> <description>Can issue command using only CMD line</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CIHB_1</name> + <name>CIHB_b</name> <description>Cannot issue command</description> <value>0x1</value> </enumeratedValue> @@ -204860,12 +211069,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>CDIHB_0</name> + <name>CDIHB_b</name> <description>Can issue command that uses the DATA line</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CDIHB_1</name> + <name>CDIHB_A</name> <description>Cannot issue command that uses the DATA line</description> <value>0x1</value> </enumeratedValue> @@ -204879,12 +211088,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>DLA_0</name> + <name>DLA_A</name> <description>DATA line inactive</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DLA_1</name> + <name>DLA_b</name> <description>DATA line active</description> <value>0x1</value> </enumeratedValue> @@ -204898,12 +211107,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>SDSTB_0</name> + <name>SDSTB_b</name> <description>Clock is changing frequency and not stable.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SDSTB_1</name> + <name>SDSTB_A</name> <description>Clock is stable.</description> <value>0x1</value> </enumeratedValue> @@ -204917,12 +211126,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>IPGOFF_0</name> + <name>IPGOFF_b</name> <description>Peripheral clock is active.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IPGOFF_1</name> + <name>IPGOFF_A</name> <description>Peripheral clock is gated off.</description> <value>0x1</value> </enumeratedValue> @@ -204936,12 +211145,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>HCKOFF_0</name> + <name>HCKOFF_B</name> <description>HCLK is active.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>HCKOFF_1</name> + <name>HCKOFF_A</name> <description>HCLK is gated off.</description> <value>0x1</value> </enumeratedValue> @@ -204955,12 +211164,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>PEROFF_0</name> + <name>PEROFF_b</name> <description>IPG_PERCLK is active.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>PEROFF_1</name> + <name>PEROFF_A</name> <description>IPG_PERCLK is gated off.</description> <value>0x1</value> </enumeratedValue> @@ -204974,12 +211183,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>SDOFF_0</name> + <name>SDOFF_D</name> <description>SD clock is active.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SDOFF_1</name> + <name>SDOFF_C</name> <description>SD clock is gated off.</description> <value>0x1</value> </enumeratedValue> @@ -204993,12 +211202,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>WTA_0</name> + <name>WTA_B</name> <description>No valid data</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WTA_1</name> + <name>WTA_A</name> <description>Transferring data</description> <value>0x1</value> </enumeratedValue> @@ -205012,12 +211221,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>RTA_0</name> + <name>RTA_B</name> <description>No valid data</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RTA_1</name> + <name>RTA_A</name> <description>Transferring data</description> <value>0x1</value> </enumeratedValue> @@ -205031,12 +211240,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>BWEN_0</name> + <name>BWEN_b</name> <description>Write disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BWEN_1</name> + <name>BWEN_A</name> <description>Write enable</description> <value>0x1</value> </enumeratedValue> @@ -205050,12 +211259,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>BREN_0</name> + <name>BREN_B</name> <description>Read disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BREN_1</name> + <name>BREN_A</name> <description>Read enable</description> <value>0x1</value> </enumeratedValue> @@ -205063,18 +211272,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RTR</name> - <description>Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)</description> + <description>Re-Tuning Request (only for SD3.0 SDR104 mode,and eMMC HS200 mode)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>RTR_0</name> + <name>RTR_B</name> <description>Fixed or well tuned sampling clock</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RTR_1</name> + <name>RTR_A</name> <description>Sampling clock needs re-tuning</description> <value>0x1</value> </enumeratedValue> @@ -205088,12 +211297,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>TSCD_0</name> + <name>TSCD_B</name> <description>Delay cell select change is not finished.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TSCD_1</name> + <name>TSCD_A</name> <description>Delay cell select change is finished.</description> <value>0x1</value> </enumeratedValue> @@ -205107,12 +211316,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>CINST_0</name> + <name>CINST_a</name> <description>Power on reset or no card</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINST_1</name> + <name>CINST_B</name> <description>Card inserted</description> <value>0x1</value> </enumeratedValue> @@ -205193,17 +211402,17 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTW_0</name> + <name>DTW_C</name> <description>1-bit mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTW_1</name> + <name>DTW_B</name> <description>4-bit mode</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>DTW_2</name> + <name>DTW_A</name> <description>8-bit mode</description> <value>0x2</value> </enumeratedValue> @@ -205217,12 +211426,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>D3CD_0</name> + <name>D3CD_B</name> <description>DATA3 does not monitor card insertion</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>D3CD_1</name> + <name>D3CD_A</name> <description>DATA3 as card detection pin</description> <value>0x1</value> </enumeratedValue> @@ -205236,17 +211445,17 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EMODE_0</name> + <name>EMODE_A</name> <description>Big endian mode</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EMODE_1</name> + <name>EMODE_B</name> <description>Half word big endian mode</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>EMODE_2</name> + <name>EMODE_C</name> <description>Little endian mode</description> <value>0x2</value> </enumeratedValue> @@ -205260,17 +211469,17 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DMASEL_0</name> + <name>DMASEL_A</name> <description>No DMA or simple DMA is selected.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMASEL_1</name> + <name>DMASEL_b</name> <description>ADMA1 is selected.</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>DMASEL_2</name> + <name>DMASEL_C</name> <description>ADMA2 is selected.</description> <value>0x2</value> </enumeratedValue> @@ -205284,12 +211493,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SABGREQ_0</name> + <name>SABGREQ_b</name> <description>Transfer</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SABGREQ_1</name> + <name>SABGREQ_A</name> <description>Stop</description> <value>0x1</value> </enumeratedValue> @@ -205303,12 +211512,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CREQ_0</name> + <name>CREQ_B</name> <description>No effect</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CREQ_1</name> + <name>CREQ_A</name> <description>Restart</description> <value>0x1</value> </enumeratedValue> @@ -205322,12 +211531,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RWCTL_0</name> + <name>RWCTL_b</name> <description>Disables read wait control and stop SD clock at block gap when SABGREQ field is set</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RWCTL_1</name> + <name>RWCTL_A</name> <description>Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set</description> <value>0x1</value> </enumeratedValue> @@ -205341,12 +211550,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>IABG_0</name> + <name>IABG_b</name> <description>Disables interrupt at block gap</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>IABG_1</name> + <name>IABG_A</name> <description>Enables interrupt at block gap</description> <value>0x1</value> </enumeratedValue> @@ -205367,12 +211576,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WECINT_0</name> + <name>WECINT_A</name> <description>Disables wakeup event enable on card interrupt</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WECINT_1</name> + <name>WECINT_b</name> <description>Enables wakeup event enable on card interrupt</description> <value>0x1</value> </enumeratedValue> @@ -205386,12 +211595,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WECINS_0</name> + <name>WECINS_b</name> <description>Disable wakeup event enable on SD card insertion</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WECINS_1</name> + <name>WECINS_A</name> <description>Enable wakeup event enable on SD card insertion</description> <value>0x1</value> </enumeratedValue> @@ -205405,12 +211614,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>WECRM_0</name> + <name>WECRM_B</name> <description>Disables wakeup event enable on SD card removal</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>WECRM_1</name> + <name>WECRM_A</name> <description>Enables wakeup event enable on SD card removal</description> <value>0x1</value> </enumeratedValue> @@ -205424,7 +211633,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BURST_LEN_EN_1</name> + <name>BURST_A</name> <description>Burst length is enabled for INCR.</description> <value>#xx1</value> </enumeratedValue> @@ -205438,12 +211647,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>NON_EXACT_BLK_RD_0</name> + <name>EXACT_B</name> <description>The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>NON_EXACT_BLK_RD_1</name> + <name>EXACT_A</name> <description>The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.</description> <value>0x1</value> </enumeratedValue> @@ -205468,22 +211677,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DVS_0</name> + <name>DVS_A</name> <description>Divide-by-1</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DVS_1</name> + <name>DVS_B</name> <description>Divide-by-2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>DVS_14</name> + <name>DVS_C</name> <description>Divide-by-15</description> <value>0xE</value> </enumeratedValue> <enumeratedValue> - <name>DVS_15</name> + <name>DVS_D</name> <description>Divide-by-16</description> <value>0xF</value> </enumeratedValue> @@ -205504,82 +211713,82 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTOCV_0</name> + <name>DTOCV_Q</name> <description>SDCLK x 2 14</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_1</name> + <name>DTOCV_P</name> <description>SDCLK x 2 15</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_2</name> + <name>DTOCV_O</name> <description>SDCLK x 2 16</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_3</name> + <name>DTOCV_N</name> <description>SDCLK x 2 17</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_4</name> + <name>DTOCV_M</name> <description>SDCLK x 2 18</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_5</name> + <name>DTOCV_L</name> <description>SDCLK x 2 19</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_6</name> + <name>DTOCV_K</name> <description>SDCLK x 2 20</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_7</name> + <name>DTOCV_J</name> <description>SDCLK x 2 21</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_8</name> + <name>DTOCV_I</name> <description>SDCLK x 2 22</description> <value>0x8</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_9</name> + <name>DTOCV_H</name> <description>SDCLK x 2 23</description> <value>0x9</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_10</name> + <name>DTOCV_G</name> <description>SDCLK x 2 24</description> <value>0xA</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_11</name> + <name>DTOCV_F</name> <description>SDCLK x 2 25</description> <value>0xB</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_12</name> + <name>DTOCV_E</name> <description>SDCLK x 2 26</description> <value>0xC</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_13</name> + <name>DTOCV_D</name> <description>SDCLK x 2 27</description> <value>0xD</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_14</name> + <name>DTOCV_C</name> <description>SDCLK x 2 28</description> <value>0xE</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_15</name> + <name>DTOCV_A</name> <description>SDCLK x 2 29</description> <value>0xF</value> </enumeratedValue> @@ -205600,12 +211809,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RSTA_0</name> + <name>RSTA_B</name> <description>No reset</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RSTA_1</name> + <name>RSTA_A</name> <description>Reset</description> <value>0x1</value> </enumeratedValue> @@ -205619,12 +211828,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RSTC_0</name> + <name>RSTC_B</name> <description>No reset</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RSTC_1</name> + <name>RSTC_A</name> <description>Reset</description> <value>0x1</value> </enumeratedValue> @@ -205638,12 +211847,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RSTD_0</name> + <name>RSTD_B</name> <description>No reset</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RSTD_1</name> + <name>RSTD_A</name> <description>Reset</description> <value>0x1</value> </enumeratedValue> @@ -205683,12 +211892,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CC_0</name> + <name>CC_B</name> <description>Command not complete</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CC_1</name> + <name>CC_A</name> <description>Command complete</description> <value>0x1</value> </enumeratedValue> @@ -205703,12 +211912,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>TC_0</name> + <name>TC_B</name> <description>Transfer does not complete</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TC_1</name> + <name>TC_A</name> <description>Transfer complete</description> <value>0x1</value> </enumeratedValue> @@ -205723,12 +211932,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>BGE_0</name> + <name>BGE_B</name> <description>No block gap event</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BGE_1</name> + <name>BGE_A</name> <description>Transaction stopped at block gap</description> <value>0x1</value> </enumeratedValue> @@ -205743,12 +211952,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>DINT_0</name> + <name>DINT_B</name> <description>No DMA interrupt</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DINT_1</name> + <name>DINT_A</name> <description>DMA interrupt is generated.</description> <value>0x1</value> </enumeratedValue> @@ -205763,12 +211972,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>BWR_0</name> + <name>BWR_B</name> <description>Not ready to write buffer</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BWR_1</name> + <name>BWR_A</name> <description>Ready to write buffer</description> <value>0x1</value> </enumeratedValue> @@ -205783,12 +211992,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>BRR_0</name> + <name>BRR_B</name> <description>Not ready to read buffer</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BRR_1</name> + <name>BRR_A</name> <description>Ready to read buffer</description> <value>0x1</value> </enumeratedValue> @@ -205803,12 +212012,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CINS_0</name> + <name>BWR_b</name> <description>Card state unstable or removed</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINS_1</name> + <name>BWR_A</name> <description>Card inserted</description> <value>0x1</value> </enumeratedValue> @@ -205823,12 +212032,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CRM_0</name> + <name>CRM_A</name> <description>Card state unstable or inserted</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CRM_1</name> + <name>CRM_b</name> <description>Card removed</description> <value>0x1</value> </enumeratedValue> @@ -205843,12 +212052,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CINT_0</name> + <name>CINT_A</name> <description>No card interrupt</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINT_1</name> + <name>CINT_b</name> <description>Generate card interrupt</description> <value>0x1</value> </enumeratedValue> @@ -205856,19 +212065,19 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RTE</name> - <description>Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)</description> + <description>Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>RTE_0</name> + <name>RTE_A</name> <description>Re-tuning is not required.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RTE_1</name> + <name>RTE_b</name> <description>Re-tuning should be performed.</description> <value>0x1</value> </enumeratedValue> @@ -205876,7 +212085,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>TP</name> - <description>Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)</description> + <description>Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -205898,12 +212107,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CTOE_0</name> + <name>CTOE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CTOE_1</name> + <name>CTOE_b</name> <description>Time out</description> <value>0x1</value> </enumeratedValue> @@ -205918,12 +212127,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CCE_0</name> + <name>CCE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCE_1</name> + <name>CCE_b</name> <description>CRC error generated</description> <value>0x1</value> </enumeratedValue> @@ -205938,12 +212147,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CEBE_0</name> + <name>CEBE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CEBE_1</name> + <name>CEBE_b</name> <description>End bit error generated</description> <value>0x1</value> </enumeratedValue> @@ -205958,12 +212167,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>CIE_0</name> + <name>CIE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CIE_1</name> + <name>CIE_b</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -205978,12 +212187,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>DTOE_0</name> + <name>DTOE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTOE_1</name> + <name>DTOE_b</name> <description>Time out</description> <value>0x1</value> </enumeratedValue> @@ -205998,12 +212207,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>DCE_0</name> + <name>DCE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DCE_1</name> + <name>DCE_b</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -206018,12 +212227,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>DEBE_0</name> + <name>DEBE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DEBE_1</name> + <name>DEBE_b</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -206038,12 +212247,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>AC12E_0</name> + <name>AC12E_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12E_1</name> + <name>AC12E_b</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -206051,7 +212260,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>TNE</name> - <description>Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)</description> + <description>Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -206066,12 +212275,12 @@ SPDX-License-Identifier: BSD-3-Clause <modifiedWriteValues>oneToClear</modifiedWriteValues> <enumeratedValues> <enumeratedValue> - <name>DMAE_0</name> + <name>DMAE_A</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMAE_1</name> + <name>DMAE_b</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -206096,12 +212305,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CCSEN_0</name> + <name>CCSEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCSEN_1</name> + <name>CCSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206115,12 +212324,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TCSEN_0</name> + <name>TCSEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TCSEN_1</name> + <name>TCSEN_A</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206134,12 +212343,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BGESEN_0</name> + <name>BGESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BGESEN_1</name> + <name>BGESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206153,12 +212362,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DINTSEN_0</name> + <name>DINTSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DINTSEN_1</name> + <name>DINTSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206172,12 +212381,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BWRSEN_0</name> + <name>BWRSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BWRSEN_1</name> + <name>BWRSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206191,12 +212400,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BRRSEN_0</name> + <name>BRRSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BRRSEN_1</name> + <name>BRREN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206210,12 +212419,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CINSSEN_0</name> + <name>CINSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINSSEN_1</name> + <name>CINSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206229,12 +212438,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CRMSEN_0</name> + <name>CRMSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CRMSEN_1</name> + <name>CRMSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206248,12 +212457,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CINTSEN_0</name> + <name>CINTSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINTSEN_1</name> + <name>CINTSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206267,12 +212476,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RTESEN_0</name> + <name>RTESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RTESEN_1</name> + <name>RTESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206286,12 +212495,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TPSEN_0</name> + <name>TPSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TPSEN_1</name> + <name>TPSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206305,12 +212514,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CTOESEN_0</name> + <name>CTOSEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CTOESEN_1</name> + <name>CTOSEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206324,12 +212533,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CCESEN_0</name> + <name>CCESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCESEN_1</name> + <name>CCESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206343,12 +212552,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CEBESEN_0</name> + <name>CEBESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CEBESEN_1</name> + <name>CEBESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206362,12 +212571,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CIESEN_0</name> + <name>CIESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CIESEN_1</name> + <name>CIESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206381,12 +212590,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTOESEN_0</name> + <name>DTOESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTOESEN_1</name> + <name>DTOESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206400,12 +212609,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DCESEN_0</name> + <name>DCESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DCESEN_1</name> + <name>DCESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206419,12 +212628,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DEBESEN_0</name> + <name>DBESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DEBESEN_1</name> + <name>DBESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206438,12 +212647,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AC12ESEN_0</name> + <name>AC12ESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12ESEN_1</name> + <name>AC12ESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206457,12 +212666,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TNESEN_0</name> + <name>TNESEN_A</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TNESEN_1</name> + <name>TNESEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206476,12 +212685,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DMAESEN_0</name> + <name>DMASEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMAESEN_1</name> + <name>DMASEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206506,12 +212715,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CCIEN_0</name> + <name>CCIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCIEN_1</name> + <name>CCIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206525,12 +212734,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TCIEN_0</name> + <name>TCIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TCIEN_1</name> + <name>TCIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206544,12 +212753,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BGEIEN_0</name> + <name>BGIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BGEIEN_1</name> + <name>BGIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206563,12 +212772,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DINTIEN_0</name> + <name>DINTIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DINTIEN_1</name> + <name>DINTIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206582,12 +212791,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BWRIEN_0</name> + <name>BWRIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BWRIEN_1</name> + <name>BWRIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206601,12 +212810,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BRRIEN_0</name> + <name>BRRIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BRRIEN_1</name> + <name>BRRIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206620,12 +212829,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CINSIEN_0</name> + <name>CINSIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINSIEN_1</name> + <name>CINSIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206639,12 +212848,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CRMIEN_0</name> + <name>CRMIEN_a</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CRMIEN_1</name> + <name>CRMIEN_b</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206658,12 +212867,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CINTIEN_0</name> + <name>CINTIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CINTIEN_1</name> + <name>CINTIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206677,12 +212886,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RTEIEN_0</name> + <name>RTEIEN_O</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RTEIEN_1</name> + <name>RTEIEN_N</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206696,12 +212905,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TPIEN_0</name> + <name>TPIEN_R</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TPIEN_1</name> + <name>TPIEN_Q</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206715,12 +212924,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CTOEIEN_0</name> + <name>CTOEIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CTOEIEN_1</name> + <name>CTOEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206734,12 +212943,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CCEIEN_0</name> + <name>CCEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CCEIEN_1</name> + <name>CCEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206753,12 +212962,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CEBEIEN_0</name> + <name>CEBEIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CEBEIEN_1</name> + <name>CEBEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206772,12 +212981,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CIEIEN_0</name> + <name>CIEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CIEIEN_1</name> + <name>CIEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206791,12 +213000,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTOEIEN_0</name> + <name>DTOEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTOEIEN_1</name> + <name>DTOEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206810,12 +213019,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DCEIEN_0</name> + <name>DCEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DCEIEN_1</name> + <name>DCEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206829,12 +213038,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DEBEIEN_0</name> + <name>DEBEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DEBEIEN_1</name> + <name>DEBEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206848,12 +213057,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AC12EIEN_0</name> + <name>AC12EIEN_b</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12EIEN_1</name> + <name>AC12EIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206867,12 +213076,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TNEIEN_0</name> + <name>TNEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TNEIEN_1</name> + <name>TNEIEN_a</name> <description>Enabled</description> <value>0x1</value> </enumeratedValue> @@ -206886,12 +213095,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DMAEIEN_0</name> + <name>DMAEIEN_B</name> <description>Masked</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMAEIEN_1</name> + <name>DMAEIEN_a</name> <description>Enable</description> <value>0x1</value> </enumeratedValue> @@ -206916,12 +213125,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AC12NE_0</name> + <name>AC12NE_B</name> <description>Executed</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12NE_1</name> + <name>AC12NE_a</name> <description>Not executed</description> <value>0x1</value> </enumeratedValue> @@ -206935,12 +213144,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AC12TOE_0</name> + <name>AC12TOE_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12TOE_1</name> + <name>AC12TOE_a</name> <description>Time out</description> <value>0x1</value> </enumeratedValue> @@ -206954,12 +213163,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AC12EBE_0</name> + <name>AC12EBE_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12EBE_1</name> + <name>AC12EBE_a</name> <description>End bit error generated</description> <value>0x1</value> </enumeratedValue> @@ -206973,12 +213182,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AC12CE_0</name> + <name>AC12CE_B</name> <description>No CRC error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12CE_1</name> + <name>AC12CE_a</name> <description>CRC error met in Auto CMD12/23 response</description> <value>0x1</value> </enumeratedValue> @@ -206992,12 +213201,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>AC12IE_0</name> + <name>AC12IE_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12IE_1</name> + <name>AC12IE_a</name> <description>Error, the CMD index in response is not CMD12/23</description> <value>0x1</value> </enumeratedValue> @@ -207011,12 +213220,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>CNIBAC12E_0</name> + <name>CNIBAC12E_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CNIBAC12E_1</name> + <name>CNIBAC12E_a</name> <description>Not issued</description> <value>0x1</value> </enumeratedValue> @@ -207030,12 +213239,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EXECUTE_TUNING_0</name> + <name>EX_TUN_B</name> <description>Tuning procedure is aborted</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EXECUTE_TUNING_1</name> + <name>ex_tun_a</name> <description>Start tuning procedure</description> <value>0x1</value> </enumeratedValue> @@ -207049,12 +213258,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SMP_CLK_SEL_0</name> + <name>SMP_CLK_B</name> <description>Fixed clock is used to sample data</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SMP_CLK_SEL_1</name> + <name>SMP_CLK_a</name> <description>Tuned clock is used to sample data</description> <value>0x1</value> </enumeratedValue> @@ -207100,12 +213309,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>USE_TUNING_SDR50_0</name> + <name>USE_TUNING_b</name> <description>SDR50 does not support tuning</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>USE_TUNING_SDR50_1</name> + <name>USE_TUNING_a</name> <description>SDR50 supports tuning</description> <value>0x1</value> </enumeratedValue> @@ -207119,22 +213328,22 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>MBL_0</name> + <name>MBL_a</name> <description>512 bytes</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>MBL_1</name> + <name>MBL_B</name> <description>1024 bytes</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>MBL_2</name> + <name>MBL_C</name> <description>2048 bytes</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>MBL_3</name> + <name>MBL_D</name> <description>4096 bytes</description> <value>0x3</value> </enumeratedValue> @@ -207148,12 +213357,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>ADMAS_0</name> + <name>ADMAS_B</name> <description>Advanced DMA not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ADMAS_1</name> + <name>ADMAS_a</name> <description>Advanced DMA supported</description> <value>0x1</value> </enumeratedValue> @@ -207167,12 +213376,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>HSS_0</name> + <name>HSS_B</name> <description>High speed not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>HSS_1</name> + <name>HSS_a</name> <description>High speed supported</description> <value>0x1</value> </enumeratedValue> @@ -207186,12 +213395,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>DMAS_0</name> + <name>DMAS_B</name> <description>DMA not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMAS_1</name> + <name>DMAS_a</name> <description>DMA supported</description> <value>0x1</value> </enumeratedValue> @@ -207205,12 +213414,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>SRS_0</name> + <name>SRS_B</name> <description>Not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SRS_1</name> + <name>SRS_a</name> <description>Supported</description> <value>0x1</value> </enumeratedValue> @@ -207224,12 +213433,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>VS33_0</name> + <name>VS33_b</name> <description>3.3 V not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>VS33_1</name> + <name>VS33_a</name> <description>3.3 V supported</description> <value>0x1</value> </enumeratedValue> @@ -207243,12 +213452,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>VS30_0</name> + <name>VS30_b</name> <description>3.0 V not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>VS30_1</name> + <name>VS30_a</name> <description>3.0 V supported</description> <value>0x1</value> </enumeratedValue> @@ -207262,12 +213471,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>VS18_0</name> + <name>VS18_B</name> <description>1.8 V not supported</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>VS18_1</name> + <name>VS18_a</name> <description>1.8 V supported</description> <value>0x1</value> </enumeratedValue> @@ -207331,12 +213540,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DMAEN_0</name> + <name>DMAIN_B</name> <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DMAEN_1</name> + <name>DMAIN_a</name> <description>Enable</description> <value>0x1</value> </enumeratedValue> @@ -207350,12 +213559,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BCEN_0</name> + <name>BCEN_B</name> <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BCEN_1</name> + <name>BCEN_a</name> <description>Enable</description> <value>0x1</value> </enumeratedValue> @@ -207369,12 +213578,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AC12EN_0</name> + <name>AC12EN_B</name> <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12EN_1</name> + <name>AC12EN_a</name> <description>Enable</description> <value>0x1</value> </enumeratedValue> @@ -207395,12 +213604,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTDSEL_0</name> + <name>DTDSEL_B</name> <description>Write (Host to card)</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTDSEL_1</name> + <name>DTDSEL_a</name> <description>Read (Card to host)</description> <value>0x1</value> </enumeratedValue> @@ -207414,12 +213623,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>MSBSEL_0</name> + <name>MSBSEL_B</name> <description>Single block</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>MSBSEL_1</name> + <name>MSBSEL_a</name> <description>Multiple blocks</description> <value>0x1</value> </enumeratedValue> @@ -207441,18 +213650,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>EXE_TUNE</name> - <description>Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)</description> + <description>Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>EXE_TUNE_0</name> + <name>EXE_TUNE_D</name> <description>Not tuned or tuning completed</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>EXE_TUNE_1</name> + <name>EXE_TUNE_C</name> <description>Execute tuning</description> <value>0x1</value> </enumeratedValue> @@ -207466,12 +213675,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SMP_CLK_SEL_0</name> + <name>SMPSEL_B</name> <description>Fixed clock is used to sample data / cmd</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SMP_CLK_SEL_1</name> + <name>SMPSEL_a</name> <description>Tuned clock is used to sample data / cmd</description> <value>0x1</value> </enumeratedValue> @@ -207479,18 +213688,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>AUTO_TUNE_EN</name> - <description>Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)</description> + <description>Auto tuning enable (Only used for SD3.0, SDR104 mode and and eMMC HS200 mode)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AUTO_TUNE_EN_0</name> + <name>AUTOTUNE_B</name> <description>Disable auto tuning</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AUTO_TUNE_EN_1</name> + <name>AUTO_TUNE_a</name> <description>Enable auto tuning</description> <value>0x1</value> </enumeratedValue> @@ -207498,18 +213707,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>FBCLK_SEL</name> - <description>Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)</description> + <description>Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>FBCLK_SEL_0</name> + <name>FBCLK_B</name> <description>Feedback clock comes from the loopback CLK</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>FBCLK_SEL_1</name> + <name>FBCLK_a</name> <description>Feedback clock comes from the ipp_card_clk_out</description> <value>0x1</value> </enumeratedValue> @@ -207671,12 +213880,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>ADMALME_0</name> + <name>ADMAES_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ADMALME_1</name> + <name>ADMAES_a</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -207690,12 +213899,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-only</access> <enumeratedValues> <enumeratedValue> - <name>ADMADCE_0</name> + <name>ADMADCE_B</name> <description>No error</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ADMADCE_1</name> + <name>ADMADCE_a</name> <description>Error</description> <value>0x1</value> </enumeratedValue> @@ -207925,12 +214134,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>VSELECT_0</name> + <name>VSELECT_B</name> <description>Change the voltage to high voltage range, around 3.0 V</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>VSELECT_1</name> + <name>VSELECT_a</name> <description>Change the voltage to low voltage range, around 1.8 V</description> <value>0x1</value> </enumeratedValue> @@ -207944,12 +214153,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CONFLICT_CHK_EN_0</name> + <name>CONFLICT_CHK_EN_a</name> <description>Conflict check disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CONFLICT_CHK_EN_1</name> + <name>CONFLICT_CHK_EN_b</name> <description>Conflict check enable</description> <value>0x1</value> </enumeratedValue> @@ -207963,12 +214172,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>AC12_WR_CHKBUSY_EN_0</name> + <name>AC12_WR_CHKBUSY_EN_a</name> <description>Do not check busy after auto CMD12 for write data packet</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>AC12_WR_CHKBUSY_EN_1</name> + <name>AC12_WR_CHKBUSY_EN_b</name> <description>Check busy after auto CMD12 for write data packet</description> <value>0x1</value> </enumeratedValue> @@ -207982,12 +214191,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>FRC_SDCLK_ON_0</name> + <name>FRC_SDCLK_ON_a</name> <description>CLK active or inactive is fully controlled by the hardware.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>FRC_SDCLK_ON_1</name> + <name>FRC_SDCLK_ON_B</name> <description>Force CLK active</description> <value>0x1</value> </enumeratedValue> @@ -208001,12 +214210,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CRC_CHK_DIS_0</name> + <name>CRC_CHK_DIS_a</name> <description>Check CRC16 for every read data packet and check CRC fields for every write data packet</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CRC_CHK_DIS_1</name> + <name>CRC_CHK_DIS_B</name> <description>Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet</description> <value>0x1</value> </enumeratedValue> @@ -208020,12 +214229,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CMD_BYTE_EN_0</name> + <name>CMD_BYTE_EN_a</name> <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CMD_BYTE_EN_1</name> + <name>CMD_BYTE_EN_b</name> <description>Enable</description> <value>0x1</value> </enumeratedValue> @@ -208035,7 +214244,7 @@ SPDX-License-Identifier: BSD-3-Clause </register> <register> <name>MMC_BOOT</name> - <description>MMC Boot</description> + <description>eMMC Boot</description> <addressOffset>0xC4</addressOffset> <size>32</size> <access>read-write</access> @@ -208050,52 +214259,52 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DTOCV_ACK_0</name> + <name>DTOCV_ACK_a</name> <description>SDCLK x 2^14</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_1</name> + <name>DTOCV_ACK_b</name> <description>SDCLK x 2^15</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_2</name> + <name>DTOCV_ACK_c</name> <description>SDCLK x 2^16</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_3</name> + <name>DTOCV_ACK_d</name> <description>SDCLK x 2^17</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_4</name> + <name>DTOCV_ACK_e</name> <description>SDCLK x 2^18</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_5</name> + <name>DTOCV_ACK_f</name> <description>SDCLK x 2^19</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_6</name> + <name>DTOCV_ACK_g</name> <description>SDCLK x 2^20</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_7</name> + <name>DTOCV_ACK_h</name> <description>SDCLK x 2^21</description> <value>0x7</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_14</name> + <name>DTOCV_ACK_i</name> <description>SDCLK x 2^28</description> <value>0xE</value> </enumeratedValue> <enumeratedValue> - <name>DTOCV_ACK_15</name> + <name>DTOCV_ACK_j</name> <description>SDCLK x 2^29</description> <value>0xF</value> </enumeratedValue> @@ -208109,12 +214318,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BOOT_ACK_0</name> + <name>BOOT_ACK_a</name> <description>No ack</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BOOT_ACK_1</name> + <name>BOOT_ACK_b</name> <description>Ack</description> <value>0x1</value> </enumeratedValue> @@ -208128,12 +214337,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BOOT_MODE_0</name> + <name>BOOT_mode_a</name> <description>Normal boot</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BOOT_MODE_1</name> + <name>BOOT_mode_b</name> <description>Alternative boot</description> <value>0x1</value> </enumeratedValue> @@ -208147,12 +214356,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>BOOT_EN_0</name> + <name>BOOT_en_a</name> <description>Fast boot disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>BOOT_EN_1</name> + <name>BOOT_en_b</name> <description>Fast boot enable</description> <value>0x1</value> </enumeratedValue> @@ -208173,12 +214382,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>DISABLE_TIME_OUT_0</name> + <name>disable_timeout_a</name> <description>Enable time out</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DISABLE_TIME_OUT_1</name> + <name>disable_timeout_b</name> <description>Disable time out</description> <value>0x1</value> </enumeratedValue> @@ -208210,12 +214419,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>CARD_INT_D3_TEST_0</name> + <name>CARD_INT_D3_a</name> <description>Check the card interrupt only when DATA3 is high.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>CARD_INT_D3_TEST_1</name> + <name>CARD_INT_D3_B</name> <description>Check the card interrupt by ignoring the status of DATA3.</description> <value>0x1</value> </enumeratedValue> @@ -208243,12 +214452,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TUNING_CMD_EN_0</name> + <name>TUNING_CMD_EN_a</name> <description>Auto tuning circuit does not check the CMD line.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TUNING_CMD_EN_1</name> + <name>TUNING_CMD_EN_B</name> <description>Auto tuning circuit checks the CMD line.</description> <value>0x1</value> </enumeratedValue> @@ -208262,12 +214471,12 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ACMD23_ARGU2_EN_0</name> + <name>ACMD23_ARGU2_EN_B</name> <description>Disable</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ACMD23_ARGU2_EN_1</name> + <name>ACMD23_ARGU2_EN_a</name> <description>Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.</description> <value>0x1</value> </enumeratedValue> @@ -208373,6 +214582,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TS_TIMER</name> @@ -211499,6 +217709,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TF0</name> @@ -216736,6 +222947,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>IPCMDDONE</name> @@ -223070,7 +229282,6 @@ SPDX-License-Identifier: BSD-3-Clause <name>SPDIF</name> <description>SPDIF</description> <groupName>SPDIF</groupName> - <prependToName>SPDIF_</prependToName> <baseAddress>0x40380000</baseAddress> <addressBlock> <offset>0</offset> @@ -223093,23 +229304,23 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>USrc_Sel</name> - <description>no description available</description> + <description>USrc_Sel</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>USrc_Sel_0</name> + <name>none</name> <description>No embedded U channel</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>USrc_Sel_1</name> + <name>spdif_rxblock</name> <description>U channel from SPDIF receive block (CD mode)</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>USrc_Sel_3</name> + <name>chip_transmit</name> <description>U channel from on chip transmitter</description> <value>0x3</value> </enumeratedValue> @@ -223117,23 +229328,23 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>TxSel</name> - <description>no description available</description> + <description>TxSel</description> <bitOffset>2</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxSel_0</name> + <name>off_out0</name> <description>Off and output 0</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxSel_1</name> + <name>feedthru</name> <description>Feed-through SPDIFIN</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TxSel_5</name> + <name>normal_op</name> <description>Tx Normal operation</description> <value>0x5</value> </enumeratedValue> @@ -223141,56 +229352,85 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>ValCtrl</name> - <description>no description available</description> + <description>ValCtrl</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ValCtrl_0</name> + <name>always_set</name> <description>Outgoing Validity always set</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ValCtrl_1</name> + <name>always_clear</name> <description>Outgoing Validity always clear</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> </field> <field> + <name>InputSrcSel</name> + <description>InputSrcSel</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>spdif_in</name> + <description>SPDIF_IN</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>none_sel_1</name> + <description>None</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>none_sel_2</name> + <description>None</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>none_sel_3</name> + <description>None</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> <name>DMA_TX_En</name> - <description>DMA Transmit Request Enable (Tx FIFO empty)</description> + <description>DMA_TX_En</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DMA_Rx_En</name> - <description>DMA Receive Request Enable (RX FIFO full)</description> + <description>DMA_Rx_En</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxFIFO_Ctrl</name> - <description>no description available</description> + <description>TxFIFO_Ctrl</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxFIFO_Ctrl_0</name> + <name>send_zero</name> <description>Send out digital zero on SPDIF Tx</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxFIFO_Ctrl_1</name> + <name>normal</name> <description>Tx Normal operation</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TxFIFO_Ctrl_2</name> + <name>reset_one</name> <description>Reset to 1 sample remaining</description> <value>0x2</value> </enumeratedValue> @@ -223198,42 +229438,42 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>soft_reset</name> - <description>When write 1 to this bit, it will cause SPDIF software reset</description> + <description>soft_reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LOW_POWER</name> - <description>When write 1 to this bit, it will cause SPDIF enter low-power mode</description> + <description>LOW_POWER</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxFIFOEmpty_Sel</name> - <description>no description available</description> + <description>TxFIFOEmpty_Sel</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxFIFOEmpty_Sel_0</name> + <name>empty_int_0</name> <description>Empty interrupt if 0 sample in Tx left and right FIFOs</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxFIFOEmpty_Sel_1</name> + <name>empty_int_4</name> <description>Empty interrupt if at most 4 sample in Tx left and right FIFOs</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TxFIFOEmpty_Sel_2</name> + <name>empty_int_8</name> <description>Empty interrupt if at most 8 sample in Tx left and right FIFOs</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>TxFIFOEmpty_Sel_3</name> + <name>empty_int_12</name> <description>Empty interrupt if at most 12 sample in Tx left and right FIFOs</description> <value>0x3</value> </enumeratedValue> @@ -223241,18 +229481,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>TxAutoSync</name> - <description>no description available</description> + <description>TxAutoSync</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxAutoSync_0</name> + <name>off</name> <description>Tx FIFO auto sync off</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxAutoSync_1</name> + <name>on</name> <description>Tx FIFO auto sync on</description> <value>0x1</value> </enumeratedValue> @@ -223260,18 +229500,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RxAutoSync</name> - <description>no description available</description> + <description>RxAutoSync</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RxAutoSync_0</name> + <name>off</name> <description>Rx FIFO auto sync off</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RxAutoSync_1</name> + <name>on</name> <description>RxFIFO auto sync on</description> <value>0x1</value> </enumeratedValue> @@ -223279,28 +229519,28 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RxFIFOFull_Sel</name> - <description>no description available</description> + <description>RxFIFOFull_Sel</description> <bitOffset>19</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RxFIFOFull_Sel_0</name> + <name>full_int_1</name> <description>Full interrupt if at least 1 sample in Rx left and right FIFOs</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFOFull_Sel_1</name> + <name>full_int_4</name> <description>Full interrupt if at least 4 sample in Rx left and right FIFOs</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFOFull_Sel_2</name> + <name>full_int_8</name> <description>Full interrupt if at least 8 sample in Rx left and right FIFOs</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFOFull_Sel_3</name> + <name>full_int_16</name> <description>Full interrupt if at least 16 sample in Rx left and right FIFO</description> <value>0x3</value> </enumeratedValue> @@ -223308,18 +229548,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RxFIFO_Rst</name> - <description>no description available</description> + <description>RxFIFO_Rst</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RxFIFO_Rst_0</name> + <name>normal</name> <description>Normal operation</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFO_Rst_1</name> + <name>reset_one</name> <description>Reset register to 1 sample remaining</description> <value>0x1</value> </enumeratedValue> @@ -223327,18 +229567,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RxFIFO_Off_On</name> - <description>no description available</description> + <description>RxFIFO_Off_On</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RxFIFO_Off_On_0</name> + <name>on_0</name> <description>SPDIF Rx FIFO is on</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFO_Off_On_1</name> + <name>off_1</name> <description>SPDIF Rx FIFO is off. Does not accept data from interface</description> <value>0x1</value> </enumeratedValue> @@ -223346,18 +229586,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RxFIFO_Ctrl</name> - <description>no description available</description> + <description>RxFIFO_Ctrl</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>RxFIFO_Ctrl_0</name> + <name>normal</name> <description>Normal operation</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>RxFIFO_Ctrl_1</name> + <name>always_zero</name> <description>Always read zero from Rx data register</description> <value>0x1</value> </enumeratedValue> @@ -223376,18 +229616,18 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>USyncMode</name> - <description>no description available</description> + <description>USyncMode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>USyncMode_0</name> + <name>non_cddata</name> <description>Non-CD data</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>USyncMode_1</name> + <name>cduser_chsubcode</name> <description>CD user channel subcode</description> <value>0x1</value> </enumeratedValue> @@ -223406,43 +229646,43 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>GainSel</name> - <description>Gain selection:</description> + <description>GainSel</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>GainSel_0</name> + <name>gainsel_0b000</name> <description>24*(2**10)</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_1</name> + <name>gainsel_0b001</name> <description>16*(2**10)</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_2</name> + <name>gainsel_0b010</name> <description>12*(2**10)</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_3</name> + <name>gainsel_0b011</name> <description>8*(2**10)</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_4</name> + <name>gainsel_0b100</name> <description>6*(2**10)</description> <value>0x4</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_5</name> + <name>gainsel_0b101</name> <description>4*(2**10)</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>GainSel_6</name> + <name>gainsel_0b110</name> <description>3*(2**10)</description> <value>0x6</value> </enumeratedValue> @@ -223450,45 +229690,45 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>LOCK</name> - <description>LOCK bit to show that the internal DPLL is locked, read only</description> + <description>LOCK</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ClkSrc_Sel</name> - <description>Clock source selection, all other settings not shown are reserved:</description> + <description>ClkSrc_Sel</description> <bitOffset>7</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ClkSrc_Sel_0</name> + <name>clksrc_0b0000</name> <description>if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>ClkSrc_Sel_1</name> + <name>clksrc_0b0001</name> <description>if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>ClkSrc_Sel_3</name> + <name>clksrc_0b0011</name> <description>if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>ClkSrc_Sel_5</name> + <name>clksrc_0b0101</name> <description>REF_CLK_32K (XTALOSC)</description> <value>0x5</value> </enumeratedValue> <enumeratedValue> - <name>ClkSrc_Sel_6</name> + <name>clksrc_0b0110</name> <description>tx_clk (SPDIF0_CLK_ROOT)</description> <value>0x6</value> </enumeratedValue> <enumeratedValue> - <name>ClkSrc_Sel_8</name> + <name>clksrc_0b1000</name> <description>SPDIF_EXT_CLK</description> <value>0x8</value> </enumeratedValue> @@ -223507,126 +229747,126 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxFIFOFul</name> - <description>SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.</description> + <description>RxFIFOFul</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxEm</name> - <description>SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.</description> + <description>TxEm</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LockLoss</name> - <description>SPDIF receiver loss of lock</description> + <description>LockLoss</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RxFIFOResyn</name> - <description>Rx FIFO resync</description> + <description>RxFIFOResyn</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RxFIFOUnOv</name> - <description>Rx FIFO underrun/overrun</description> + <description>RxFIFOUnOv</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>UQErr</name> - <description>U/Q Channel framing error</description> + <description>UQErr</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>UQSync</name> - <description>U/Q Channel sync found</description> + <description>UQSync</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>QRxOv</name> - <description>Q Channel receive register overrun</description> + <description>QRxOv</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>QRxFul</name> - <description>Q Channel receive register full, can't be cleared with reg</description> + <description>QRxFul</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>URxOv</name> - <description>U Channel receive register overrun</description> + <description>URxOv</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>URxFul</name> - <description>U Channel receive register full, can't be cleared with reg</description> + <description>URxFul</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BitErr</name> - <description>SPDIF receiver found parity bit error</description> + <description>BitErr</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SymErr</name> - <description>SPDIF receiver found illegal symbol</description> + <description>SymErr</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ValNoGood</name> - <description>SPDIF validity flag no good</description> + <description>ValNoGood</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CNew</name> - <description>SPDIF receive change in value of control channel</description> + <description>CNew</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxResyn</name> - <description>SPDIF Tx FIFO resync</description> + <description>TxResyn</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxUnOv</name> - <description>SPDIF Tx FIFO under/overrun</description> + <description>TxUnOv</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>Lock</name> - <description>SPDIF receiver's DPLL is locked</description> + <description>Lock</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -223645,98 +229885,98 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>LockLoss</name> - <description>SPDIF receiver loss of lock</description> + <description>LockLoss</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>RxFIFOResyn</name> - <description>Rx FIFO resync</description> + <description>RxFIFOResyn</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>RxFIFOUnOv</name> - <description>Rx FIFO underrun/overrun</description> + <description>RxFIFOUnOv</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>UQErr</name> - <description>U/Q Channel framing error</description> + <description>UQErr</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>UQSync</name> - <description>U/Q Channel sync found</description> + <description>UQSync</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>QRxOv</name> - <description>Q Channel receive register overrun</description> + <description>QRxOv</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>URxOv</name> - <description>U Channel receive register overrun</description> + <description>URxOv</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>BitErr</name> - <description>SPDIF receiver found parity bit error</description> + <description>BitErr</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SymErr</name> - <description>SPDIF receiver found illegal symbol</description> + <description>SymErr</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>ValNoGood</name> - <description>SPDIF validity flag no good</description> + <description>ValNoGood</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNew</name> - <description>SPDIF receive change in value of control channel</description> + <description>CNew</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>TxResyn</name> - <description>SPDIF Tx FIFO resync</description> + <description>TxResyn</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>TxUnOv</name> - <description>SPDIF Tx FIFO under/overrun</description> + <description>TxUnOv</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>Lock</name> - <description>SPDIF receiver's DPLL is locked</description> + <description>Lock</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> @@ -223755,126 +229995,126 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxFIFOFul</name> - <description>SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.</description> + <description>RxFIFOFul</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TxEm</name> - <description>SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.</description> + <description>TxEm</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LockLoss</name> - <description>SPDIF receiver loss of lock</description> + <description>LockLoss</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RxFIFOResyn</name> - <description>Rx FIFO resync</description> + <description>RxFIFOResyn</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RxFIFOUnOv</name> - <description>Rx FIFO underrun/overrun</description> + <description>RxFIFOUnOv</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>UQErr</name> - <description>U/Q Channel framing error</description> + <description>UQErr</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>UQSync</name> - <description>U/Q Channel sync found</description> + <description>UQSync</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>QRxOv</name> - <description>Q Channel receive register overrun</description> + <description>QRxOv</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>QRxFul</name> - <description>Q Channel receive register full, can't be cleared with reg</description> + <description>QRxFul</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>URxOv</name> - <description>U Channel receive register overrun</description> + <description>URxOv</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>URxFul</name> - <description>U Channel receive register full, can't be cleared with reg</description> + <description>URxFul</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BitErr</name> - <description>SPDIF receiver found parity bit error</description> + <description>BitErr</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SymErr</name> - <description>SPDIF receiver found illegal symbol</description> + <description>SymErr</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ValNoGood</name> - <description>SPDIF validity flag no good</description> + <description>ValNoGood</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CNew</name> - <description>SPDIF receive change in value of control channel</description> + <description>CNew</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TxResyn</name> - <description>SPDIF Tx FIFO resync</description> + <description>TxResyn</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TxUnOv</name> - <description>SPDIF Tx FIFO under/overrun</description> + <description>TxUnOv</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>Lock</name> - <description>SPDIF receiver's DPLL is locked</description> + <description>Lock</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -223892,7 +230132,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxDataLeft</name> - <description>Processor receive SPDIF data left</description> + <description>RxDataLeft</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -223910,7 +230150,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxDataRight</name> - <description>Processor receive SPDIF data right</description> + <description>RxDataRight</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -223928,7 +230168,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxCChannel_h</name> - <description>SPDIF receive C channel register, contains first 24 bits of C channel without interpretation</description> + <description>RxCChannel_h</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -223946,7 +230186,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxCChannel_l</name> - <description>SPDIF receive C channel register, contains next 24 bits of C channel without interpretation</description> + <description>RxCChannel_l</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -223964,7 +230204,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxUChannel</name> - <description>SPDIF receive U channel register, contains next 3 U channel bytes</description> + <description>RxUChannel</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -223982,7 +230222,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>RxQChannel</name> - <description>SPDIF receive Q channel register, contains next 3 Q channel bytes</description> + <description>RxQChannel</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -224000,7 +230240,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>TxDataLeft</name> - <description>SPDIF transmit left channel data. It is write-only, and always returns zeros when read</description> + <description>TxDataLeft</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>write-only</access> @@ -224018,7 +230258,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>TxDataRight</name> - <description>SPDIF transmit right channel data. It is write-only, and always returns zeros when read</description> + <description>TxDataRight</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>write-only</access> @@ -224036,7 +230276,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>TxCChannelCons_h</name> - <description>SPDIF transmit Cons</description> + <description>TxCChannelCons_h</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-write</access> @@ -224054,7 +230294,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>TxCChannelCons_l</name> - <description>SPDIF transmit Cons</description> + <description>TxCChannelCons_l</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-write</access> @@ -224072,7 +230312,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>FreqMeas</name> - <description>Frequency measurement data</description> + <description>FreqMeas</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> <access>read-only</access> @@ -224090,23 +230330,23 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>TxClk_DF</name> - <description>Divider factor (1-128)</description> + <description>TxClk_DF</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxClk_DF_0</name> + <name>div1</name> <description>divider factor is 1</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxClk_DF_1</name> + <name>div2</name> <description>divider factor is 2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TxClk_DF_127</name> + <name>div128</name> <description>divider factor is 128</description> <value>0x7F</value> </enumeratedValue> @@ -224114,18 +230354,18 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>tx_all_clk_en</name> - <description>Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.</description> + <description>tx_all_clk_en</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>tx_all_clk_en_0</name> + <name>disable</name> <description>disable transfer clock.</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>tx_all_clk_en_1</name> + <name>enable</name> <description>enable transfer clock.</description> <value>0x1</value> </enumeratedValue> @@ -224133,67 +230373,52 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>TxClk_Source</name> - <description>no description available</description> + <description>TxClk_Source</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>TxClk_Source_0</name> - <description>XTALOSC input (XTALOSC clock)</description> + <name>txclk_src_0b000</name> + <description>REF_CLK_32K input (XTALOSC 32 kHz clock)</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>TxClk_Source_1</name> - <description>tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)</description> + <name>txclk_src_0b001</name> + <description>tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TxClk_Source_2</name> - <description>tx_clk1 (from SAI1)</description> - <value>0x2</value> - </enumeratedValue> - <enumeratedValue> - <name>TxClk_Source_3</name> - <description>tx_clk2 SPDIF_EXT_CLK, from pads</description> + <name>txclk_src_0b011</name> + <description>SPDIF_EXT_CLK, from pads</description> <value>0x3</value> </enumeratedValue> <enumeratedValue> - <name>TxClk_Source_4</name> - <description>tx_clk3 (from SAI2)</description> - <value>0x4</value> - </enumeratedValue> - <enumeratedValue> - <name>TxClk_Source_5</name> + <name>txclk_src_0b101</name> <description>ipg_clk input (frequency divided)</description> <value>0x5</value> </enumeratedValue> - <enumeratedValue> - <name>TxClk_Source_6</name> - <description>tx_clk4 (from SAI3)</description> - <value>0x6</value> - </enumeratedValue> </enumeratedValues> </field> <field> <name>SYSCLK_DF</name> - <description>system clock divider factor, 2~512.</description> + <description>SYSCLK_DF</description> <bitOffset>11</bitOffset> <bitWidth>9</bitWidth> <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>SYSCLK_DF_0</name> + <name>no_clk</name> <description>no clock signal</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>SYSCLK_DF_1</name> + <name>div2</name> <description>divider factor is 2</description> <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>SYSCLK_DF_511</name> + <name>div512</name> <description>divider factor is 512</description> <value>0x1FF</value> </enumeratedValue> @@ -227953,7 +234178,7 @@ SPDX-License-Identifier: BSD-3-Clause <enumeratedValues> <enumeratedValue> <name>DISABLED</name> - <description>LPSPI module is disabled in debug mode</description> + <description>LPSPI module is disabled when the CPU is halted. When LPSPI is disabled, the PCS will be negated once the transmit FIFO is empty regardless of the state of TCR register.</description> <value>0</value> </enumeratedValue> <enumeratedValue> @@ -229439,6 +235664,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>TRIG0_DONE0</name> @@ -244980,9 +251206,8 @@ SPDX-License-Identifier: BSD-3-Clause </peripheral> <peripheral> <name>AOI1</name> - <description>AND/OR/INVERT module</description> + <description>AOI</description> <groupName>AOI</groupName> - <prependToName>AOI1_</prependToName> <headerStructName>AOI</headerStructName> <baseAddress>0x403B4000</baseAddress> <addressBlock> @@ -244992,10 +251217,7 @@ SPDX-License-Identifier: BSD-3-Clause </addressBlock> <registers> <register> - <dim>4</dim> - <dimIncrement>0x4</dimIncrement> - <dimIndex>0,1,2,3</dimIndex> - <name>BFCRT01%s</name> + <name>BFCRT010</name> <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description> <addressOffset>0</addressOffset> <size>16</size> @@ -245238,10 +251460,7 @@ SPDX-License-Identifier: BSD-3-Clause </fields> </register> <register> - <dim>4</dim> - <dimIncrement>0x4</dimIncrement> - <dimIndex>0,1,2,3</dimIndex> - <name>BFCRT23%s</name> + <name>BFCRT230</name> <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description> <addressOffset>0x2</addressOffset> <size>16</size> @@ -245483,13 +251702,1470 @@ SPDX-License-Identifier: BSD-3-Clause </field> </fields> </register> + <register> + <name>BFCRT011</name> + <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description> + <addressOffset>0x4</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT1_DC</name> + <description>Product term 1, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_CC</name> + <description>Product term 1, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_BC</name> + <description>Product term 1, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_AC</name> + <description>Product term 1, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_DC</name> + <description>Product term 0, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_CC</name> + <description>Product term 0, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_BC</name> + <description>Product term 0, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_AC</name> + <description>Product term 0, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>BFCRT231</name> + <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description> + <addressOffset>0x6</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT3_DC</name> + <description>Product term 3, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_CC</name> + <description>Product term 3, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_BC</name> + <description>Product term 3, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_AC</name> + <description>Product term 3, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_DC</name> + <description>Product term 2, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_CC</name> + <description>Product term 2, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_BC</name> + <description>Product term 2, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_AC</name> + <description>Product term 2, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>BFCRT012</name> + <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description> + <addressOffset>0x8</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT1_DC</name> + <description>Product term 1, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_CC</name> + <description>Product term 1, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_BC</name> + <description>Product term 1, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_AC</name> + <description>Product term 1, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_DC</name> + <description>Product term 0, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_CC</name> + <description>Product term 0, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_BC</name> + <description>Product term 0, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_AC</name> + <description>Product term 0, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>BFCRT232</name> + <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description> + <addressOffset>0xA</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT3_DC</name> + <description>Product term 3, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_CC</name> + <description>Product term 3, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_BC</name> + <description>Product term 3, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_AC</name> + <description>Product term 3, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_DC</name> + <description>Product term 2, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_CC</name> + <description>Product term 2, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_BC</name> + <description>Product term 2, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_AC</name> + <description>Product term 2, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>BFCRT013</name> + <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description> + <addressOffset>0xC</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT1_DC</name> + <description>Product term 1, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_CC</name> + <description>Product term 1, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_BC</name> + <description>Product term 1, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT1_AC</name> + <description>Product term 1, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT1_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT1_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_DC</name> + <description>Product term 0, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_CC</name> + <description>Product term 0, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_BC</name> + <description>Product term 0, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT0_AC</name> + <description>Product term 0, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT0_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT0_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>BFCRT233</name> + <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description> + <addressOffset>0xE</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFF</resetMask> + <fields> + <field> + <name>PT3_DC</name> + <description>Product term 3, D input configuration</description> + <bitOffset>0</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_CC</name> + <description>Product term 3, C input configuration</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_BC</name> + <description>Product term 3, B input configuration</description> + <bitOffset>4</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT3_AC</name> + <description>Product term 3, A input configuration</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT3_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT3_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_DC</name> + <description>Product term 2, D input configuration</description> + <bitOffset>8</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_DC_0</name> + <description>Force the D input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_1</name> + <description>Pass the D input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_2</name> + <description>Complement the D input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_DC_3</name> + <description>Force the D input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_CC</name> + <description>Product term 2, C input configuration</description> + <bitOffset>10</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_CC_0</name> + <description>Force the C input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_1</name> + <description>Pass the C input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_2</name> + <description>Complement the C input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_CC_3</name> + <description>Force the C input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_BC</name> + <description>Product term 2, B input configuration</description> + <bitOffset>12</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_BC_0</name> + <description>Force the B input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_1</name> + <description>Pass the B input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_2</name> + <description>Complement the B input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_BC_3</name> + <description>Force the B input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PT2_AC</name> + <description>Product term 2, A input configuration</description> + <bitOffset>14</bitOffset> + <bitWidth>2</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>PT2_AC_0</name> + <description>Force the A input in this product term to a logical zero</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_1</name> + <description>Pass the A input in this product term</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_2</name> + <description>Complement the A input in this product term</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>PT2_AC_3</name> + <description>Force the A input in this product term to a logical one</description> + <value>0x3</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> </registers> </peripheral> <peripheral derivedFrom="AOI1"> <name>AOI2</name> - <description>AND/OR/INVERT module</description> + <description>AOI</description> <groupName>AOI</groupName> - <prependToName>AOI2_</prependToName> <baseAddress>0x403B8000</baseAddress> <addressBlock> <offset>0</offset> @@ -249066,7 +256742,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>WAITEN</name> - <description>WAIT Enable</description> + <description>Wait Enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> @@ -249688,12 +257364,12 @@ SPDX-License-Identifier: BSD-3-Clause <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_2</name> <description>Output is tristated.</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_3</name> <description>Output is tristated.</description> <value>0x3</value> </enumeratedValue> @@ -249717,12 +257393,12 @@ SPDX-License-Identifier: BSD-3-Clause <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_2</name> <description>Output is tristated.</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_3</name> <description>Output is tristated.</description> <value>0x3</value> </enumeratedValue> @@ -249746,12 +257422,12 @@ SPDX-License-Identifier: BSD-3-Clause <value>0x1</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_2</name> <description>Output is tristated.</description> <value>0x2</value> </enumeratedValue> <enumeratedValue> - <name>TRISTATED</name> + <name>TRISTATED_3</name> <description>Output is tristated.</description> <value>0x3</value> </enumeratedValue> @@ -253414,13 +261090,13 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <enumeratedValues> <enumeratedValue> - <name>ENABLED</name> - <description>Enabled</description> + <name>DISABLED</name> + <description>Disabled</description> <value>0</value> </enumeratedValue> <enumeratedValue> - <name>DISABLED</name> - <description>Disabled</description> + <name>ENABLED</name> + <description>Enabled</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -254118,7 +261794,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RXEMPTY</name> - <description>RX Empty</description> + <description>Receive Empty</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -255001,12 +262677,12 @@ SPDX-License-Identifier: BSD-3-Clause <enumeratedValues> <enumeratedValue> <name>RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG</name> - <description>Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]).</description> + <description>Reading the Receive Data register returns received data and clears the Receive Data flag.</description> <value>0</value> </enumeratedValue> <enumeratedValue> <name>WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG</name> - <description>Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).</description> + <description>Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is set, returns the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).</description> <value>0x1</value> </enumeratedValue> </enumeratedValues> @@ -255267,7 +262943,7 @@ SPDX-License-Identifier: BSD-3-Clause </field> <field> <name>RXEMPTY</name> - <description>RX Empty</description> + <description>Receive Empty</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -260164,7 +267840,7 @@ SPDX-License-Identifier: BSD-3-Clause <value>70</value> </interrupt> <interrupt> - <name>Reserved87</name> + <name>GPIO10_Combined_0_31</name> <value>71</value> </interrupt> <interrupt> @@ -260516,6 +268192,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETENA</name> @@ -260535,6 +268212,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETENA</name> @@ -260554,6 +268232,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETENA</name> @@ -260573,6 +268252,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETENA</name> @@ -260592,6 +268272,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETENA</name> @@ -260611,6 +268292,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRENA</name> @@ -260630,6 +268312,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRENA</name> @@ -260649,6 +268332,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRENA</name> @@ -260668,6 +268352,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRENA</name> @@ -260687,6 +268372,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRENA</name> @@ -260706,6 +268392,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETPEND</name> @@ -260725,6 +268412,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETPEND</name> @@ -260744,6 +268432,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETPEND</name> @@ -260763,6 +268452,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETPEND</name> @@ -260782,6 +268472,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>SETPEND</name> @@ -260801,6 +268492,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRPEND</name> @@ -260820,6 +268512,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRPEND</name> @@ -260839,6 +268532,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRPEND</name> @@ -260858,6 +268552,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRPEND</name> @@ -260877,6 +268572,7 @@ SPDX-License-Identifier: BSD-3-Clause <access>read-write</access> <resetValue>0</resetValue> <resetMask>0xFFFFFFFF</resetMask> + <modifiedWriteValues>oneToClear</modifiedWriteValues> <fields> <field> <name>CLRPEND</name> @@ -262267,7 +269963,7 @@ SPDX-License-Identifier: BSD-3-Clause <fields> <field> <name>PRI71</name> - <description>Priority of the INT_Reserved87 interrupt 71</description> + <description>Priority of the INT_GPIO10_Combined_0_31 interrupt 71</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> @@ -263843,6 +271539,901 @@ SPDX-License-Identifier: BSD-3-Clause </registers> </peripheral> <peripheral> + <name>MPU</name> + <description>Memory Protection Unit</description> + <groupName>MPU</groupName> + <baseAddress>0xE000ED90</baseAddress> + <addressBlock> + <offset>0</offset> + <size>0x2C</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>TYPE</name> + <description>The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.</description> + <addressOffset>0</addressOffset> + <size>32</size> + <access>read-only</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>SEPARATE</name> + <description>Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field> + <name>DREGION</name> + <description>Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-only</access> + </field> + <field> + <name>IREGION</name> + <description>Instruction region. RAZ. Armv7-M only supports a unified MPU.</description> + <bitOffset>16</bitOffset> + <bitWidth>8</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>CTRL</name> + <description>MPU Control Register.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0xFFFFFFFF</resetMask> + <fields> + <field> + <name>ENABLE</name> + <description>Enables the MPU.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>MPU_DISABLE</name> + <description>The MPU is disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>MPU_ENABLED</name> + <description>The MPU is enabled.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>HFNMIENA</name> + <description>Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLE</name> + <description>Disables the MPU for these handlers.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLE</name> + <description>Use the MPU for memory accesses by these handlers.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>PRIVDEFENA</name> + <description>no description available</description> + <bitOffset>2</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>ENABLE</name> + <description>Disables the default memory map. Any instruction or data access that does not access a defined region faults.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>DISABLE</name> + <description>Enables the default memory map as a background region for privileged access. The background region acts as region number -1. All memory regions configured in the MPU take priority over the default memory map.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>RNR</name> + <description>MPU Region Number Register.</description> + <addressOffset>0x8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>REGION</name> + <description>Indicates the memory region accessed by MPU_RBAR and MPU_RASR.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>RBAR</name> + <description>MPU Region Base Address Register.</description> + <addressOffset>0xC</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>REGION</name> + <description>On writes, can specify the number of the region to update. On reads, returns bits[3:0] of MPU_RNR.</description> + <bitOffset>0</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>VALID</name> + <description>On writes, indicates whether the region to update is specified by MPU_RNR.REGION, or by the REGION value specified in this write. When using the REGION value specified by this write, MPU_RNR.REGION is updated to this value.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>IGNORE_RBAR_REGION</name> + <description>Apply the base address update to the region specified by MPU_RNR.REGION. The REGION field value is ignored.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>USE_RBAR_REGION</name> + <description>Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ADDR</name> + <description>Base address of the region.</description> + <bitOffset>5</bitOffset> + <bitWidth>27</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>RASR</name> + <description>MPU Region Attribute and Size Register.</description> + <addressOffset>0x10</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>ENABLE</name> + <description>Enables this region.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>When the MPU is enabled, this region is disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>When the MPU is enabled, this region is enabled.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SIZE</name> + <description>Indicates the region size. The region size, in bytes, is 2**(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.</description> + <bitOffset>1</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRD</name> + <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. SRD[0-7]=0 - subregion enabled. SRD[0-7]=1 - subregion disabled.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>B</name> + <description>Memory type attribute B. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>C</name> + <description>Memory type attribute C. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>17</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>S</name> + <description>For Normal memory regions, the S bit indicates whether the region is shareable. For Strongly-ordered and Device memory, the S bit is ignored.</description> + <bitOffset>18</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NON_SHAREABLE</name> + <description>Non-shareable memory.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SHAREABLE</name> + <description>Shareable memory.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>TEX</name> + <description>Memory type attribute TEX. The TEX[2:0], C, and B bits together indicate the memory type of the region</description> + <bitOffset>19</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + <field> + <name>AP</name> + <description>The AP[2:0] bits indicate the access and privilege properties of the region.</description> + <bitOffset>24</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_ACCESS</name> + <description>Any access generates a permission fault.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_ACCESS</name> + <description>Privileged access only.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>UNPRIVILEGED_READ_ACCESS</name> + <description>Any unprivileged write generates a permission fault (Priviledge read/write, unprivileged read-only).</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>FULL_ACCESS</name> + <description>Full access</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_READ_ONLY</name> + <description>Privileged read-only access.</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY_2</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>XN</name> + <description>The XN bit is an Execute Never bit, that indicates whether the processor can execute instructions from the region.</description> + <bitOffset>28</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>EXECUTE</name> + <description>Execution of an instruction fetched from this region permitted.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EXECUTE_NEVER</name> + <description>Execution of an instruction fetched from this region not permitted.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>RBAR_A1</name> + <description>MPU Region Base Address Register.</description> + <addressOffset>0x14</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>REGION</name> + <description>On writes, can specify the number of the region to update. On reads, returns bits[3:0] of MPU_RNR.</description> + <bitOffset>0</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>VALID</name> + <description>On writes, indicates whether the region to update is specified by MPU_RNR.REGION, or by the REGION value specified in this write. When using the REGION value specified by this write, MPU_RNR.REGION is updated to this value.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>IGNORE_RBAR_REGION</name> + <description>Apply the base address update to the region specified by MPU_RNR.REGION. The REGION field value is ignored.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>USE_RBAR_REGION</name> + <description>Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ADDR</name> + <description>Base address of the region.</description> + <bitOffset>5</bitOffset> + <bitWidth>27</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>RASR_A1</name> + <description>MPU Region Attribute and Size Register.</description> + <addressOffset>0x18</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>ENABLE</name> + <description>Enables this region.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>When the MPU is enabled, this region is disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>When the MPU is enabled, this region is enabled.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SIZE</name> + <description>Indicates the region size. The region size, in bytes, is 2**(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.</description> + <bitOffset>1</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRD</name> + <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. SRD[0-7]=0 - subregion enabled. SRD[0-7]=1 - subregion disabled.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>B</name> + <description>Memory type attribute B. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>C</name> + <description>Memory type attribute C. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>17</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>S</name> + <description>For Normal memory regions, the S bit indicates whether the region is shareable. For Strongly-ordered and Device memory, the S bit is ignored.</description> + <bitOffset>18</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NON_SHAREABLE</name> + <description>Non-shareable memory.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SHAREABLE</name> + <description>Shareable memory.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>TEX</name> + <description>Memory type attribute TEX. The TEX[2:0], C, and B bits together indicate the memory type of the region</description> + <bitOffset>19</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + <field> + <name>AP</name> + <description>The AP[2:0] bits indicate the access and privilege properties of the region.</description> + <bitOffset>24</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_ACCESS</name> + <description>Any access generates a permission fault.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_ACCESS</name> + <description>Privileged access only.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>UNPRIVILEGED_READ_ACCESS</name> + <description>Any unprivileged write generates a permission fault (Priviledge read/write, unprivileged read-only).</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>FULL_ACCESS</name> + <description>Full access</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_READ_ONLY</name> + <description>Privileged read-only access.</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY_2</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>XN</name> + <description>The XN bit is an Execute Never bit, that indicates whether the processor can execute instructions from the region.</description> + <bitOffset>28</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>EXECUTE</name> + <description>Execution of an instruction fetched from this region permitted.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EXECUTE_NEVER</name> + <description>Execution of an instruction fetched from this region not permitted.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>RBAR_A2</name> + <description>MPU Region Base Address Register.</description> + <addressOffset>0x1C</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>REGION</name> + <description>On writes, can specify the number of the region to update. On reads, returns bits[3:0] of MPU_RNR.</description> + <bitOffset>0</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>VALID</name> + <description>On writes, indicates whether the region to update is specified by MPU_RNR.REGION, or by the REGION value specified in this write. When using the REGION value specified by this write, MPU_RNR.REGION is updated to this value.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>IGNORE_RBAR_REGION</name> + <description>Apply the base address update to the region specified by MPU_RNR.REGION. The REGION field value is ignored.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>USE_RBAR_REGION</name> + <description>Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ADDR</name> + <description>Base address of the region.</description> + <bitOffset>5</bitOffset> + <bitWidth>27</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>RASR_A2</name> + <description>MPU Region Attribute and Size Register.</description> + <addressOffset>0x20</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>ENABLE</name> + <description>Enables this region.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>When the MPU is enabled, this region is disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>When the MPU is enabled, this region is enabled.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SIZE</name> + <description>Indicates the region size. The region size, in bytes, is 2**(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.</description> + <bitOffset>1</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRD</name> + <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. SRD[0-7]=0 - subregion enabled. SRD[0-7]=1 - subregion disabled.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>B</name> + <description>Memory type attribute B. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>C</name> + <description>Memory type attribute C. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>17</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>S</name> + <description>For Normal memory regions, the S bit indicates whether the region is shareable. For Strongly-ordered and Device memory, the S bit is ignored.</description> + <bitOffset>18</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NON_SHAREABLE</name> + <description>Non-shareable memory.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SHAREABLE</name> + <description>Shareable memory.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>TEX</name> + <description>Memory type attribute TEX. The TEX[2:0], C, and B bits together indicate the memory type of the region</description> + <bitOffset>19</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + <field> + <name>AP</name> + <description>The AP[2:0] bits indicate the access and privilege properties of the region.</description> + <bitOffset>24</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_ACCESS</name> + <description>Any access generates a permission fault.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_ACCESS</name> + <description>Privileged access only.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>UNPRIVILEGED_READ_ACCESS</name> + <description>Any unprivileged write generates a permission fault (Priviledge read/write, unprivileged read-only).</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>FULL_ACCESS</name> + <description>Full access</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_READ_ONLY</name> + <description>Privileged read-only access.</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY_2</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>XN</name> + <description>The XN bit is an Execute Never bit, that indicates whether the processor can execute instructions from the region.</description> + <bitOffset>28</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>EXECUTE</name> + <description>Execution of an instruction fetched from this region permitted.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EXECUTE_NEVER</name> + <description>Execution of an instruction fetched from this region not permitted.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + <register> + <name>RBAR_A3</name> + <description>MPU Region Base Address Register.</description> + <addressOffset>0x24</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>REGION</name> + <description>On writes, can specify the number of the region to update. On reads, returns bits[3:0] of MPU_RNR.</description> + <bitOffset>0</bitOffset> + <bitWidth>4</bitWidth> + <access>read-write</access> + </field> + <field> + <name>VALID</name> + <description>On writes, indicates whether the region to update is specified by MPU_RNR.REGION, or by the REGION value specified in this write. When using the REGION value specified by this write, MPU_RNR.REGION is updated to this value.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>IGNORE_RBAR_REGION</name> + <description>Apply the base address update to the region specified by MPU_RNR.REGION. The REGION field value is ignored.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>USE_RBAR_REGION</name> + <description>Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>ADDR</name> + <description>Base address of the region.</description> + <bitOffset>5</bitOffset> + <bitWidth>27</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>RASR_A3</name> + <description>MPU Region Attribute and Size Register.</description> + <addressOffset>0x28</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0</resetValue> + <resetMask>0</resetMask> + <fields> + <field> + <name>ENABLE</name> + <description>Enables this region.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>DISABLED</name> + <description>When the MPU is enabled, this region is disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>ENABLED</name> + <description>When the MPU is enabled, this region is enabled.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>SIZE</name> + <description>Indicates the region size. The region size, in bytes, is 2**(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.</description> + <bitOffset>1</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + <field> + <name>SRD</name> + <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. SRD[0-7]=0 - subregion enabled. SRD[0-7]=1 - subregion disabled.</description> + <bitOffset>8</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field> + <name>B</name> + <description>Memory type attribute B. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>16</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>C</name> + <description>Memory type attribute C. The TEX[2:0], C, and B bits together indicate the memory type of the region.</description> + <bitOffset>17</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>S</name> + <description>For Normal memory regions, the S bit indicates whether the region is shareable. For Strongly-ordered and Device memory, the S bit is ignored.</description> + <bitOffset>18</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NON_SHAREABLE</name> + <description>Non-shareable memory.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>SHAREABLE</name> + <description>Shareable memory.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>TEX</name> + <description>Memory type attribute TEX. The TEX[2:0], C, and B bits together indicate the memory type of the region</description> + <bitOffset>19</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + </field> + <field> + <name>AP</name> + <description>The AP[2:0] bits indicate the access and privilege properties of the region.</description> + <bitOffset>24</bitOffset> + <bitWidth>3</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>NO_ACCESS</name> + <description>Any access generates a permission fault.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_ACCESS</name> + <description>Privileged access only.</description> + <value>0x1</value> + </enumeratedValue> + <enumeratedValue> + <name>UNPRIVILEGED_READ_ACCESS</name> + <description>Any unprivileged write generates a permission fault (Priviledge read/write, unprivileged read-only).</description> + <value>0x2</value> + </enumeratedValue> + <enumeratedValue> + <name>FULL_ACCESS</name> + <description>Full access</description> + <value>0x3</value> + </enumeratedValue> + <enumeratedValue> + <name>PRIVILEGED_READ_ONLY</name> + <description>Privileged read-only access.</description> + <value>0x5</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x6</value> + </enumeratedValue> + <enumeratedValue> + <name>READ_ONLY_2</name> + <description>Privileged and unprivileged read-only access.</description> + <value>0x7</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>XN</name> + <description>The XN bit is an Execute Never bit, that indicates whether the processor can execute instructions from the region.</description> + <bitOffset>28</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + <enumeratedValues> + <enumeratedValue> + <name>EXECUTE</name> + <description>Execution of an instruction fetched from this region permitted.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>EXECUTE_NEVER</name> + <description>Execution of an instruction fetched from this region not permitted.</description> + <value>0x1</value> + </enumeratedValue> + </enumeratedValues> + </field> + </fields> + </register> + </registers> + </peripheral> + <peripheral> <name>CM7_MCM</name> <description>CM7_MCM</description> <groupName>CM7_MCM</groupName> diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h index 8d76abf886..22f37ed04e 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### -** Version: rev. 1.0, 2018-11-16 -** Build: b211108 +** Version: rev. 2.0, 2022-03-25 +** Build: b220426 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -20,6 +20,8 @@ ** Initial version. ** - rev. 1.0 (2018-11-16) ** Update feature files to align with IMXRT1060RM Rev.0. +** - rev. 2.0 (2022-03-25) +** Add RT1060X device ** ** ################################################################### */ @@ -72,7 +74,7 @@ /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (3) /* @brief IGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_IGPIO_COUNT (9) +#define FSL_FEATURE_SOC_IGPIO_COUNT (10) /* @brief IOMUXC availability on the SoC. */ #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) /* @brief IOMUXC_GPR availability on the SoC. */ @@ -89,6 +91,8 @@ #define FSL_FEATURE_SOC_LPSPI_COUNT (4) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) /* @brief OCOTP availability on the SoC. */ #define FSL_FEATURE_SOC_OCOTP_COUNT (1) /* @brief PIT availability on the SoC. */ @@ -338,6 +342,8 @@ #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate.(RW610). */ +#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) /* EWM module features */ @@ -392,6 +398,12 @@ #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) /* GPC module features */ @@ -648,6 +660,8 @@ #define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1) /* @brief If SEMC has register DBICR2 (register DBICR2). */ #define FSL_FEATURE_SEMC_HAS_DBICR2 (0) +/* @brief SEMC supports hardware ECC on NAND flash interface. */ +#define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0) /* SNVS module features */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf index ea18bafcfd..f4cfe95c38 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf @@ -5,17 +5,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf index 4a1c691743..dc43dbc5bb 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf @@ -5,17 +5,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf index f5685c5630..31830845fd 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf @@ -5,17 +5,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf index ecb5cbc0f3..b4b8a208cc 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf @@ -5,17 +5,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf index 504675062a..8317c1eb19 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf @@ -5,17 +5,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S index 6bee28bf9f..44891fca0c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S @@ -2,13 +2,13 @@ /* @file: startup_MIMXRT1062.s */ /* @purpose: CMSIS Cortex-M7 Core Device Startup File */ /* MIMXRT1062 */ -/* @version: 1.2 */ -/* @date: 2019-4-29 */ -/* @build: b210419 */ +/* @version: 1.4 */ +/* @date: 2022-3-25 */ +/* @build: b220425 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ +/* Copyright 2016-2022 NXP */ /* All rights reserved. */ /* */ /* SPDX-License-Identifier: BSD-3-Clause */ @@ -112,7 +112,7 @@ __Vectors: .long ADC2_IRQHandler /* ADC2 interrupt*/ .long DCDC_IRQHandler /* DCDC interrupt*/ .long Reserved86_IRQHandler /* Reserved interrupt*/ - .long Reserved87_IRQHandler /* Reserved interrupt*/ + .long GPIO10_Combined_0_31_IRQHandler /* Combined interrupt indication for GPIO10 signal 0 throughout 31*/ .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ @@ -150,7 +150,7 @@ __Vectors: .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ .long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/ .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ - .long SEMC_IRQHandler /* Reserved interrupt*/ + .long SEMC_IRQHandler /* SEMC interrupt*/ .long USDHC1_IRQHandler /* USDHC1 interrupt*/ .long USDHC2_IRQHandler /* USDHC2 interrupt*/ .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ @@ -301,11 +301,11 @@ Reset_Handler: str r1, [r0] ldr r2, [r1] msr msp, r2 - ldr r0,=SystemInit - blx r0 + ldr r0,=SystemInit + blx r0 cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 + ldr r0,=__main + bx r0 .pool .size Reset_Handler, . - Reset_Handler @@ -916,7 +916,7 @@ FLEXIO3_IRQHandler: def_irq_handler ADC2_IRQHandler def_irq_handler DCDC_IRQHandler def_irq_handler Reserved86_IRQHandler - def_irq_handler Reserved87_IRQHandler + def_irq_handler GPIO10_Combined_0_31_IRQHandler def_irq_handler GPIO1_INT0_IRQHandler def_irq_handler GPIO1_INT1_IRQHandler def_irq_handler GPIO1_INT2_IRQHandler diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c index d922e343e7..d3af9fdfc6 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c @@ -21,13 +21,14 @@ typedef struct _mem_align_control_block #define FSL_COMPONENT_ID "platform.drivers.common" #endif +#if !((defined(__DSC__) && defined(__CW__))) void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; uint32_t alignedsize; /* Check overflow. */ - alignedsize = SDK_SIZEALIGN(size, alignbytes); + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); if (alignedsize < size) { return NULL; @@ -38,19 +39,15 @@ void *SDK_Malloc(size_t size, size_t alignbytes) return NULL; } - alignedsize += alignbytes + sizeof(mem_align_cb_t); + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); union { void *pointer_value; -#if (defined(__DSC__) && defined(__CW__)) - uint32_t unsigned_value; -#else uintptr_t unsigned_value; -#endif } p_align_addr, p_addr; - p_addr.pointer_value = malloc(alignedsize); + p_addr.pointer_value = malloc((size_t)alignedsize); if (p_addr.pointer_value == NULL) { @@ -71,11 +68,7 @@ void SDK_Free(void *ptr) union { void *pointer_value; -#if (defined(__DSC__) && defined(__CW__)) - uint32_t unsigned_value; -#else uintptr_t unsigned_value; -#endif } p_free; p_free.pointer_value = ptr; mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); @@ -89,3 +82,4 @@ void SDK_Free(void *ptr) free(p_free.pointer_value); } +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h index ed9a34d3ce..d9cb304f2f 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h @@ -59,7 +59,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*@}*/ /* Debug console type definition. */ @@ -190,6 +190,11 @@ enum _status_groups kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ }; /*! \public @@ -264,6 +269,7 @@ typedef int32_t status_t; extern "C" { #endif +#if !((defined(__DSC__) && defined(__CW__))) /*! * @brief Allocate memory with given alignment and aligned size. * @@ -281,6 +287,7 @@ void *SDK_Malloc(size_t size, size_t alignbytes); * @param ptr The memory to be release. */ void SDK_Free(void *ptr); +#endif /*! * @brief Delay at least for some time. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c index efcfb9a81b..269d62c7ff 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -314,19 +314,19 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm * * param base eDMA peripheral base address. * param channel eDMA channel number. - * param type A channel link type, which can be one of the following: + * param linkType A channel link type, which can be one of the following: * arg kEDMA_LinkNone * arg kEDMA_MinorLink * arg kEDMA_MajorLink * param linkedChannel The linked channel number. * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel) { assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel); + EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], linkType, linkedChannel); } /*! @@ -458,7 +458,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd) tcd->CITER = 0U; tcd->DLAST_SGA = 0U; /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); + tcd->CSR = DMA_CSR_DREQ(1U); tcd->BITER = 0U; } @@ -466,7 +466,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd) * brief Configures the eDMA TCD transfer attribute. * * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. + * The TCD is used in the scatter-gather mode. * This function configures the TCD transfer attribute, including source address, destination address, * transfer size, address offset, and so on. It also configures the scatter gather feature if the * user supplies the next TCD address. @@ -592,19 +592,19 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t * * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. * param tcd Point to the TCD structure. - * param type Channel link type, it can be one of: + * param linkType Channel link type, it can be one of: * arg kEDMA_LinkNone * arg kEDMA_MinorLink * arg kEDMA_MajorLink * param linkedChannel The linked channel number. */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel) { assert(tcd != NULL); assert(((uint32_t)tcd & 0x1FU) == 0U); assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - if (type == kEDMA_MinorLink) /* Minor link config */ + if (linkType == kEDMA_MinorLink) /* Minor link config */ { uint16_t tmpreg; @@ -619,7 +619,7 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); tcd->BITER = tmpreg; } - else if (type == kEDMA_MajorLink) /* Major link config */ + else if (linkType == kEDMA_MajorLink) /* Major link config */ { uint16_t tmpreg; @@ -1044,7 +1044,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, * param destWidth eDMA transfer destination address width(bytes). * param bytesEachRequest eDMA transfer bytes per channel request. * param transferBytes eDMA transfer bytes to be transferred. - * param type eDMA transfer type. + * param transferType eDMA transfer type. * note The data address and the data width must be consistent. For example, if the SRC * is 4 bytes, the source address must be 4 bytes aligned, or it results in * source address error (SAE). @@ -1056,13 +1056,13 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, - edma_transfer_type_t type) + edma_transfer_type_t transferType) { assert(config != NULL); int16_t srcOffset = 0, destOffset = 0; - switch (type) + switch (transferType) { case kEDMA_MemoryToMemory: destOffset = (int16_t)destWidth; @@ -1468,6 +1468,15 @@ void EDMA_HandleIRQ(edma_handle_t *handle) { tcds_done += handle->tcdSize; } + /* + * While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware + * so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD + * overwritten. + */ + if (transfer_done) + { + handle->base->CDNE = handle->channel; + } } /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ handle->header = (int8_t)new_header; diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h index 3ebb55d8e7..3d31f88365 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -438,14 +438,14 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm * * @param base eDMA peripheral base address. * @param channel eDMA channel number. - * @param type A channel link type, which can be one of the following: + * @param linkType A channel link type, which can be one of the following: * @arg kEDMA_LinkNone * @arg kEDMA_MinorLink * @arg kEDMA_MajorLink * @param linkedChannel The linked channel number. * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel); /*! * @brief Sets the bandwidth for the eDMA transfer. @@ -563,7 +563,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd); * @brief Configures the eDMA TCD transfer attribute. * * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. + * The TCD is used in the scatter-gather mode. * This function configures the TCD transfer attribute, including source address, destination address, * transfer size, address offset, and so on. It also configures the scatter gather feature if the * user supplies the next TCD address. @@ -608,13 +608,13 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi * * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. * @param tcd Point to the TCD structure. - * @param type Channel link type, it can be one of: + * @param linkType Channel link type, it can be one of: * @arg kEDMA_LinkNone * @arg kEDMA_MinorLink * @arg kEDMA_MajorLink * @param linkedChannel The linked channel number. */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel); /*! * @brief Sets the bandwidth for the eDMA TCD. @@ -890,7 +890,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, * @param destWidth eDMA transfer destination address width(bytes). * @param bytesEachRequest eDMA transfer bytes per channel request. * @param transferBytes eDMA transfer bytes to be transferred. - * @param type eDMA transfer type. + * @param transferType eDMA transfer type. * @note The data address and the data width must be consistent. For example, if the SRC * is 4 bytes, the source address must be 4 bytes aligned, or it results in * source address error (SAE). @@ -902,7 +902,7 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, - edma_transfer_type_t type); + edma_transfer_type_t transferType); /*! * @brief Submits the eDMA transfer request. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c index 59fbc6be49..cf26e857c1 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c @@ -44,6 +44,9 @@ enum /*! @brief Pointers to enet clocks for each instance. */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE +const clock_ip_name_t s_enetExtraClock[] = ENET_EXTRA_CLOCKS; +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /*! @brief Pointers to enet transmit IRQ number for each instance. */ @@ -329,6 +332,11 @@ status_t ENET_Init(ENET_Type *base, /* Ungate ENET clock. */ (void)CLOCK_EnableClock(s_enetClock[instance]); + +#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE + /* Ungate ENET extra clock. */ + (void)CLOCK_EnableClock(s_enetExtraClock[instance]); +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset ENET module. */ ENET_Reset(base); @@ -374,6 +382,11 @@ void ENET_Deinit(ENET_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disables the clock source. */ (void)CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); + +#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE + /* Disables ENET extra clock. */ + (void)CLOCK_DisableClock(s_enetExtraClock[ENET_GetInstance(base)]); +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -3906,14 +3919,14 @@ void ENET_1G_1588_Timer_DriverIRQHandler(void) #endif /* ENET_1G */ #if defined(ENET1) -void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void); -void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void) +void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void); +void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void) { ENET_CommonFrame1IRQHandler(ENET1); SDK_ISR_EXIT_BARRIER; } -void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void); -void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void) +void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void); +void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void) { ENET_CommonFrame2IRQHandler(ENET1); SDK_ISR_EXIT_BARRIER; diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h index 02570feaf2..740ac58a22 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 3)) +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 4)) /*@}*/ /*! @name ENET DESCRIPTOR QUEUE */ @@ -776,6 +776,9 @@ typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); /*! @brief Pointers to enet clocks for each instance. */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) extern const clock_ip_name_t s_enetClock[]; +#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE +extern const clock_ip_name_t s_enetExtraClock[]; +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c index b92658a38d..1f495af526 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -96,10 +96,10 @@ /* Define the range of memory that needs to be initialized when the device has memory error detection feature. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) -#define CAN_INIT_RXFIR ((uint32_t)base + 0x4Cu) -#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1) +#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu) +#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1) #define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 -#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2) +#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2) #define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 #endif @@ -366,6 +366,23 @@ static flexcan_isr_t s_flexcanIsr; #endif /******************************************************************************* + * Implementation of 32-bit memset + ******************************************************************************/ + +static void flexcan_memset(void *s, uint32_t c, size_t n) +{ + size_t m; + uint32_t *ptr = s; + + m = n / sizeof(*ptr); + + while ((m--) != (size_t)0) + { + *ptr++ = c; + } +} + +/******************************************************************************* * Code ******************************************************************************/ /*! @@ -733,8 +750,8 @@ static void FLEXCAN_Reset(CAN_Type *base) /* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly updated. */ *(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U; - (void)memset((void *)CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1); - (void)memset((void *)CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2); + flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1); + flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2); /* Disable unrestricted write access to FlexCAN memory. */ base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; @@ -742,7 +759,7 @@ static void FLEXCAN_Reset(CAN_Type *base) FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag); #else /* Only need clean all Message Buffer memory. */ - (void)memset((void *)&base->MB[0], 0, sizeof(base->MB)); + flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB)); #endif /* Clean all individual Rx Mask of Message Buffers. */ @@ -818,7 +835,7 @@ static void FLEXCAN_SetBitRate(CAN_Type *base, } /* Update actual timing characteristic. */ - FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); + FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) @@ -869,7 +886,7 @@ static void FLEXCAN_SetFDBitRate(CAN_Type *base, } /* Update actual timing characteristic. */ - FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); + FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig); } #endif @@ -2692,17 +2709,12 @@ void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_rep */ static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) { - uint32_t dbg_temp = 0U; - uint32_t u32TempCS = 0U; - uint32_t u32Timeout = DELAY_BUSIDLE; - uint32_t u32TempIMASK1 = base->IMASK1; -/*after backup all interruption, disable ALL interruption*/ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint32_t u32TempIMASK2 = base->IMASK2; - base->IMASK2 = 0; -#endif - base->IMASK1 = 0; - dbg_temp = (uint32_t)(base->DBG1); + uint32_t dbg_temp = 0U; + uint32_t u32TempCS = 0U; + uint32_t u32Timeout = DELAY_BUSIDLE; + /*disable ALL interrupts to prevent any context switching*/ + uint32_t irqMask = DisableGlobalIRQ(); + dbg_temp = (uint32_t)(base->DBG1); switch (dbg_temp & CAN_DBG1_CFSM_MASK) { case RXINTERMISSION: @@ -2743,10 +2755,7 @@ static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) *mbCSAddr = u32TempCS; } /*restore interruption*/ - base->IMASK1 = u32TempIMASK1; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - base->IMASK2 = u32TempIMASK2; -#endif + EnableGlobalIRQ(irqMask); } #endif @@ -2776,12 +2785,12 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t uint32_t cs_temp = 0; status_t status; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) - FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); -#endif /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); +#endif /* Inactive Tx Message Buffer. */ base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); @@ -2862,14 +2871,13 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) - FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); -#endif - can_cs = mbAddr[offset]; /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); +#endif /* Inactive Tx Message Buffer and Fill Message ID field. */ mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); mbAddr[offset + 1U] = pTxFrame->id; @@ -3226,7 +3234,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra status_t status; /* Write Tx Message Buffer to initiate a data sending. */ - if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)pTxFrame)) + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame)) { /* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) @@ -3311,7 +3319,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f status_t status; /* Write Tx Message Buffer to initiate a data sending. */ - if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pTxFrame)) + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame)) { /* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) @@ -3563,7 +3571,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl } if (kStatus_Success == - FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uint32_t)pMbXfer->frame)) + FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) { /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) @@ -3680,7 +3688,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han } if (kStatus_Success == - FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pMbXfer->framefd)) + FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) { /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h index 57e6f4c598..6c34277a0d 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexCAN driver version. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 2)) +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 6)) /*@}*/ #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) @@ -396,7 +396,7 @@ enum _flexcan_interrupt_enable kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */ kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */ kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */ - kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 22. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */ #endif @@ -1607,8 +1607,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) /* Solve interrupt enable bits in CTRL1 register. */ base->CTRL1 |= (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | - (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | - (uint32_t)kFLEXCAN_WakeUpInterruptEnable)); + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); } /*! @@ -1656,8 +1655,7 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) /* Solve interrupt enable bits in CTRL1 register. */ base->CTRL1 &= ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | - (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | - (uint32_t)kFLEXCAN_WakeUpInterruptEnable)); + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); } /*! @@ -1730,9 +1728,9 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); * @param base FlexCAN peripheral base address. * @return FlexCAN Rx FIFO Head address. */ -static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) { - return (uint32_t) & (base->MB[0].CS); + return (uintptr_t) & (base->MB[0].CS); } /* @} */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c index f484660e8c..e067c86eaa 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -34,9 +34,11 @@ enum _flexcan_edma_tansfer_state /******************************************************************************* * Variables ******************************************************************************/ +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; -/*<! Private handle only used for internally. */ -static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT]; +/* Private handle only used for internally. */ +static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[ARRAY_SIZE(s_flexcanBases)]; /******************************************************************************* * Prototypes @@ -77,9 +79,9 @@ static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U; framefd->idhit = framefd->dataWord[idHitIndex]; /* Clear the unused frame data. */ - for (uint32_t i = idHitIndex; i < 16U; i++) + for (uint32_t j = idHitIndex; j < 16U; j++) { - framefd->dataWord[i] = 0x0U; + framefd->dataWord[j] = 0x0U; } framefd++; } diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h index b7e86cb5dd..b5606c269a 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexCAN EDMA driver version. */ -#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 1)) +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 6)) /*@}*/ /* Forward declaration of the handle typedef. */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c index ef6053c725..06542d9120 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -67,30 +67,48 @@ static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) { - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; if (handle->txData != NULL) { /* Transmit data and update tx size/buff. */ if (handle->bytePerFrame == 1U) { - tmpData = *(handle->txData); + tmpData = (uint32_t) * (handle->txData); handle->txData++; } - else + else if (handle->bytePerFrame == 2U) { if (handle->direction == kFLEXIO_SPI_MsbFirst) { - tmpData = (uint16_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; } else { - tmpData = (uint16_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; } handle->txData += 2U; } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } } else { @@ -109,7 +127,7 @@ static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) { - uint16_t tmpData; + uint32_t tmpData; tmpData = FLEXIO_SPI_ReadData(base, handle->direction); @@ -118,11 +136,10 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_ if (handle->bytePerFrame == 1U) { *handle->rxData = (uint8_t)tmpData; - handle->rxData++; } - else + else if (handle->bytePerFrame == 2U) { - if (handle->direction == kFLEXIO_SPI_MsbFirst) + if (handle->direction == kFLEXIO_SPI_LsbFirst) { *handle->rxData = (uint8_t)(tmpData >> 8); handle->rxData++; @@ -134,8 +151,31 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_ handle->rxData++; *handle->rxData = (uint8_t)(tmpData >> 8); } - handle->rxData++; } + else + { + if (handle->direction == kFLEXIO_SPI_LsbFirst) + { + *handle->rxData = (uint8_t)(tmpData >> 24U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)tmpData; + } + else + { + *handle->rxData = (uint8_t)tmpData; + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 24U); + } + } + handle->rxData++; } handle->rxRemainingBytes -= handle->bytePerFrame; } @@ -270,10 +310,10 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - + /* Low 8-bits are used to configure baudrate. */ timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps); timerDiv = timerDiv / 2U - 1U; - + /* High 8-bits are used to configure shift clock edges(transfer width). */ timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U; timerCmp |= timerDiv; @@ -297,7 +337,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerCompare = 0xFFFFU; + timerConfig.timerCompare = 0xFFFFU; /* Never compare. */ FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); } @@ -473,8 +513,6 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { - /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous - PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; } @@ -768,16 +806,31 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra { flexio_spi_shift_direction_t direction; uint8_t bytesPerFrame; - uint32_t dataMode = 0; - uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]); - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]); + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); #if SPI_RETRY_TIMES uint32_t waitTimes; #endif timerCmp &= 0x00FFU; + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + /* Configure the values in handle. */ - switch (xfer->flags) + switch (dataFormat) { case (uint8_t)kFLEXIO_SPI_8bitMsb: dataMode = (8UL * 2UL - 1UL) << 8U; @@ -803,6 +856,18 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra direction = kFLEXIO_SPI_LsbFirst; break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: dataMode = (8UL * 2UL - 1UL) << 8U; bytesPerFrame = 1U; @@ -813,6 +878,12 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra dataMode |= timerCmp; + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + /* Configure transfer size. */ base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; @@ -839,23 +910,41 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra /* Transmit data and update tx size/buff. */ if (bytesPerFrame == 1U) { - tmpData = *(xfer->txData); + tmpData = (uint32_t) * (xfer->txData); xfer->txData++; } - else + else if (bytesPerFrame == 2U) { if (direction == kFLEXIO_SPI_MsbFirst) { - tmpData = (uint16_t)(xfer->txData[0]) << 8U; - tmpData += xfer->txData[1]; + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += (uint32_t)xfer->txData[1]; } else { - tmpData = (uint16_t)(xfer->txData[1]) << 8U; - tmpData += xfer->txData[0]; + tmpData = (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; } xfer->txData += 2U; } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 24U; + tmpData += (uint32_t)(xfer->txData[1]) << 16U; + tmpData += (uint32_t)(xfer->txData[2]) << 8U; + tmpData += (uint32_t)xfer->txData[3]; + } + else + { + tmpData = (uint32_t)(xfer->txData[3]) << 24U; + tmpData += (uint32_t)(xfer->txData[2]) << 16U; + tmpData += (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; + } + xfer->txData += 4U; + } } else { @@ -888,11 +977,10 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra if (bytesPerFrame == 1U) { *xfer->rxData = (uint8_t)tmpData; - xfer->rxData++; } - else + else if (bytesPerFrame == 2U) { - if (direction == kFLEXIO_SPI_MsbFirst) + if (direction == kFLEXIO_SPI_LsbFirst) { *xfer->rxData = (uint8_t)(tmpData >> 8); xfer->rxData++; @@ -904,8 +992,31 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra xfer->rxData++; *xfer->rxData = (uint8_t)(tmpData >> 8); } - xfer->rxData++; } + else + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + *xfer->rxData = (uint8_t)(tmpData >> 24U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)tmpData; + } + else + { + *xfer->rxData = (uint8_t)tmpData; + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 24U); + } + } + xfer->rxData++; } } @@ -967,9 +1078,10 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, assert(handle != NULL); assert(xfer != NULL); - uint32_t dataMode = 0; - uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); timerCmp &= 0x00FFU; @@ -985,8 +1097,27 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, return kStatus_InvalidArgument; } + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + /* Configure the values in handle */ - switch (xfer->flags) + switch (dataFormat) { case (uint8_t)kFLEXIO_SPI_8bitMsb: dataMode = (8UL * 2UL - 1UL) << 8U; @@ -1008,6 +1139,16 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, handle->bytePerFrame = 2U; handle->direction = kFLEXIO_SPI_LsbFirst; break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; default: dataMode = (8UL * 2UL - 1UL) << 8U; handle->bytePerFrame = 1U; @@ -1018,6 +1159,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, dataMode |= timerCmp; + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + /* Configure transfer size. */ base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; @@ -1035,23 +1182,41 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, /* Transmit data and update tx size/buff. */ if (handle->bytePerFrame == 1U) { - tmpData = *(handle->txData); + tmpData = (uint32_t) * (handle->txData); handle->txData++; } - else + else if (handle->bytePerFrame == 2U) { if (handle->direction == kFLEXIO_SPI_MsbFirst) { - tmpData = (uint16_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; } else { - tmpData = (uint16_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; } handle->txData += 2U; } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } } else { @@ -1220,7 +1385,8 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, assert(handle != NULL); assert(xfer != NULL); - uint32_t dataMode = 0; + uint32_t dataMode = 0; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); /* Check if SPI is busy. */ if (handle->state == (uint32_t)kFLEXIO_SPI_Busy) @@ -1234,8 +1400,35 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, return kStatus_InvalidArgument; } + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + /* Configure the values in handle */ - switch (xfer->flags) + switch (dataFormat) { case (uint8_t)kFLEXIO_SPI_8bitMsb: dataMode = 8U * 2U - 1U; @@ -1257,14 +1450,30 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, handle->bytePerFrame = 2U; handle->direction = kFLEXIO_SPI_LsbFirst; break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; default: - dataMode = 8U * 2U - 1U; + dataMode = 8UL * 2UL - 1UL; handle->bytePerFrame = 1U; handle->direction = kFLEXIO_SPI_MsbFirst; assert(true); break; } + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + /* Configure transfer size. */ base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; @@ -1328,3 +1537,17 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) } } } + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h index 38af76b583..61c1034fc2 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,13 +23,13 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO SPI driver version 2.2.1. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*! @brief FlexIO SPI driver version. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ #ifndef FLEXIO_SPI_DUMMYDATA /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ -#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) +#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU) #endif /*! @brief Retry times for waiting flag. */ @@ -37,6 +37,9 @@ #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +/*! @brief Get the transfer data format of width and bit order. */ +#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U)) + /*! @brief Error codes for the FlexIO SPI driver. */ enum { @@ -68,6 +71,7 @@ typedef enum _flexio_spi_data_bitcount_mode { kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ + kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */ } flexio_spi_data_bitcount_mode_t; /*! @brief Define FlexIO SPI interrupt mask. */ @@ -92,20 +96,25 @@ enum _flexio_spi_dma_enable kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ }; -/*! @brief Define FlexIO SPI transfer flags. */ +/*! @brief Define FlexIO SPI transfer flags. + * @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */ enum _flexio_spi_transfer_flags { - kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ - kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ - kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ - kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ + kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */ + kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */ + kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */ + kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */ }; /*! @brief Define FlexIO SPI access structure typedef. */ typedef struct _flexio_spi_type { FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t SDOPinIndex; /*!< Pin select for data output. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as + GPIO input and disable all pull up/down in application. */ uint8_t SDIPinIndex; /*!< Pin select for data input. */ uint8_t SCKPinIndex; /*!< Pin select for clock. */ uint8_t CSnPinIndex; /*!< Pin select for enable. */ @@ -477,9 +486,9 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, * * @param base Pointer to the FLEXIO_SPI_Type structure. * @param direction Shift direction of MSB first or LSB first. - * @param data 8 bit/16 bit data. + * @param data 8/16/32 bit data. */ -static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data) { if (direction == kFLEXIO_SPI_MsbFirst) { @@ -501,15 +510,15 @@ static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_ * @param direction Shift direction of MSB first or LSB first. * @return 8 bit/16 bit data received. */ -static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) { if (direction == kFLEXIO_SPI_MsbFirst) { - return (uint16_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); + return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); } else { - return (uint16_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); } } @@ -560,6 +569,14 @@ status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, */ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base); +/*@}*/ + /*Transactional APIs*/ /*! diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c index 934eb045ed..c1feba0f00 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -50,17 +50,19 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t * @param base pointer to FLEXIO_SPI_Type structure. * @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. * @param xfer Pointer to flexio spi transfer structure. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_InvalidArgument The transfer size is not supported. */ -static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer); +static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); /******************************************************************************* * Variables ******************************************************************************/ /* Dummy data used to send */ -static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA; +static const uint32_t s_dummyData = FLEXIO_SPI_DUMMYDATA; /*< @brief user configurable flexio spi handle count. */ #define FLEXIO_SPI_HANDLE_COUNT 2 @@ -122,16 +124,17 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t } } -static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) +static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) { edma_transfer_config_t xferConfig = {0}; flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; uint8_t bytesPerFrame; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); /* Configure the values in handle. */ - switch (xfer->flags) + switch (dataFormat) { case (uint8_t)kFLEXIO_SPI_8bitMsb: bytesPerFrame = 1U; @@ -149,6 +152,14 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, bytesPerFrame = 2U; direction = kFLEXIO_SPI_LsbFirst; break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; default: bytesPerFrame = 1U; direction = kFLEXIO_SPI_MsbFirst; @@ -156,6 +167,12 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, break; } + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + /* Save total transfer size. */ handle->transferSize = xfer->dataSize; @@ -168,7 +185,7 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; xferConfig.minorLoopBytes = 1U; } - else + else if (bytesPerFrame == 2U) { if (direction == kFLEXIO_SPI_MsbFirst) { @@ -178,6 +195,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; xferConfig.minorLoopBytes = 2U; } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 3U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.minorLoopBytes = 4U; + } /* Configure DMA channel. */ if (xfer->txData != NULL) @@ -213,6 +240,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, xferConfig.srcAddr -= 1U; } } + else if (bytesPerFrame == 4U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 3U; + } + } + else + { + } xferConfig.srcOffset = 0; xferConfig.destAddr = (uint32_t)(xfer->rxData); xferConfig.destOffset = (int16_t)bytesPerFrame; @@ -229,6 +266,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true); EDMA_StartTransfer(handle->txHandle); } + + return kStatus_Success; } /*! @@ -321,8 +360,9 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, assert(handle != NULL); assert(xfer != NULL); - uint32_t dataMode = 0; - uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); timerCmp &= 0x00FFU; @@ -338,27 +378,48 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, return kStatus_InvalidArgument; } + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + /* configure data mode. */ - if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb)) + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) { dataMode = (8UL * 2UL - 1UL) << 8U; } - else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb)) + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) { dataMode = (16UL * 2UL - 1UL) << 8U; } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = (32UL * 2UL - 1UL) << 8U; + } else { - dataMode = 8UL * 2UL - 1UL; + dataMode = (8UL * 2UL - 1UL) << 8U; } dataMode |= timerCmp; base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); } /*! @@ -438,7 +499,8 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, assert(handle != NULL); assert(xfer != NULL); - uint32_t dataMode = 0U; + uint32_t dataMode = 0U; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); /* Check if the device is busy. */ if ((handle->txInProgress) || (handle->rxInProgress)) @@ -446,6 +508,33 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, return kStatus_FLEXIO_SPI_Busy; } + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + /* Check if input parameter invalid. */ if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) { @@ -453,14 +542,18 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, } /* configure data mode. */ - if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb)) + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) { dataMode = 8U * 2U - 1U; } - else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb)) + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) { dataMode = 16U * 2U - 1U; } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = 32UL * 2UL - 1UL; + } else { dataMode = 8U * 2U - 1U; @@ -468,7 +561,5 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); } diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h index 699bcd6ee7..c71a1b1fda 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FlexIO SPI EDMA driver version. */ -#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ /*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c index 7f2db85d74..65e7318301 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2021 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * @@ -128,6 +128,55 @@ void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnabl } } +void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error) +{ + assert(error != NULL); + + switch (memory) + { + case kFLEXRAM_OCRAM: + base->OCRAM_ECC_ERROR_INJEC = + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_ITCM: + base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_D0TCM: + base->D0TCM_ECC_ERROR_INJEC = + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_D1TCM: + base->D1TCM_ECC_ERROR_INJEC = + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion); + break; + default: + assert(NULL); + break; + } + + __DSB(); +} + void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info) { assert(NULL != info); diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h index 73f4ecc438..3c9a9c2db3 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2021 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * @@ -23,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.1.0. */ -#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U)) +/*! @brief Driver version. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U)) /*@}*/ /*! @brief Get ECC error detailed information. */ @@ -108,6 +108,29 @@ enum }; #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC) +/*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */ +typedef enum _flexram_memory_type +{ + kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */ + kFLEXRAM_ITCM = 1U, /*!< Memory type ITCM */ + kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */ + kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */ +} flexram_memory_type_t; + +/*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */ +typedef struct _flexram_ecc_error_type +{ + uint8_t SingleBitPos; /*!< Bit position of the bit to inject ECC Error. */ + uint8_t SecondBitPos; /*!< Bit position of the second bit to inject multi-bit ECC Error */ + bool Fource1BitDataInversion; /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */ + bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write + access */ + bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory + write access */ + bool FourceContiNCDataInversion; /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on + memory write access */ +} flexram_ecc_error_type_t; + /*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */ typedef struct _flexram_ocram_ecc_single_error_info { @@ -423,6 +446,14 @@ static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAd void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable); /*! + * @brief FLEXRAM ECC error injection. + * @param base FLEXRAM base address. + * @param memory memory type, such as OCRAM/ITCM/DTCM. + * @param error ECC error type. + */ +void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error); + +/*! * @brief FLEXRAM get ocram ecc single error information. * @param base FLEXRAM base address. * @param info ecc error information. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c index ef72d3709c..7964163917 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c @@ -33,10 +33,14 @@ enum FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */ kFLEXSPI_FlashASampleClockRefDelayLocked = FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */ +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) kFLEXSPI_FlashBSampleClockSlaveDelayLocked = FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */ +#endif +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) kFLEXSPI_FlashBSampleClockRefDelayLocked = FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */ +#endif }; /*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */ @@ -293,10 +297,15 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) /* Configure MCR2 configurations. */ configValue = base->MCR2; - configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK | - FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); + configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + FLEXSPI_MCR2_SCKBDIFFOPT_MASK | +#endif + FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | +#endif FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); @@ -354,9 +363,11 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) config->enableCombination = false; #endif - config->enableDoze = true; - config->enableHalfSpeedAccess = false; - config->enableSckBDiffOpt = false; + config->enableDoze = true; + config->enableHalfSpeedAccess = false; +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + config->enableSckBDiffOpt = false; +#endif config->enableSameConfigForAll = false; config->seqTimeoutCycle = 0xFFFFU; config->ipGrantTimeoutCycle = 0xFFU; @@ -432,12 +443,18 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ - statusValue = - (index == 0U) ? - ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | - (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) : + if (index == 0U) + { + statusValue = + ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked); + } +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) + else + { + statusValue = ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked); - + } +#endif if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK)) { /* Wait slave delay line locked and slave reference delay line locked. */ @@ -527,11 +544,13 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); } +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) else { base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); } +#endif /* Exit stop mode. */ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; @@ -564,8 +583,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, } /* Unlock LUT for update. */ +#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x02; +#endif + base->LUTCR = 0x02; lutBase = &base->LUT[index]; for (i = 0; i < count; i++) @@ -574,8 +595,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, } /* Lock LUT. */ +#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x01; +#endif + base->LUTCR = 0x01; } /*! brief Update read sample clock source diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h index e009fec11c..5269d439da 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h @@ -25,7 +25,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief FLEXSPI driver version 2.3.5. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5)) +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) /*@}*/ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -190,8 +190,10 @@ typedef enum _flexspi_port { kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ - kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ - kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ +#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) + kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ + kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ +#endif kFLEXSPI_PortCount } flexspi_port_t; @@ -231,11 +233,13 @@ typedef struct _flexspi_config bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ #endif - bool enableDoze; /*!< Enable/disable doze mode support. */ - bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half - speed commands. */ - bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock - output, when enable, Port B flash access is not available. */ + bool enableDoze; /*!< Enable/disable doze mode support. */ + bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half + speed commands. */ +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock + output, when enable, Port B flash access is not available. */ +#endif bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all. */ uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, @@ -615,10 +619,12 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT); } +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) if (portBPhase != NULL) { *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT); } +#endif } #endif @@ -683,6 +689,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) */ void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource); +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) /*! @brief Enables/disables the FLEXSPI IP command parallel mode. * * @param base FLEXSPI peripheral base address. @@ -699,7 +706,9 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; } } +#endif +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) /*! @brief Enables/disables the FLEXSPI AHB command parallel mode. * * @param base FLEXSPI peripheral base address. @@ -716,6 +725,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; } } +#endif /*! @brief Updates the LUT table. * diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c index 341757d91b..68ccade87d 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020 NXP + * Copyright 2016-2017, 2020-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,8 +17,10 @@ * Variables ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Array of GPIO peripheral base address. */ static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Array of GPIO clock name. */ @@ -29,6 +31,7 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; * Prototypes ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /*! * @brief Gets the GPIO instance according to the GPIO base * @@ -58,6 +61,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base) return instance; } +#endif /*! * brief Initializes the GPIO peripheral according to the specified diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h index bfbda25220..bd0e7f20bb 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) /*@}*/ /*! @brief GPIO direction definition. */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h index 0cf070a6c8..ec274588bf 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ /*! diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h index 4bb523fe50..a6ea1f69fb 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h @@ -1,6 +1,6 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1144,6 +1144,69 @@ #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SPI_B0_00_GPIO10_IO00 0x401F865CU, 0x5U, 0, 0, 0x401F86B4U + +#define IOMUXC_GPIO_SPI_B0_01_FLEXSPI2_B_SCLK 0x401F8660U, 0x0U, 0x401F8754U, 0x1U, 0x401F86B8U +#define IOMUXC_GPIO_SPI_B0_01_GPIO10_IO01 0x401F8660U, 0x5U, 0, 0, 0x401F86B8U + +#define IOMUXC_GPIO_SPI_B0_02_FLEXSPI2_A_DATA00 0x401F8664U, 0x0U, 0x401F8730U, 0x2U, 0x401F86BCU +#define IOMUXC_GPIO_SPI_B0_02_GPIO10_IO02 0x401F8664U, 0x5U, 0, 0, 0x401F86BCU + +#define IOMUXC_GPIO_SPI_B0_03_FLEXSPI2_B_DATA02 0x401F8668U, 0x0U, 0x401F8748U, 0x1U, 0x401F86C0U +#define IOMUXC_GPIO_SPI_B0_03_GPIO10_IO03 0x401F8668U, 0x5U, 0, 0, 0x401F86C0U + +#define IOMUXC_GPIO_SPI_B0_04_FLEXSPI2_B_DATA03 0x401F866CU, 0x0U, 0x401F874CU, 0x1U, 0x401F86C4U +#define IOMUXC_GPIO_SPI_B0_04_GPIO10_IO04 0x401F866CU, 0x5U, 0, 0, 0x401F86C4U + +#define IOMUXC_GPIO_SPI_B0_05_FLEXSPI2_A_SS0_B 0x401F8670U, 0x0U, 0, 0, 0x401F86C8U +#define IOMUXC_GPIO_SPI_B0_05_GPIO10_IO05 0x401F8670U, 0x5U, 0, 0, 0x401F86C8U + +#define IOMUXC_GPIO_SPI_B0_06_FLEXSPI2_A_DATA02 0x401F8674U, 0x0U, 0x401F8738U, 0x2U, 0x401F86CCU +#define IOMUXC_GPIO_SPI_B0_06_GPIO10_IO06 0x401F8674U, 0x5U, 0, 0, 0x401F86CCU + +#define IOMUXC_GPIO_SPI_B0_07_FLEXSPI2_B_DATA01 0x401F8678U, 0x0U, 0x401F8744U, 0x1U, 0x401F86D0U +#define IOMUXC_GPIO_SPI_B0_07_GPIO10_IO07 0x401F8678U, 0x5U, 0, 0, 0x401F86D0U + +#define IOMUXC_GPIO_SPI_B0_08_FLEXSPI2_A_SCLK 0x401F867CU, 0x0U, 0x401F8750U, 0x2U, 0x401F86D4U +#define IOMUXC_GPIO_SPI_B0_08_GPIO10_IO08 0x401F867CU, 0x5U, 0, 0, 0x401F86D4U + +#define IOMUXC_GPIO_SPI_B0_09_FLEXSPI2_A_DQS 0x401F8680U, 0x0U, 0x401F872CU, 0x2U, 0x401F86D8U +#define IOMUXC_GPIO_SPI_B0_09_GPIO10_IO09 0x401F8680U, 0x5U, 0, 0, 0x401F86D8U + +#define IOMUXC_GPIO_SPI_B0_10_FLEXSPI2_A_DATA03 0x401F8684U, 0x0U, 0x401F873CU, 0x2U, 0x401F86DCU +#define IOMUXC_GPIO_SPI_B0_10_GPIO10_IO10 0x401F8684U, 0x5U, 0, 0, 0x401F86DCU + +#define IOMUXC_GPIO_SPI_B0_11_FLEXSPI2_B_DATA00 0x401F8688U, 0x0U, 0x401F8740U, 0x1U, 0x401F86E0U +#define IOMUXC_GPIO_SPI_B0_11_GPIO10_IO11 0x401F8688U, 0x5U, 0, 0, 0x401F86E0U + +#define IOMUXC_GPIO_SPI_B0_12_FLEXSPI2_A_DATA01 0x401F868CU, 0x0U, 0x401F8734U, 0x2U, 0x401F86E4U +#define IOMUXC_GPIO_SPI_B0_12_GPIO10_IO12 0x401F868CU, 0x5U, 0, 0, 0x401F86E4U + +#define IOMUXC_GPIO_SPI_B0_13_GPIO10_IO13 0x401F8690U, 0x5U, 0, 0, 0x401F86E8U + +#define IOMUXC_GPIO_SPI_B1_00_FLEXSPI2_A_DQS 0x401F8694U, 0x0U, 0x401F872CU, 0x0U, 0x401F86ECU +#define IOMUXC_GPIO_SPI_B1_00_GPIO10_IO14 0x401F8694U, 0x5U, 0, 0, 0x401F86ECU + +#define IOMUXC_GPIO_SPI_B1_01_FLEXSPI2_A_DATA03 0x401F8698U, 0x0U, 0x401F873CU, 0x0U, 0x401F86F0U +#define IOMUXC_GPIO_SPI_B1_01_GPIO10_IO15 0x401F8698U, 0x5U, 0, 0, 0x401F86F0U + +#define IOMUXC_GPIO_SPI_B1_02_FLEXSPI2_A_DATA02 0x401F869CU, 0x0U, 0x401F8738U, 0x0U, 0x401F86F4U +#define IOMUXC_GPIO_SPI_B1_02_GPIO10_IO16 0x401F869CU, 0x5U, 0, 0, 0x401F86F4U + +#define IOMUXC_GPIO_SPI_B1_03_FLEXSPI2_A_DATA01 0x401F86A0U, 0x0U, 0x401F8734U, 0x0U, 0x401F86F8U +#define IOMUXC_GPIO_SPI_B1_03_GPIO10_IO17 0x401F86A0U, 0x5U, 0, 0, 0x401F86F8U + +#define IOMUXC_GPIO_SPI_B1_04_FLEXSPI2_A_DATA00 0x401F86A4U, 0x0U, 0x401F8730U, 0x0U, 0x401F86FCU +#define IOMUXC_GPIO_SPI_B1_04_GPIO10_IO18 0x401F86A4U, 0x5U, 0, 0, 0x401F86FCU + +#define IOMUXC_GPIO_SPI_B1_05_FLEXSPI2_A_SCLK 0x401F86A8U, 0x0U, 0x401F8750U, 0x0U, 0x401F8700U +#define IOMUXC_GPIO_SPI_B1_05_GPIO10_IO19 0x401F86A8U, 0x5U, 0, 0, 0x401F8700U + +#define IOMUXC_GPIO_SPI_B1_06_FLEXSPI2_A_SS0_B 0x401F86ACU, 0x0U, 0, 0, 0x401F8704U +#define IOMUXC_GPIO_SPI_B1_06_GPIO10_IO20 0x401F86ACU, 0x5U, 0, 0, 0x401F8704U + +#define IOMUXC_GPIO_SPI_B1_07_GPIO10_IO21 0x401F86B0U, 0x5U, 0, 0, 0x401F8708U + #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U #define IOMUXC_SNVS_WAKEUP_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.c new file mode 100644 index 0000000000..efb2d40333 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_freertos" +#endif + +static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData) +{ + lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPI2C. + * + * This function initializes the LPI2C module and related RTOS context. + * + * param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPI2C instance to initialize. + * param masterConfig Configuration structure to set-up LPI2C in master mode. + * param srcClock_Hz Frequency of input clock of the LPI2C module. + * return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpi2c_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->semaphore = xSemaphoreCreateBinary(); + if (handle->semaphore == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + LPI2C_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPI2C_MasterTransferCreateHandle(base, &handle->drv_handle, LPI2C_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and related RTOS context. + * + * param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle) +{ + LPI2C_MasterDeinit(handle->base); + + vSemaphoreDelete(handle->semaphore); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs I2C transfer. + * + * This function performs an I2C transfer using LPI2C module according to data given in the transfer structure. + * + * param handle The RTOS LPI2C handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPI2C_Busy; + } + + status = LPI2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.h new file mode 100644 index 0000000000..90bc78e934 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_LPI2C_FREERTOS_H__ +#define __FSL_LPI2C_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_lpi2c.h" + +/*! + * @addtogroup lpi2c_freertos_driver LPI2C FreeRTOS Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C FreeRTOS driver version. */ +#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! + * @cond RTOS_PRIVATE + * @brief LPI2C FreeRTOS handle + */ +typedef struct _lpi2c_rtos_handle +{ + LPI2C_Type *base; /*!< LPI2C base address */ + lpi2c_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t semaphore; /*!< Semaphore to notify and unblock task when transfer ends */ +} lpi2c_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPI2C RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPI2C. + * + * This function initializes the LPI2C module and related RTOS context. + * + * @param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPI2C instance to initialize. + * @param masterConfig Configuration structure to set-up LPI2C in master mode. + * @param srcClock_Hz Frequency of input clock of the LPI2C module. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and related RTOS context. + * + * @param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle); + +/*! + * @brief Performs I2C transfer. + * + * This function performs an I2C transfer using LPI2C module according to data given in the transfer structure. + * + * @param handle The RTOS LPI2C handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_LPI2C_FREERTOS_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h index 85da8edc21..adfc4e51e2 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -163,11 +163,11 @@ extern "C" { * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a * specified LPSPI instance, call this API once to get the initialized handle. * - * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA * request source. * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and - * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. - * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle. * * @param base LPSPI peripheral base address. * @param handle LPSPI handle pointer to lpspi_master_edma_handle_t. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.c new file mode 100644 index 0000000000..58305df266 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_freertos" +#endif + +static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData) +{ + lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPSPI instance to initialize. + * param masterConfig Configuration structure to set-up LPSPI in master mode. + * param srcClock_Hz Frequency of input clock of the LPSPI module. + * return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpspi_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->event = xSemaphoreCreateBinary(); + if (handle->event == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + LPSPI_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, LPSPI_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle) +{ + LPSPI_Deinit(handle->base); + vSemaphoreDelete(handle->event); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs SPI transfer. + * + * This function performs an SPI transfer according to data given in the transfer structure. + * + * param handle The RTOS LPSPI handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Busy; + } + + status = LPSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Error; + } + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.h new file mode 100644 index 0000000000..2c6bc1e1d5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_LPSPI_FREERTOS_H__ +#define __FSL_LPSPI_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_lpspi.h" + +/*! + * @addtogroup lpspi_freertos_driver LPSPI FreeRTOS Driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI FreeRTOS driver version 2.0.5. */ +#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! + * @cond RTOS_PRIVATE + * @brief LPSPI FreeRTOS handle + */ +typedef struct _lpspi_rtos_handle +{ + LPSPI_Type *base; /*!< LPSPI base address */ + lpspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ +} lpspi_rtos_handle_t; +/*! \endcond */ + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPSPI RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPSPI instance to initialize. + * @param masterConfig Configuration structure to set-up LPSPI in master mode. + * @param srcClock_Hz Frequency of input clock of the LPSPI module. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle); + +/*! + * @brief Performs SPI transfer. + * + * This function performs an SPI transfer according to data given in the transfer structure. + * + * @param handle The RTOS LPSPI handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_LPSPI_FREERTOS_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c index 44ce32358b..7da69430af 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -700,7 +700,7 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address) * endcode * * param base LPUART peripheral base address. - * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable. */ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) { @@ -727,7 +727,7 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); #endif - /* Check int enable bits in base->CTRL */ + /* Set int enable bits in base->CTRL */ base->CTRL |= mask; } @@ -851,7 +851,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base) * can't be cleared by this function. * Flags that can only cleared or set by hardware are: * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, - * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. * diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h index 24110d51dd..cbe43ddf6a 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief LPUART driver version. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 2)) +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 3)) /*@}*/ /*! @brief Retry times for waiting flag. */ @@ -564,7 +564,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base); * can't be cleared by this function. * Flags that can only cleared or set by hardware are: * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, - * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. * @@ -595,7 +595,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); * @endcode * * @param base LPUART peripheral base address. - * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable. + * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable. */ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c index f18d40cba5..f812f570cd 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -38,6 +38,18 @@ enum ******************************************************************************/ /* Array of LPUART handle. */ +#if (defined(LPUART12)) +#define LPUART_HANDLE_ARRAY_SIZE 13 +#else /* LPUART12 */ +#if (defined(LPUART11)) +#define LPUART_HANDLE_ARRAY_SIZE 12 +#else /* LPUART11 */ +#if (defined(LPUART10)) +#define LPUART_HANDLE_ARRAY_SIZE 11 +#else /* LPUART10 */ +#if (defined(LPUART9)) +#define LPUART_HANDLE_ARRAY_SIZE 10 +#else /* LPUART9 */ #if (defined(LPUART8)) #define LPUART_HANDLE_ARRAY_SIZE 9 #else /* LPUART8 */ @@ -75,6 +87,10 @@ enum #endif /* LPUART 6 */ #endif /* LPUART 7 */ #endif /* LPUART 8 */ +#endif /* LPUART 9 */ +#endif /* LPUART 10 */ +#endif /* LPUART 11 */ +#endif /* LPUART 12 */ /*<! Private handle only used for internally. */ static lpuart_edma_private_handle_t s_lpuartEdmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE]; diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.c new file mode 100644 index 0000000000..bc6a6f7df6 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.c @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_freertos.h" +#include <FreeRTOS.h> +#include <event_groups.h> +#include <semphr.h> + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_freertos" +#endif + +static void LPUART_RTOS_Callback(LPUART_Type *base, lpuart_handle_t *state, status_t status, void *param) +{ + lpuart_rtos_handle_t *handle = (lpuart_rtos_handle_t *)param; + BaseType_t xHigherPriorityTaskWoken, xResult; + + xHigherPriorityTaskWoken = pdFALSE; + xResult = pdFAIL; + + if (status == kStatus_LPUART_RxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_TxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_LPUART_TX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxRingBufferOverrun) + { + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxHardwareOverrun) + { + /* Clear Overrun flag (OR) in LPUART STAT register */ + (void)LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag); + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else + { + xResult = pdFAIL; + } + + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Init + * Description : Initializes the LPUART instance for application + * + *END**************************************************************************/ +/*! + * brief Initializes an LPUART instance for operation in RTOS. + * + * param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * param t_handle The pointer to an allocated space to store the transactional layer internal state. + * param cfg The pointer to the parameters required to configure the LPUART after initialization. + * return kStatus_Success, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg) +{ + status_t status; + lpuart_config_t defcfg; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + if (NULL == t_handle) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg->base) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->srcclk) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->baudrate) + { + return kStatus_InvalidArgument; + } + + handle->base = cfg->base; + handle->t_state = t_handle; + handle->rx_timeout_constant_ms = cfg->rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = cfg->rx_timeout_multiplier_ms; + handle->tx_timeout_constant_ms = cfg->tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = cfg->tx_timeout_multiplier_ms; + +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer); +#else + handle->txSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->txSemaphore) + { + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer); +#else + handle->rxSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->rxSemaphore) + { + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer); +#else + handle->txEvent = xEventGroupCreate(); +#endif + if (NULL == handle->txEvent) + { + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer); +#else + handle->rxEvent = xEventGroupCreate(); +#endif + if (NULL == handle->rxEvent) + { + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + + LPUART_GetDefaultConfig(&defcfg); + + defcfg.baudRate_Bps = cfg->baudrate; + defcfg.parityMode = cfg->parity; + defcfg.stopBitCount = cfg->stopbits; +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + defcfg.enableRxRTS = cfg->enableRxRTS; + defcfg.enableTxCTS = cfg->enableTxCTS; + defcfg.txCtsSource = cfg->txCtsSource; + defcfg.txCtsConfig = cfg->txCtsConfig; +#endif + status = LPUART_Init(handle->base, &defcfg, cfg->srcclk); + if (status != kStatus_Success) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + LPUART_TransferCreateHandle(handle->base, handle->t_state, LPUART_RTOS_Callback, handle); + LPUART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); + + LPUART_EnableTx(handle->base, true); + LPUART_EnableRx(handle->base, true); + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Deinit + * Description : Deinitializes the LPUART instance and frees resources + * + *END**************************************************************************/ +/*! + * brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle) +{ + LPUART_Deinit(handle->base); + + vEventGroupDelete(handle->txEvent); + vEventGroupDelete(handle->rxEvent); + + /* Give the semaphore. This is for functional safety */ + (void)xSemaphoreGive(handle->txSemaphore); + (void)xSemaphoreGive(handle->rxSemaphore); + + vSemaphoreDelete(handle->txSemaphore); + vSemaphoreDelete(handle->rxSemaphore); + + /* Invalidate the handle */ + handle->base = NULL; + handle->t_state = NULL; + + return 0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Send + * Description : Send chars over LPUART + * + *END**************************************************************************/ +/*! + * brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer to send. + * param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) +{ + EventBits_t ev; + int retval = kStatus_Fail; + status_t status; + const TickType_t txTickTimeout = + (length * handle->tx_timeout_multiplier_ms + handle->tx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0u)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->txTransfer.data = (uint8_t *)buffer; + handle->txTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->txSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE, pdTRUE, pdFALSE, + (txTickTimeout > 0u) ? txTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_TX_COMPLETE) != 0u) + { + retval = kStatus_Success; + } + else /* timeout expired or unknown error*/ + { + if (txTickTimeout > 0u) + { + LPUART_TransferAbortSend(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_Fail; + } + } + + if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Receive + * Description : Receives chars from LPUART + * + *END**************************************************************************/ +/*! + * brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer where to write received data. + * param length The number of bytes to receive. + * param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) +{ + EventBits_t ev; + size_t n = 0u; + int retval = kStatus_Fail; + uint32_t local_received = 0u; + status_t status; + const TickType_t rxTickTimeout = + (length * handle->rx_timeout_multiplier_ms + handle->rx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + if (received != NULL) + { + *received = n; + } + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + /* New transfer can be performed only after current one is finished */ + if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->rxTransfer.data = buffer; + handle->rxTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->rxSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits( + handle->rxEvent, + RTOS_LPUART_RX_COMPLETE | RTOS_LPUART_RING_BUFFER_OVERRUN | RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, pdTRUE, + pdFALSE, (rxTickTimeout > 0u) ? rxTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_HARDWARE_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxHardwareOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RING_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxRingBufferOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RX_COMPLETE) != 0u) + { + retval = kStatus_Success; + local_received = length; + } + else /* timeout expired or unknown error*/ + { + if (rxTickTimeout > 0u) + { + (void)LPUART_TransferGetReceiveCount(handle->base, handle->t_state, &local_received); + LPUART_TransferAbortReceive(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_LPUART_Error; + local_received = 0u; + } + } + + /* Prevent repetitive NULL check */ + if (received != NULL) + { + *received = (size_t)local_received; + } + + /* Enable next transfer. Current one is finished */ + if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetRxTimeout + * Description : Modify receive timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->rx_timeout_constant_ms = rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = rx_timeout_multiplier_ms; + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetTxTimeout + * Description : Modify send timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->tx_timeout_constant_ms = tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = tx_timeout_multiplier_ms; + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.h new file mode 100644 index 0000000000..05d842efd4 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_LPUART_RTOS_H__ +#define __FSL_LPUART_RTOS_H__ + +#include "fsl_lpuart.h" +#include <FreeRTOS.h> +#include <event_groups.h> +#include <semphr.h> + +/*! + * @addtogroup lpuart_freertos_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART FreeRTOS driver version. */ +#define FSL_LPUART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*@}*/ + +/*! @brief LPUART RTOS configuration structure. */ +typedef struct _lpuart_rtos_config +{ + LPUART_Type *base; /*!< UART base address */ + uint32_t srcclk; /*!< UART source clock in Hz*/ + uint32_t baudrate; /*!< Desired communication speed */ + lpuart_parity_mode_t parity; /*!< Parity setting */ + lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ + uint8_t *buffer; /*!< Buffer for background reception */ + uint32_t buffer_size; /*!< Size of buffer for background reception */ + /* Zero in constant and multiplier is interpreted as infinit timeout. */ + uint32_t rx_timeout_constant_ms; /*!< RX timeout applied per receive */ + uint32_t rx_timeout_multiplier_ms; /*!< RX timeout added for each byte of the receive. */ + uint32_t tx_timeout_constant_ms; /*!< TX timeout applied per transmition */ + uint32_t tx_timeout_multiplier_ms; /*!< TX timeout added for each byte of the transmition. */ +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif +} lpuart_rtos_config_t; + +/*! + * @cond RTOS_PRIVATE + * @name LPUART event flags + * + * This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t). + */ +/*@{*/ +/*! @brief Event flag - uart transmit complete. */ +#define RTOS_LPUART_TX_COMPLETE 0x1U +/*! @brief Event flag - uart receive complete. */ +#define RTOS_LPUART_RX_COMPLETE 0x2U +/*! @brief Event flag - ring buffer overrun. */ +#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x4U +/*! @brief Event flag - hardware buffer overrun. */ +#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x8U +/*@}*/ + +/*! @brief LPUART FreeRTOS transfer structure. */ +typedef struct _lpuart_rtos_handle +{ + LPUART_Type *base; /*!< UART base address */ + lpuart_transfer_t txTransfer; /*!< TX transfer structure */ + lpuart_transfer_t rxTransfer; /*!< RX transfer structure */ + SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ + SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ + EventGroupHandle_t rxEvent; /*!< RX completion event */ + EventGroupHandle_t txEvent; /*!< TX completion event */ + uint32_t rx_timeout_constant_ms; /*!< RX Timeout applied per transfer */ + uint32_t rx_timeout_multiplier_ms; /*!< RX Timeout added for each byte of the transfer. */ + uint32_t tx_timeout_constant_ms; /*!< TX Timeout applied per transfer */ + uint32_t tx_timeout_multiplier_ms; /*!< TX Timeout added for each byte of the transfer. */ + void *t_state; /*!< Transactional state of the underlying driver */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */ + StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */ + StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */ + StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */ +#endif +} lpuart_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPUART RTOS Operation + * @{ + */ + +/*! + * @brief Initializes an LPUART instance for operation in RTOS. + * + * @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * @param t_handle The pointer to an allocated space to store the transactional layer internal state. + * @param cfg The pointer to the parameters required to configure the LPUART after initialization. + * @return 0 succeed, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg); + +/*! + * @brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * @param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle); + +/*! + * @name LPUART transactional Operation + * @{ + */ + +/*! + * @brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer to send. + * @param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); + +/*! + * @brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer where to write received data. + * @param length The number of bytes to receive. + * @param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); + +/*! + * @brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms); + +/*! + * @brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_LPUART_RTOS_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h index ddc9f3c4bd..fb7feec8ec 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h @@ -1,5 +1,5 @@ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,8 +26,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief NIC301 driver version 2.0.0. */ -#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) +/*! @brief NIC301 driver version 2.0.1. */ +#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) /*@}*/ #define GPV0_BASE (0x41000000UL) @@ -177,7 +177,7 @@ extern "C" { */ static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) { - *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK); + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); __DSB(); } @@ -189,7 +189,7 @@ static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) */ static inline nic_qos_t NIC_GetReadQos(nic_reg_t base) { - return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET)) & NIC_QOS_MASK); + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); } /*! @@ -200,7 +200,7 @@ static inline nic_qos_t NIC_GetReadQos(nic_reg_t base) */ static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) { - *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK); + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); __DSB(); } @@ -212,7 +212,7 @@ static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) */ static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base) { - return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET)) & NIC_QOS_MASK); + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); } /*! @@ -223,7 +223,7 @@ static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base) */ static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v) { - *(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET) = v; + *(volatile uint32_t *)(base) = v; __DSB(); } @@ -235,7 +235,7 @@ static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v) */ static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base) { - return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET)) & NIC_FN_MOD_AHB_MASK); + return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK); } /*! @@ -246,7 +246,7 @@ static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base) */ static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) { - *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK); + *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK); __DSB(); } @@ -258,7 +258,7 @@ static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) */ static inline uint8_t NIC_GetWrTideMark(nic_reg_t base) { - return (uint8_t)((*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET)) & NIC_WR_TIDEMARK_MASK); + return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK); } /*! @@ -269,7 +269,7 @@ static inline uint8_t NIC_GetWrTideMark(nic_reg_t base) */ static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) { - *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value; + *(volatile uint32_t *)(base) = value; __DSB(); } @@ -281,7 +281,7 @@ static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) */ static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base) { - return (nic_fn_mod_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET)) & NIC_FN_MOD_MASK); + return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK); } /*! @@ -292,7 +292,7 @@ static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base) */ static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) { - *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value; + *(volatile uint32_t *)(base) = value; __DSB(); } @@ -304,7 +304,7 @@ static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) */ static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base) { - return (nic_fn_mod2_t)((*(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET)) & NIC_FN_MOD2_MASK); + return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK); } #if defined(__cplusplus) diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction.h new file mode 100644 index 0000000000..379bde9c2c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction.h @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "fsl_common.h" +#include "fsl_os_abstraction_config.h" +#include "generic_list.h" + +/*! + * @addtogroup osa_adapter + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Type for the Task Priority*/ +typedef uint16_t osa_task_priority_t; +/*! @brief Type for a task handler */ +typedef void *osa_task_handle_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ +typedef void *osa_task_param_t; +/*! @brief Type for task pointer. Task prototype declaration */ +typedef void (*osa_task_ptr_t)(osa_task_param_t task_param); +/*! @brief Type for the semaphore handler */ +typedef void *osa_semaphore_handle_t; +/*! @brief Type for the mutex handler */ +typedef void *osa_mutex_handle_t; +/*! @brief Type for the event handler */ +typedef void *osa_event_handle_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ +typedef uint32_t osa_event_flags_t; +/*! @brief Message definition. */ +typedef void *osa_msg_handle_t; +/*! @brief Type for the message queue handler */ +typedef void *osa_msgq_handle_t; +/*! @brief Type for the Timer handler */ +typedef void *osa_timer_handle_t; +/*! @brief Type for the Timer callback function pointer. */ +typedef void (*osa_timer_fct_ptr_t)(void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osa_task_def_tag +{ + osa_task_ptr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; /*!< stack pointer*/ + void *tlink; /*!< link pointer*/ + uint8_t *tname; /*!< name pointer*/ + uint8_t useFloat; /*!< is use float*/ +} osa_task_def_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osa_thread_link_tag +{ + uint8_t link[12]; /*!< link*/ + osa_task_handle_t osThreadId; /*!< thread id*/ + osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/ + uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/ +} osa_thread_link_t, *osa_thread_link_handle_t; + +/*! @brief Definition structure contains timer parameters.*/ +typedef struct osa_time_def_tag +{ + osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */ + void *argument; /* < argument of a timer function */ +} osa_time_def_t; + +/*! @brief Type for the timer definition*/ +typedef enum _osa_timer +{ + KOSA_TimerOnce = 0, /*!< one-shot timer*/ + KOSA_TimerPeriodic = 1 /*!< repeating timer*/ +} osa_timer_t; + +/*! @brief Defines the return status of OSA's functions */ +typedef enum _osa_status +{ + KOSA_StatusSuccess = kStatus_Success, /*!< Success */ + KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */ + KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */ + KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +} osa_status_t; + +#ifdef USE_RTOS +#undef USE_RTOS +#endif + +#define USE_RTOS (1) +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#define OSA_TASK_HANDLE_SIZE (12U) +#else +#define OSA_TASK_HANDLE_SIZE (16U) +#endif +#define OSA_EVENT_HANDLE_SIZE (8U) +#define OSA_SEM_HANDLE_SIZE (4U) +#define OSA_MUTEX_HANDLE_SIZE (4U) +#define OSA_MSGQ_HANDLE_SIZE (4U) +#define OSA_MSG_HANDLE_SIZE (0U) + +/*! @brief Priority setting for OSA. */ +#ifndef OSA_PRIORITY_IDLE +#define OSA_PRIORITY_IDLE (6) +#endif + +#ifndef OSA_PRIORITY_LOW +#define OSA_PRIORITY_LOW (5) +#endif + +#ifndef OSA_PRIORITY_BELOW_NORMAL +#define OSA_PRIORITY_BELOW_NORMAL (4) +#endif + +#ifndef OSA_PRIORITY_NORMAL +#define OSA_PRIORITY_NORMAL (3) +#endif + +#ifndef OSA_PRIORITY_ABOVE_NORMAL +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#endif + +#ifndef OSA_PRIORITY_HIGH +#define OSA_PRIORITY_HIGH (1) +#endif + +#ifndef OSA_PRIORITY_REAL_TIME +#define OSA_PRIORITY_REAL_TIME (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MAX +#define OSA_TASK_PRIORITY_MAX (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MIN +#define OSA_TASK_PRIORITY_MIN (15) +#endif + +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(FSL_RTOS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#elif defined(FSL_RTOS_UCOSII) +#if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)} +#endif +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \ + NULL, NULL, (uint8_t *)#name, (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) &os_thread_def_##name + +#define OSA_TASK_PROTO(name) externosa_task_def_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL} + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) &os_timer_def_##name + +/* ==== Buffer Definition ==== */ + +/*! + * @brief Defines the semaphore handle + * + * This macro is used to define a 4 byte aligned semaphore handle. + * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle. + * + * The macro should be global and could be optional. You could also define semaphore handle by yourself. + * + * This is an example, + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * @endcode + * + * @param name The name string of the semaphore handle. + */ +#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \ + uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the mutex handle + * + * This macro is used to define a 4 byte aligned mutex handle. + * Then use "(osa_mutex_handle_t)name" to get the mutex handle. + * + * The macro should be global and could be optional. You could also define mutex handle by yourself. + * + * This is an example, + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * @endcode + * + * @param name The name string of the mutex handle. + */ +#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the event handle + * + * This macro is used to define a 4 byte aligned event handle. + * Then use "(osa_event_handle_t)name" to get the event handle. + * + * The macro should be global and could be optional. You could also define event handle by yourself. + * + * This is an example, + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * @endcode + * + * @param name The name string of the event handle. + */ +#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the message queue handle + * + * This macro is used to define a 4 byte aligned message queue handle. + * Then use "(osa_msgq_handle_t)name" to get the message queue handle. + * + * The macro should be global and could be optional. You could also define message queue handle by yourself. + * + * This is an example, + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct)); + * @endcode + * + * @param name The name string of the message queue handle. + * @param numberOfMsgs Number of messages. + * @param msgSize Message size. + * + */ + +/*< Macro For FREE_RTOS*/ +#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ + uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the TASK handle + * + * This macro is used to define a 4 byte aligned TASK handle. + * Then use "(osa_task_handle_t)name" to get the TASK handle. + * + * The macro should be global and could be optional. You could also define TASK handle by yourself. + * + * This is an example, + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * @endcode + * + * @param name The name string of the TASK handle. + */ +#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +#include "fsl_os_abstraction_rtthread.h" + +extern const uint8_t gUseRtos_c; + +/* + * alloc the temporary memory to store the status + */ +#define OSA_SR_ALLOC() uint32_t osaCurrentSr; +/* + * Enter critical mode + */ +#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr) +/* + * Exit critical mode and retore the previous mode + */ +#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr) + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Reserves the requested amount of memory in bytes. + * + * The function is used to reserve the requested amount of memory in bytes and initializes it to 0. + * + * @param length Amount of bytes to reserve. + * + * @return Pointer to the reserved memory. NULL if memory can't be allocated. + */ +void *OSA_MemoryAllocate(uint32_t length); + +/*! + * @brief Frees the memory previously reserved. + * + * The function is used to free the memory block previously reserved. + * + * @param p Pointer to the start of the memory block previously reserved. + * + */ +void OSA_MemoryFree(void *p); + +/*! + * @brief Enter critical with nesting mode. + * + * @param sr Store current status and return to caller. + */ +void OSA_EnterCritical(uint32_t *sr); + +/*! + * @brief Exit critical with nesting mode. + * + * @param sr Previous status to restore. + */ +void OSA_ExitCritical(uint32_t sr); + +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * Example below shows how to use this API to create the task handle. + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0); + * OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL); + * @endcode + * + * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_TASK_HANDLE_DEFINE(taskHandle); + * or + * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param thread_def pointer to theosa_task_def_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * @retval KOSA_StatusSuccess The task is successfully created. + * @retval KOSA_StatusError The task can not be created. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval KOSA_StatusSuccess The function is called successfully. + * @retval KOSA_StatusError Error occurs with this function. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is received. + * + * @return Task's priority. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Sets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval KOSA_StatusSuccess Task's priority is set successfully. + * @retval KOSA_StatusError Task's priority can not be set. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Destroys a previously created task. + * + * @param taskHandle The handler of the task to destroy. + * + * @retval KOSA_StatusSuccess The task was successfully destroyed. + * @retval KOSA_StatusError Task destruction failed or invalid parameter. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * Example below shows how to use this API to create the semaphore handle. + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff); + * @endcode + * + * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * or + * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param initValue Initial value the semaphore will be set to. + * + * @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully. + * @retval KOSA_StatusError if the semaphore can not be created. + */ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semaphoreHandle The semaphore handle. + * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer, + * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used. + * + * @retval KOSA_StatusSuccess The semaphore is successfully destroyed. + * @retval KOSA_StatusError The semaphore can not be destroyed. + */ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used + * to wait. + * + * @param semaphoreHandle The semaphore handle. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess The semaphore is received. + * @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semaphoreHandle The semaphore handle to signal. + * + * @retval KOSA_StatusSuccess The semaphore is successfully signaled. + * @retval KOSA_StatusError The object can not be signaled or invalid parameter. + * + */ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * Example below shows how to use this API to create the mutex handle. + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * OSA_MutexCreate((osa_mutex_handle_t)mutexHandle); + * @endcode + * + * @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * or + * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully. + * @retval KOSA_StatusError if the mutex can not be created. + */ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexHandle The mutex handle. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * + * @retval KOSA_StatusSuccess The mutex is locked successfully. + * @retval KOSA_StatusTimeout Timeout occurred. + * @retval KOSA_StatusError Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully unlocked. + * @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter. + */ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully destroyed. + * @retval KOSA_StatusError The mutex can not be destroyed. + * + */ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is 1, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * Example below shows how to use this API to create the event handle. + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * OSA_EventCreate((osa_event_handle_t)eventHandle, 0); + * @endcode + * + * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_EVENT_HANDLE_DEFINE(eventHandle); + * or + * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param autoClear 1 The event is auto-clear. + * 0 The event manual-clear + * @retval KOSA_StatusSuccess the new event if the event is created successfully. + * @retval KOSA_StatusError if the event can not be created. + */ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToSet Flags to be set. + * + * @retval KOSA_StatusSuccess The flags were successfully set. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToClear Flags to be clear. + * + * @retval KOSA_StatusSuccess The flags were successfully cleared. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear); + +/*! + * @brief Get event's flags. + * + * Get specified flags of an event object. + * + * @param eventHandle The event handle. + * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer, + * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used. + * @param flagsMask The flags user want to get are specified by this parameter. + * @param pFlagsOfEvent The event flags are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The event flags were successfully got. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, + osa_event_flags_t flagsMask, + osa_event_flags_t *pFlagsOfEvent); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventHandle The event handle. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The wait condition met and function returns successfully. + * @retval KOSA_StatusTimeout Has not met wait condition within timeout. + * @retval KOSA_StatusError An incorrect parameter was passed. + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventHandle The event handle. + * + * @retval KOSA_StatusSuccess The event is successfully destroyed. + * @retval KOSA_StatusError Event destruction failed. + */ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * Example below shows how to use this API to create the massage queue handle. + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg)); + * @endcode + * + * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel + * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * or + * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param msgNo :number of messages the message queue should accommodate. + * @param msgSize :size of a single message structure. + * + * @retval KOSA_StatusSuccess Message queue successfully Create. + * @retval KOSA_StatusError Message queue create failure. + */ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the KOSA_StatusError; + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval KOSA_StatusSuccess Message successfully put into the queue. + * @retval KOSA_StatusError The queue was full or an invalid parameter was passed. + */ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess Message successfully obtained from the queue. + * @retval KOSA_StatusTimeout The queue remains empty after timeout. + * @retval KOSA_StatusError Invalid parameter. + */ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgqHandle Message Queue handler. + * + * @retval KOSA_StatusSuccess The queue was successfully destroyed. + * @retval KOSA_StatusError Message queue destruction failed. + */ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle); + +/*! + * @brief Enable all interrupts. + */ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. + */ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. + */ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. + */ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +/*! @}*/ +#ifdef __cplusplus +} +#endif +/*! @}*/ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_config.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_config.h new file mode 100644 index 0000000000..234cf972bc --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_config.h @@ -0,0 +1,36 @@ +/*! + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif + +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 1 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif + +/*! @brief Definition to determine whether enable OSA's TASK module. */ +#ifndef OSA_USED +#ifndef FSL_OSA_TASK_ENABLE +#define FSL_OSA_TASK_ENABLE 0U +#endif +#else +#if defined(FSL_OSA_TASK_ENABLE) +#undef FSL_OSA_TASK_ENABLE +#endif +#define FSL_OSA_TASK_ENABLE 1U +#endif /* OSA_USED */ + +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c new file mode 100644 index 0000000000..524744c251 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c @@ -0,0 +1,917 @@ +/*! ********************************************************************************* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019 NXP + * All rights reserved. + * + * + * This is the source file for the OS Abstraction layer for freertos. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "fsl_os_abstraction.h" +#include "fsl_os_abstraction_rtthread.h" +#include <string.h> +#include "generic_list.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U) + +#ifdef DEBUG_ASSERT +#define OS_ASSERT(condition) \ + if (!(condition)) \ + while (1) \ + ; +#else +#define OS_ASSERT(condition) (void)(condition); +#endif + +/*! @brief Converts milliseconds to ticks*/ +#define MSEC_TO_TICK(msec) \ + (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ)) +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ +typedef struct osa_freertos_task +{ + list_element_t link; + rt_thread_t taskHandle; +} osa_freertos_task_t; + +typedef struct _osa_event_struct +{ + rt_event_t handle; /* The event handle */ + uint8_t autoClear; /*!< Auto clear or manual clear */ +} osa_event_struct_t; + +/*! @brief State structure for bm osa manager. */ +typedef struct _osa_state +{ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + list_label_t taskList; + OSA_TASK_HANDLE_DEFINE(mainTaskHandle); +#endif + uint32_t basePriority; + int32_t basePriorityNesting; + uint32_t interruptDisableCount; +} osa_state_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +__WEAK_FUNC void main_task(void const *argument); +__WEAK_FUNC void main_task(void const *argument) +{ +} + +void startup_task(void *argument); + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS + +static osa_state_t s_osaState = {0}; +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryAllocate + * Description : Reserves the requested amount of memory in bytes. + * + *END**************************************************************************/ +void *OSA_MemoryAllocate(uint32_t length) +{ + void *p = rt_malloc(length); + + if (RT_NULL != p) + { + rt_memset(p, 0, length); + } + + return p; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryFree + * Description : Frees the memory previously reserved. + * + *END**************************************************************************/ +void OSA_MemoryFree(void *p) +{ + rt_free(p); +} + +void OSA_EnterCritical(uint32_t *sr) +{ + if (rt_thread_self() != RT_NULL) + rt_enter_critical(); +} + +void OSA_ExitCritical(uint32_t sr) +{ + if (rt_thread_self() != RT_NULL) + rt_exit_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : startup_task + * Description : Wrapper over main_task.. + * + *END**************************************************************************/ +void startup_task(void *argument) +{ + main_task(argument); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetCurrentHandle + * Description : This function is used to get current active task's handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void) +{ + list_element_handle_t list_element; + osa_freertos_task_t *ptask; + + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + ptask = (osa_freertos_task_t *)(void *)list_element; + if (ptask->taskHandle == xTaskGetCurrentTaskHandle()) + { + return (osa_task_handle_t)ptask; + } + list_element = LIST_GetNext(list_element); + } + return NULL; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskYield + * Description : When a task calls this function, it will give up CPU and put + * itself to the tail of ready list. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void) +{ + taskYIELD(); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetPriority + * Description : This function returns task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(ptask->taskHandle))); +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskSetPriority + * Description : This function sets task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(taskPriority)); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskCreate + * Description : This function is used to create a task and make it ready. + * Param[in] : threadDef - Definition of the thread. + * task_param - Parameter to pass to the new thread. + * Return Thread handle of the new thread, or NULL if failed. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param) +{ + assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); + assert(taskHandle); + TaskHandle_t pxCreatedTask; + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + + if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */ + (char const *)thread_def->tname, /* task name for kernel awareness debugging */ + (configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */ + (task_param_t)task_param, /* optional task startup argument */ + PRIORITY_OSA_TO_RTOS(thread_def->tpriority), /* initial priority */ + &pxCreatedTask /* optional task handle to create */ + ) == pdPASS) + { + ptask->taskHandle = pxCreatedTask; + OSA_InterruptDisable(); + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link)); + OSA_InterruptEnable(); + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskDestroy + * Description : This function destroy a task. + * Param[in] :taskHandle - Thread handle. + * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + osa_status_t status; + uint16_t oldPriority; + /*Change priority to avoid context switches*/ + oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle()); + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME); +#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */ + vTaskDelete((task_handler_t)ptask->taskHandle); + status = KOSA_StatusSuccess; +#else + status = KOSA_StatusError; /* vTaskDelete() not available */ +#endif + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority); + OSA_InterruptDisable(); + (void)LIST_RemoveElement(taskHandle); + OSA_InterruptEnable(); + return status; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeDelay + * Description : This function is used to suspend the active thread for the given number of milliseconds. + * + *END**************************************************************************/ +void OSA_TimeDelay(uint32_t millisec) +{ + rt_thread_mdelay(millisec); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeGetMsec + * Description : This function gets current time in milliseconds. + * + *END**************************************************************************/ +uint32_t OSA_TimeGetMsec(void) +{ + return rt_tick_get_millisecond(); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreCreate + * Description : This function is used to create a semaphore. + * Return : Semaphore handle of the new semaphore, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) +{ + assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE); + assert(semaphoreHandle); + + union + { + rt_sem_t sem; + uint32_t semhandle; + } xSemaHandle; + + xSemaHandle.sem = rt_sem_create("osa_sem", initValue, RT_IPC_FLAG_PRIO); + if (NULL != xSemaHandle.sem) + { + *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreDestroy + * Description : This function is used to destroy a semaphore. + * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + rt_sem_delete(sem); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreWait + * Description : This function checks the semaphore's counting value, if it is + * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout + * will be used for wait. The parameter timeout indicates how long should wait + * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will + * return KOSA_StatusTimeout immediately if semaphore is not positive. + * This function returns KOSA_StatusSuccess if the semaphore is received, returns + * KOSA_StatusTimeout if the semaphore is not received within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec) +{ + int32_t timeoutTicks; + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (RT_EOK != rt_sem_take(sem, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphorePost + * Description : This function is used to wake up one task that wating on the + * semaphore. If no task is waiting, increase the semaphore. The function returns + * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + rt_sem_release(sem); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexCreate + * Description : This function is used to create a mutex. + * Return : Mutex handle of the new mutex, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) +{ + assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE); + assert(mutexHandle); + + union + { + rt_mutex_t mutex; + uint32_t pmutexHandle; + } xMutexHandle; + + xMutexHandle.mutex = rt_mutex_create("osa_mutex", RT_IPC_FLAG_PRIO); + if (RT_NULL != xMutexHandle.mutex) + { + *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexLock + * Description : This function checks the mutex's status, if it is unlocked, + * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex. + * This function returns KOSA_StatusSuccess if the mutex is obtained, returns + * KOSA_StatusError if any errors occur during waiting. If the mutex has been + * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately. + * + *END**************************************************************************/ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) +{ + assert(mutexHandle); + int32_t timeoutTicks; + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (RT_EOK != rt_mutex_take(mutex, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexUnlock + * Description : This function is used to unlock a mutex. + * + *END**************************************************************************/ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + rt_mutex_release(mutex); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexDestroy + * Description : This function is used to destroy a mutex. + * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + rt_mutex_delete(mutex); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventCreate + * Description : This function is used to create a event object. + * Return : Event handle of the new event, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + pEventStruct->handle = rt_event_create("osa_event", RT_IPC_FLAG_PRIO); + if (RT_NULL != pEventStruct->handle) + { + pEventStruct->autoClear = autoClear; + } + else + { + return KOSA_StatusError; + } + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventSet + * Description : Set one or more event flags of an event object. + * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet) +{ + rt_err_t result; + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + rt_event_send(pEventStruct->handle, (rt_uint32_t)flagsToSet); + + (void)result; + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventClear + * Description : Clear one or more event flags of an event object. + * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + rt_uint32_t recved; + rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToClear, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 0, &recved); + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventGet + * Description : This function is used to get event's flags that specified by prameter + * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So + * you should pass the parameter 0xffffffff to specify you want to check all. + * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + rt_uint32_t eventFlags; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + if (RT_NULL == pFlagsOfEvent) + { + return KOSA_StatusError; + } + + if (RT_EOK != rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsMask, RT_EVENT_FLAG_OR, 0, &eventFlags)) + { + eventFlags = 0; + } + + *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask; + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventWait + * Description : This function checks the event's status, if it meets the wait + * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for + * wait. The parameter timeout indicates how long should wait in milliseconds. + * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value + * KOSA_StatusTimeout immediately if wait condition is not met. The event flags + * will be cleared if the event is auto clear mode. Flags that wakeup waiting + * task could be obtained from the parameter setFlags. + * This function returns KOSA_StatusSuccess if wait condition is met, returns + * KOSA_StatusTimeout if wait condition is not met within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags) +{ + assert(eventHandle); + rt_uint8_t option = 0; + rt_int32_t timeoutTicks; + rt_uint32_t flagsSave; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + /* Clean FreeRTOS cotrol flags */ + flagsToWait = flagsToWait & 0x00FFFFFFU; + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (pEventStruct->autoClear != 0U) + { + option |= RT_EVENT_FLAG_CLEAR; + } + option |= waitAll ? RT_EVENT_FLAG_AND : RT_EVENT_FLAG_OR; + + rt_err_t status = rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToWait, option, timeoutTicks, &flagsSave); + + flagsSave &= (rt_uint32_t)flagsToWait; + if (RT_NULL != pSetFlags) + { + *pSetFlags = (osa_event_flags_t)flagsSave; + } + + if (RT_EOK != status) + { + return KOSA_StatusTimeout; + } + else + { + return KOSA_StatusSuccess; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventDestroy + * Description : This function is used to destroy a event object. Return + * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise + * return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + rt_event_delete(pEventStruct->handle); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQCreate + * Description : This function is used to create a message queue. + * Return : the handle to the message queue if create successfully, otherwise + * return NULL. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) +{ + assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE); + assert(msgqHandle); + + union + { + rt_mq_t msgq; + uint32_t pmsgqHandle; + } xMsgqHandle; + + /* Create the message queue where the number and size is specified by msgNo and msgSize */ + xMsgqHandle.msgq = rt_mq_create("osa_mq", msgSize, msgNo, RT_IPC_FLAG_PRIO); + if (RT_NULL != xMsgqHandle.msgq) + { + *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQPut + * Description : This function is used to put a message to a message queue. + * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage) +{ + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + if (RT_EOK == rt_mq_send(handler, pMessage, handler->msg_size)) + { + return KOSA_StatusSuccess; + } + else + { + return KOSA_StatusError; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQGet + * Description : This function checks the queue's status, if it is not empty, + * get message from it and return KOSA_StatusSuccess, otherwise, timeout will + * be used for wait. The parameter timeout indicates how long should wait in + * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return + * KOSA_StatusTimeout immediately if queue is empty. + * This function returns KOSA_StatusSuccess if message is got successfully, + * returns KOSA_StatusTimeout if message queue is empty within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec) +{ + osa_status_t osaStatus; + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + int32_t timeoutTicks; + + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + if (RT_EOK != rt_mq_recv(handler, pMessage, handler->msg_size, timeoutTicks)) + { + osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */ + } + else + { + osaStatus = KOSA_StatusSuccess; + } + return osaStatus; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQDestroy + * Description : This function is used to destroy the message queue. + * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) +{ + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + rt_mq_delete(handler); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + rt_exit_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + rt_enter_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableIRQGlobal + * Description : enable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_EnableIRQGlobal(void) +{ + if (s_osaState.interruptDisableCount > 0U) + { + s_osaState.interruptDisableCount--; + + if (0U == s_osaState.interruptDisableCount) + { + __enable_irq(); + } + /* call core API to enable the global interrupt*/ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableIRQGlobal + * Description : disable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_DisableIRQGlobal(void) +{ + /* call core API to disable the global interrupt*/ + __disable_irq(); + + /* update counter*/ + s_osaState.interruptDisableCount++; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InstallIntHandler + * Description : This function is used to install interrupt handler. + * + *END**************************************************************************/ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)) +{ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_suppress = Pm138") +#endif +#if defined(ENABLE_RAM_VECTOR_TABLE) + (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_remark = PM138") +#endif +} + +/*!********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + +static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0); + +int main(void) +{ + extern void BOARD_InitHardware(void); + /* Initialize MCU clock */ + BOARD_InitHardware(); + LIST_Init((&s_osaState.taskList), 0); + + s_osaState.basePriorityNesting = 0; + s_osaState.interruptDisableCount = 0; + (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL); + + vTaskStartScheduler(); + return 0; +} +#endif /* FSL_OSA_TASK_ENABLE */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.h new file mode 100644 index 0000000000..40bd24271a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.h @@ -0,0 +1,130 @@ +/*! ********************************************************************************* + * Copyright (c) 2013-2014, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * ile + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ +#if !defined(__FSL_OS_ABSTRACTION_RTTHREAD_H__) +#define __FSL_OS_ABSTRACTION_RTTHREAD_H__ + +#if defined(__IAR_SYSTEMS_ICC__) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + */ +// http://supp.iar.com/Support/?note=24725 + +#define MISRAC_DISABLE \ + _Pragma( \ + "diag_suppress= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") + +#define MISRAC_ENABLE \ + _Pragma( \ + "diag_default= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") +#else +/* Empty MISRA C macros for other toolchains. */ +#define MISRAC_DISABLE +#define MISRAC_ENABLE +#endif + +MISRAC_DISABLE +#include <rtthread.h> +MISRAC_ENABLE + +/*! + * @addtogroup os_abstraction_free_rtos + * @{ + */ + +/******************************************************************************* + * Declarations + ******************************************************************************/ +/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ +typedef rt_thread_t task_handler_t; + +/*! @brief Type for a task stack.*/ +typedef rt_uint32_t task_stack_t; + +/*! @brief Type for task parameter */ +typedef void *task_param_t; + +/*! @brief Type for an event flags object.*/ +typedef rt_uint32_t event_flags_t; + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define OSA_WAIT_FOREVER 0xFFFFFFFFU + +/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */ +#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU + +/*! @brief The default interrupt handler installed in vector table. */ +#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR)) + +extern void DefaultISR(void); + +/*! + * @name Thread management + * @{ + */ + +/*! + * @brief To provide unified task piority for upper layer, OSA layer makes conversion. + */ +#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U) +#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U) + +/* @}*/ + +/*! + * @name Message queues + * @{ + */ + +/*! + * @brief This macro statically reserves the memory required for the queue. + * + * @param name Identifier for the memory region. + * @param number Number of elements in the queue. + * @param size Size of every elements in words. + */ +#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL + +/* @}*/ + +/*! @}*/ +/*! @}*/ +/*! @}*/ + +#endif // __FSL_OS_ABSTRACTION_RTTHREAD_H__ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c index 502037539b..2e55f5d7b8 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2021 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * @@ -48,6 +48,30 @@ #define PXP_ADDR_CPU_2_IP(addr) (addr) #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) +#define S1_COLOR_MODE PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE +#define S1_ALPHA_MODE PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE +#define S1_GLOBAL_ALPHA_MODE PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE +#define S1_S0_FACTOR_MODE PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE +#define S0_COLOR_MODE PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE +#define S0_ALPHA_MODE PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE +#define S0_GLOBAL_ALPHA_MODE PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE +#define S0_S1_FACTOR_MODE PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE +#define PORTER_DUFF_ENABLE_MASK PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK +#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ + +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +#define S1_COLOR_MODE PXP_ALPHA_A_CTRL_S1_COLOR_MODE +#define S1_ALPHA_MODE PXP_ALPHA_A_CTRL_S1_ALPHA_MODE +#define S1_GLOBAL_ALPHA_MODE PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE +#define S1_S0_FACTOR_MODE PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE +#define S0_COLOR_MODE PXP_ALPHA_A_CTRL_S0_COLOR_MODE +#define S0_ALPHA_MODE PXP_ALPHA_A_CTRL_S0_ALPHA_MODE +#define S0_GLOBAL_ALPHA_MODE PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE +#define S0_S1_FACTOR_MODE PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE +#define PORTER_DUFF_ENABLE_MASK PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_MASK +#endif /* FSL_FEATURE_PXP_V3 */ + typedef union _u32_f32 { float f32; @@ -168,17 +192,17 @@ static uint32_t PXP_GetInstance(PXP_Type *base) static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits) { /* One bit reserved for sign bit. */ - assert(intBits + fracBits < 32); + assert(intBits + fracBits < 32U); u32_f32_t u32_f32; uint32_t ret; u32_f32.f32 = floatValue; uint32_t floatBits = u32_f32.u32; - int32_t expValue = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127; + int32_t expValue = (int32_t)((uint16_t)((floatBits & 0x7F800000UL) >> 23U)) - 127; ret = (floatBits & 0x007FFFFFU) | 0x00800000U; - expValue += fracBits; + expValue += (int32_t)fracBits; if (expValue < 0) { @@ -188,17 +212,17 @@ static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t frac { /* should not exceed 31-bit when left shift. */ assert((expValue - 23) <= 7); - ret <<= (expValue - 23); + ret <<= ((uint16_t)expValue - 23U); } else { - ret >>= (23 - expValue); + ret >>= (23U - (uint16_t)expValue); } /* Set the sign bit. */ - if (floatBits & 0x80000000U) + if ((floatBits & 0x80000000UL) != 0U) { - ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1)); + ret = ((~ret) + 1UL) & ~(((uint32_t)-1) << ((uint32_t)intBits + (uint32_t)fracBits + 1UL)); } return ret; @@ -359,6 +383,32 @@ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t base->AS_CTRL = reg; } +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * brief Set the alpha surface blending configuration for the secondary engine. + * + * param base PXP peripheral base address. + * param config Pointer to the configuration structure. + */ +void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config) +{ + assert(NULL != config); + + base->ALPHA_B_CTRL_1 = + (base->ALPHA_B_CTRL_1 & ~(PXP_ALPHA_B_CTRL_1_ROP_MASK | PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK)) | + PXP_ALPHA_B_CTRL_1_ROP((uint32_t)config->ropMode) | PXP_ALPHA_B_CTRL_1_ROP_ENABLE((uint32_t)config->ropEnable); + + if (config->invertAlpha) + { + base->AS_CTRL |= PXP_AS_CTRL_ALPHA1_INVERT_MASK; + } + else + { + base->AS_CTRL &= ~PXP_AS_CTRL_ALPHA1_INVERT_MASK; + } +} +#endif /* FSL_FEATURE_PXP_V3 */ + /*! * brief Set the alpha surface position in output buffer. * @@ -375,6 +425,43 @@ void PXP_SetAlphaSurfacePosition( base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX); } +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * brief Set the alpha surface overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface + * pixel value for that location. If no PS image is present or if the PS image also + * matches its colorkey range, the PS background color is used. + * + * param base PXP peripheral base address. + * param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * param colorKeyLow Color key low range. + * param colorKeyHigh Color key high range. + * + * note Colorkey operations are higher priority than alpha or ROP operations + */ +void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + switch (num) + { + case 0: + base->AS_CLRKEYLOW = colorKeyLow; + base->AS_CLRKEYHIGH = colorKeyHigh; + break; + + case 1: + base->AS_CLRKEYLOW_1 = colorKeyLow; + base->AS_CLRKEYHIGH_1 = colorKeyHigh; + break; + + default: + /* Only 2 alpha process engine instances are supported. */ + assert(false); + break; + } +} +#else /*! * brief Set the alpha surface overlay color key. * @@ -394,6 +481,7 @@ void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, ui base->AS_CLRKEYLOW = colorKeyLow; base->AS_CLRKEYHIGH = colorKeyHigh; } +#endif /* FSL_FEATURE_PXP_V3 */ /*! * brief Set the process surface input buffer configuration. @@ -456,6 +544,39 @@ void PXP_SetProcessSurfacePosition( base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX); } +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * brief Set the process surface color key. + * + * If the PS image matches colorkey range, the PS background color is output. Set + * p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying. + * + * param base PXP peripheral base address. + * param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * param colorKeyLow Color key low range. + * param colorKeyHigh Color key high range. + */ +void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + switch (num) + { + case 0: + base->PS_CLRKEYLOW = colorKeyLow; + base->PS_CLRKEYHIGH = colorKeyHigh; + break; + + case 1: + base->PS_CLRKEYLOW_1 = colorKeyLow; + base->PS_CLRKEYHIGH_1 = colorKeyHigh; + break; + + default: + /* Only 2 alpha process engine instances are supported. */ + assert(false); + break; + } +} +#else /*! * brief Set the process surface color key. * @@ -471,6 +592,7 @@ void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_ base->PS_CLRKEYLOW = colorKeyLow; base->PS_CLRKEYHIGH = colorKeyHigh; } +#endif /* FSL_FEATURE_PXP_V3 */ /*! * brief Set the PXP outpt buffer configuration. @@ -496,9 +618,101 @@ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t * otherwise the dither engine could not work. */ #if defined(PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) - base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(config->width - 1U) | - PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(config->height - 1U); + base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->width - 1U) | + PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->height - 1U); +#endif +} + +/*! + * brief Build a solid rectangle of given pixel value. + * + * param base PXP peripheral base address. + * param outFormat output pixel format. + * param value The value of the pixel to be filled in the rectangle in ARGB8888 format. + * param width width of the rectangle. + * param height height of the rectangle. + * param pitch output pitch in byte. + * param outAddr address of the memory to store the rectangle. + */ +void PXP_BuildRect(PXP_Type *base, + pxp_output_pixel_format_t outFormat, + uint32_t value, + uint16_t width, + uint16_t height, + uint16_t pitch, + uint32_t outAddr) +{ + /* Only support RGB format output. */ + assert((uint8_t)outFormat <= (uint8_t)kPXP_OutputPixelFormatRGB565); + + /* PS configuration */ +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + PXP_SetProcessSurfaceBackGroundColor(base, 0U, value); +#else + PXP_SetProcessSurfaceBackGroundColor(base, value); +#endif + PXP_SetProcessSurfacePosition(base, 0xFFFF, 0xFFFF, 0, 0); + + if ((outFormat == kPXP_OutputPixelFormatARGB8888) || (outFormat == kPXP_OutputPixelFormatARGB1555) || + (outFormat == kPXP_OutputPixelFormatARGB4444)) + { + uint8_t alpha = (uint8_t)(value >> 24U); + pxp_as_buffer_config_t asBufferConfig = { + .pixelFormat = kPXP_AsPixelFormatARGB8888, + .bufferAddr = outAddr, + .pitchBytes = pitch, + }; + PXP_SetAlphaSurfaceBufferConfig(base, &asBufferConfig); + + pxp_as_blend_config_t asBlendConfig = { + .alpha = alpha, .invertAlpha = false, .alphaMode = kPXP_AlphaOverride, .ropMode = kPXP_RopMergeAs}; + PXP_SetAlphaSurfaceBlendConfig(base, &asBlendConfig); +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + PXP_SetAlphaSurfaceOverlayColorKey(base, 0U, 0U, 0xFFFFFFFFUL); + PXP_EnableAlphaSurfaceOverlayColorKey(base, 0U, true); +#else + PXP_SetAlphaSurfaceOverlayColorKey(base, 0U, 0xFFFFFFFFUL); + PXP_EnableAlphaSurfaceOverlayColorKey(base, true); #endif + PXP_SetAlphaSurfacePosition(base, 0, 0, width, height); + } + else + { + /* No need to configure AS for formats that do not have alpha value. */ + PXP_SetAlphaSurfacePosition(base, 0xFFFFU, 0xFFFFU, 0, 0); + } + + /* Output config. */ + pxp_output_buffer_config_t outputBufferConfig; + outputBufferConfig.pixelFormat = outFormat; + outputBufferConfig.interlacedMode = kPXP_OutputProgressive; + outputBufferConfig.buffer0Addr = outAddr; + outputBufferConfig.buffer1Addr = 0U; + outputBufferConfig.pitchBytes = pitch; + outputBufferConfig.width = width; + outputBufferConfig.height = height; + PXP_SetOutputBufferConfig(base, &outputBufferConfig); + + PXP_EnableCsc1(base, false); + +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + PXP_SetPath(PXP, kPXP_Mux3SelectCsc1Engine); + PXP_SetPath(PXP, kPXP_Mux8SelectAlphaBlending0); + PXP_SetPath(PXP, kPXP_Mux11SelectMux8); + PXP_SetPath(PXP, kPXP_Mux14SelectMux11); + PXP_SetPath(PXP, kPXP_Mux0SelectNone); + PXP_SetPath(PXP, kPXP_Mux6SelectNone); + PXP_SetPath(PXP, kPXP_Mux9SelectNone); + PXP_SetPath(PXP, kPXP_Mux12SelectNone); +#endif + + PXP_ClearStatusFlags(base, (uint32_t)kPXP_CompleteFlag); + /* Start PXP. */ + PXP_Start(base); + /* Wait for process complete. */ + while (0UL == ((uint32_t)kPXP_CompleteFlag & PXP_GetStatusFlags(base))) + { + } } /*! @@ -547,28 +761,33 @@ void PXP_SetNextCommand(PXP_Type *base, void *commandAddr) void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config) { assert(NULL != config); + uint32_t tempReg; base->CSC2_CTRL = (base->CSC2_CTRL & ~PXP_CSC2_CTRL_CSC_MODE_MASK) | PXP_CSC2_CTRL_CSC_MODE(config->mode); - base->CSC2_COEF0 = - (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT) | - (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A2_SHIFT); + tempReg = + (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT); + base->CSC2_COEF0 = tempReg | (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) + << PXP_CSC2_COEF0_A2_SHIFT); - base->CSC2_COEF1 = - (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT) | - (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_B1_SHIFT); + tempReg = + (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT); + base->CSC2_COEF1 = tempReg | (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) + << PXP_CSC2_COEF1_B1_SHIFT); - base->CSC2_COEF2 = - (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT) | - (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B3_SHIFT); + tempReg = + (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT); + base->CSC2_COEF2 = tempReg | (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) + << PXP_CSC2_COEF2_B3_SHIFT); - base->CSC2_COEF3 = - (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT) | - (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C2_SHIFT); + tempReg = + (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT); + base->CSC2_COEF3 = tempReg | (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) + << PXP_CSC2_COEF3_C2_SHIFT); - base->CSC2_COEF4 = - (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT) | - PXP_CSC2_COEF4_D1(config->D1); + tempReg = + (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT); + base->CSC2_COEF4 = tempReg | PXP_CSC2_COEF4_D1(config->D1); base->CSC2_COEF5 = PXP_CSC2_COEF5_D2(config->D2) | PXP_CSC2_COEF5_D3(config->D3); } @@ -685,8 +904,8 @@ status_t PXP_LoadLutTable( else { /* Number of bytes must be divisable by 8. */ - if ((bytesNum & 0x07U) || (bytesNum < 8U) || (lutStartAddr & 0x07U) || - (bytesNum + lutStartAddr > PXP_LUT_TABLE_BYTE)) + if (((bytesNum & 0x07U) != 0U) || (bytesNum < 8U) || ((lutStartAddr & 0x07U) != 0U) || + (bytesNum + (uint32_t)lutStartAddr > PXP_LUT_TABLE_BYTE)) { return kStatus_InvalidArgument; } @@ -702,7 +921,7 @@ status_t PXP_LoadLutTable( __DSB(); /* Wait for transfer completed. */ - while (!(base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)) + while (0U == (base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)) { } } @@ -723,12 +942,12 @@ status_t PXP_LoadLutTable( */ void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr) { - assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE); + assert(((uint32_t)memStartAddr + bytesNum) <= (uint32_t)PXP_INTERNAL_RAM_LUT_BYTE); base->INIT_MEM_CTRL = PXP_INIT_MEM_CTRL_ADDR(memStartAddr) | PXP_INIT_MEM_CTRL_SELECT(ram) | PXP_INIT_MEM_CTRL_START_MASK; - while (bytesNum--) + while (0U != bytesNum--) { base->INIT_MEM_DATA = (uint32_t)(*data); data++; @@ -773,18 +992,53 @@ void PXP_EnableDither(PXP_Type *base, bool enable) if (enable) { base->CTRL_SET = PXP_CTRL_ENABLE_DITHER_MASK; - /* Route dither output to output buffer. */ - base->DATA_PATH_CTRL0 &= ~PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK; } else { base->CTRL_CLR = PXP_CTRL_ENABLE_DITHER_MASK; - /* Route MUX 12 output to output buffer. */ - base->DATA_PATH_CTRL0 |= PXP_DATA_PATH_CTRL0_MUX14_SEL(1U); } } #endif /* FSL_FEATURE_PXP_HAS_DITHER */ +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * brief Set the Porter Duff configuration for one of the alpha process engine. + * + * param base PXP peripheral base address. + * param num instance number. + * param config Pointer to the configuration. + */ +void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config) +{ + assert(NULL != config); + + union + { + pxp_porter_duff_config_t pdConfigStruct; + uint32_t u32; + } pdConfig; + + pdConfig.pdConfigStruct = *config; + + switch (num) + { + case 0: + base->ALPHA_A_CTRL = pdConfig.u32; + break; + + case 1: + base->ALPHA_B_CTRL = pdConfig.u32; + break; + + default: + /* Only 2 alpha process engine instances are supported. */ + assert(false); + break; + } +} +#endif /* FSL_FEATURE_PXP_V3 */ + +#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) /*! * brief Set the Porter Duff configuration. * @@ -805,7 +1059,10 @@ void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *con base->PORTER_DUFF_CTRL = pdConfig.u32; } +#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ +#if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \ + (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3) /*! * brief Get the Porter Duff configuration by blend mode. * @@ -826,64 +1083,52 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d static const uint32_t pdCtrl[] = { /* kPXP_PorterDuffSrc */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), /* kPXP_PorterDuffAtop */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), /* kPXP_PorterDuffOver */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), /* kPXP_PorterDuffIn */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), /* kPXP_PorterDuffOut */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), /* kPXP_PorterDuffDst */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne), /* kPXP_PorterDuffDstAtop */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight), /* kPXP_PorterDuffDstOver */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne), /* kPXP_PorterDuffDstIn */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight), /* kPXP_PorterDuffDstOut */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), /* kPXP_PorterDuffXor */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed), /* kPXP_PorterDuffClear */ - PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK | - PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | - PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), + PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) | + S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero), }; if (mode >= kPXP_PorterDuffMax) @@ -892,12 +1137,10 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d } else { - pdConfig.u32 = pdCtrl[(uint32_t)mode] | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) | - PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) | - PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) | - PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) | - PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(kPXP_PorterDuffAlphaStraight) | - PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(kPXP_PorterDuffAlphaStraight); + pdConfig.u32 = pdCtrl[(uint32_t)mode] | S0_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) | + S1_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) | S0_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) | + S1_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) | S0_ALPHA_MODE(kPXP_PorterDuffAlphaStraight) | + S1_ALPHA_MODE(kPXP_PorterDuffAlphaStraight); *config = pdConfig.pdConfigStruct; @@ -906,6 +1149,7 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d return status; } +#endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ static void PXP_StartRectCopy(PXP_Type *base, uint32_t srcAddr, @@ -943,7 +1187,7 @@ static void PXP_StartRectCopy(PXP_Type *base, PXP_SetAlphaSurfaceBufferConfig(base, &asBufferConfig); PXP_SetAlphaSurfacePosition(base, 0U, 0U, width - 1U, height - 1U); - /* Alpha mode set to ROP, AS OR PS*/ + /* Alpha mode set to ROP, AS OR PS */ const pxp_as_blend_config_t asBlendConfig = { .alpha = 0U, .invertAlpha = false, .alphaMode = kPXP_AlphaRop, .ropMode = kPXP_RopMergeAs}; @@ -1049,3 +1293,898 @@ status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, u return kStatus_Success; } + +/*! + * brief Copy continous memory. + * + * param base PXP peripheral base address. + * retval kStatus_Success Successfully started the copy process. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size) +{ + uint16_t pitchBytes; + uint32_t height; + uint32_t unalignedSize; + + if (0U == size) + { + return kStatus_InvalidArgument; + } + + /* For 512 not aligned part, copy by CPU. */ + unalignedSize = size % 512U; + + if (0UL != unalignedSize) + { + (void)memcpy((uint8_t *)destAddr, (uint8_t *)srcAddr, unalignedSize); + + destAddr += unalignedSize; + srcAddr += unalignedSize; + size -= unalignedSize; + } + + if (0UL != size) + { + /* + * By default, PXP process block is 8x8. For better performance, choose + * width and height dividable by block size. + */ + if (size < 8U * 512U) + { + height = 8U; + pitchBytes = (uint16_t)(size / height); + } + else + { + pitchBytes = 512U; + height = size / pitchBytes; + } + + if (height > PXP_MAX_HEIGHT) + { + return kStatus_InvalidArgument; + } + + PXP_StartRectCopy(base, srcAddr, pitchBytes, destAddr, pitchBytes, pitchBytes / 4U, (uint16_t)height, + kPXP_AsPixelFormatARGB8888); + + while (0UL == ((uint32_t)kPXP_CompleteFlag & PXP_GetStatusFlags(base))) + { + } + + PXP_ClearStatusFlags(base, (uint32_t)kPXP_CompleteFlag); + } + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + +/*! + * brief Configures one channle of some block's fetch engine. + * + * Fetch engine is 64-bit input and 32-bit output per channel + * + * param base PXP peripheral base address. + * param name which block the fetch engine belongs to. + * param channel channel number. + * param config pointer to the configuration structure. + * retval kStatus_Success Successfully configured the engine. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetFetchEngineConfig(PXP_Type *base, + pxp_fetch_engine_name_t name, + uint8_t channel, + const pxp_fetch_engine_config_t *config) +{ + assert(NULL != config); + + /* Check fetch address */ + if ((config->inputBaseAddr0 == 0U) || + ((config->inputBaseAddr1 == 0U) && (config->pixelFormat == kPXP_FetchFormatYUV422_2P))) + { + return kStatus_InvalidArgument; + } + /* Must enable expand when input pixel format is YUV422_2P, to combine Y and UV buffer to one output. */ + if ((config->expandEnable == false) && (config->pixelFormat == kPXP_FetchFormatYUV422_2P)) + { + return kStatus_InvalidArgument; + } + /* Must enable block if flip or rotation is enabled. */ + if ((config->fetchFormat.enableblock == false) && + ((config->flipMode != kPXP_FlipDisable) || (config->rotateDegree != kPXP_Rotate0))) + { + return kStatus_InvalidArgument; + } + /* Block mode cannot work in 64-bit mode */ + if ((config->fetchFormat.enableblock == true) && (config->activeBits == kPXP_Active64Bits)) + { + return kStatus_InvalidArgument; + } + + uint32_t ctrlReg = 0U; + uint32_t ulcReg = 0U; + uint32_t lrcReg = 0U; + uint32_t fetchSizeReg = 0U; + uint32_t shiftCtrlReg = 0U; + uint32_t shiftOffsetReg = 0U; + uint32_t shiftWidthReg = 0U; + uint8_t scanlineNum = 0U; + + /* When block disabled, handshake scanline mode can only use 1 line mode where scanlineNum = 0. */ + if (config->fetchFormat.enableblock) + { + /* */ + if (config->fetchFormat.blockSize16) + { + scanlineNum = 2; + } + else + { + scanlineNum = 1; + } + } + + ctrlReg = PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM((uint32_t)scanlineNum) | + PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(config->fetchFormat.burstLength) | + PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE((uint32_t)config->rotateDegree) | + ((uint32_t)config->flipMode << PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT) | + PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE((uint32_t)config->wordOrder) | + ((uint32_t)config->interface << PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT) | + PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN((uint32_t)config->fetchFormat.enableblock) | + PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16((uint32_t)config->fetchFormat.blockSize16) | + PXP_INPUT_FETCH_CTRL_CH0_CH_EN((uint32_t)config->channelEnable); + ulcReg = (((uint32_t)config->ulcY) << 16U) | (uint32_t)config->ulcX; + lrcReg = (((uint32_t)config->lrcY) << 16U) | (uint32_t)config->lrcX; + fetchSizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth); + shiftCtrlReg = PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP((uint32_t)config->activeBits) | + PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT((uint32_t)config->pixelFormat) | + PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN((uint32_t)config->expandEnable) | + PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass); + if (!config->shiftConfig.shiftBypass) + { + shiftOffsetReg = (uint32_t)config->shiftConfig.component0.offset | + ((uint32_t)(config->shiftConfig.component1.offset) << 8U) | + ((uint32_t)(config->shiftConfig.component2.offset) << 16U) | + ((uint32_t)(config->shiftConfig.component3.offset) << 24U); + shiftWidthReg = (uint32_t)config->shiftConfig.component0.width | + ((uint32_t)(config->shiftConfig.component1.width) << 4U) | + ((uint32_t)(config->shiftConfig.component2.width) << 8U) | + ((uint32_t)(config->shiftConfig.component3.width) << 12U); + } + + if (name == kPXP_FetchInput) + { + switch (channel) + { + case 0: + base->INPUT_FETCH_CTRL_CH0 = ctrlReg; + base->INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 = ulcReg; + base->INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 = lrcReg; + base->INPUT_FETCH_SIZE_CH0 = fetchSizeReg; + base->INPUT_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK) | + (uint32_t)config->pitchBytes; + base->INPUT_FETCH_SHIFT_CTRL_CH0 = shiftCtrlReg; + base->INPUT_FETCH_ADDR_0_CH0 = config->inputBaseAddr0; + base->INPUT_FETCH_ADDR_1_CH0 = config->inputBaseAddr1; + if (!config->shiftConfig.shiftBypass) + { + base->INPUT_FETCH_SHIFT_OFFSET_CH0 = shiftOffsetReg; + base->INPUT_FETCH_SHIFT_WIDTH_CH0 = shiftWidthReg; + } + break; + + case 1: + base->INPUT_FETCH_CTRL_CH1 = ctrlReg; + base->INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 = ulcReg; + base->INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 = lrcReg; + base->INPUT_FETCH_SIZE_CH1 = fetchSizeReg; + base->INPUT_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK) | + ((uint32_t)config->pitchBytes << 16U); + base->INPUT_FETCH_SHIFT_CTRL_CH1 = shiftCtrlReg; + base->INPUT_FETCH_ADDR_0_CH1 = config->inputBaseAddr0; + base->INPUT_FETCH_ADDR_1_CH1 = config->inputBaseAddr1; + if (!config->shiftConfig.shiftBypass) + { + base->INPUT_FETCH_SHIFT_OFFSET_CH1 = shiftOffsetReg; + base->INPUT_FETCH_SHIFT_WIDTH_CH1 = shiftWidthReg; + } + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_FETCH_CTRL_CH0 = ctrlReg; + base->DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 = ulcReg; + base->DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 = lrcReg; + base->DITHER_FETCH_SIZE_CH0 = fetchSizeReg; + base->DITHER_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK) | + (uint32_t)config->pitchBytes; + base->DITHER_FETCH_SHIFT_CTRL_CH0 = shiftCtrlReg; + base->DITHER_FETCH_ADDR_0_CH0 = config->inputBaseAddr0; + base->DITHER_FETCH_ADDR_1_CH0 = config->inputBaseAddr1; + if (!config->shiftConfig.shiftBypass) + { + base->DITHER_FETCH_SHIFT_OFFSET_CH0 = shiftOffsetReg; + base->DITHER_FETCH_SHIFT_WIDTH_CH0 = shiftWidthReg; + } + break; + + case 1: + base->DITHER_FETCH_CTRL_CH1 = ctrlReg; + base->DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 = ulcReg; + base->DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 = lrcReg; + base->DITHER_FETCH_SIZE_CH1 = fetchSizeReg; + base->DITHER_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK) | + ((uint32_t)config->pitchBytes << 16U); + base->DITHER_FETCH_SHIFT_CTRL_CH1 = shiftCtrlReg; + base->DITHER_FETCH_ADDR_0_CH1 = config->inputBaseAddr0; + base->DITHER_FETCH_ADDR_1_CH1 = config->inputBaseAddr1; + if (!config->shiftConfig.shiftBypass) + { + base->DITHER_FETCH_SHIFT_OFFSET_CH1 = shiftOffsetReg; + base->DITHER_FETCH_SHIFT_WIDTH_CH1 = shiftWidthReg; + } + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + return kStatus_Success; +} + +/*! + * brief Configures one channel of some block's store engine. + * + * Store engine is 32-bit input and 64-bit output per channel. + * note: If there is only one channel used for data input, channel 0 must be used rather than channel 1. + * + * param base PXP peripheral base address. + * param name the store engine belongs to which block. + * param channel channel number. + * param config pointer to the configuration structure. + * retval kStatus_Success Successfully configured the engine. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetStoreEngineConfig(PXP_Type *base, + pxp_store_engine_name_t name, + uint8_t channel, + const pxp_store_engine_config_t *config) +{ + assert(NULL != config); + /* Can only choose one plane for YUV422_2p for one channel output */ + if ((uint32_t)config->yuvMode == 0x3U) + { + return kStatus_InvalidArgument; + } + + /* Block mode cannot work in 64-bit mode or YUV422_2p mode */ + if ((config->storeFormat.enableblock == true) && + ((config->activeBits == kPXP_Active64Bits) || (config->yuvMode != kPXP_StoreYUVDisable))) + { + return kStatus_InvalidArgument; + } + + /* When block mode is disabled the interface array size can only be 1. TODO. The availiable fetch engine now are + only input&fetch that can only use handshake 1x1, no need to check */ + // if ((config->storeFormat.enableblock == false) && (config->arraySize != kPXP_StoreHandshake1x1)) + // { + // return kStatus_InvalidArgument; + // } + + uint32_t ctrlReg = 0U; + uint32_t shiftCtrlReg = 0U; + uint32_t sizeReg = 0U; + uint32_t dataShiftMaskRegAddr = 0U; + uint32_t dataShiftWidthRegAddr = 0U; + uint32_t flagShiftMaskRegAddr = 0U; + uint32_t flagShiftWidthRegAddr = 0U; + + ctrlReg = PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES((uint32_t)config->storeFormat.burstLength) | + PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN((uint32_t)config->useFixedData) | + PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL((uint32_t)config->packInSelect) | + ((uint32_t)config->interface << PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT) | + // PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM((uint32_t)config->arraySize) | + PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(0U) | + PXP_INPUT_STORE_CTRL_CH0_BLOCK_16((uint32_t)config->storeFormat.enableblock) | + PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN((uint32_t)config->storeFormat.blockSize16) | + PXP_INPUT_STORE_CTRL_CH0_CH_EN((uint32_t)config->channelEnable); + shiftCtrlReg = PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass) | + ((uint32_t)config->yuvMode << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT) | + PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP((uint32_t)config->activeBits); + sizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth); + + if (name == kPXP_StoreInput) + { + switch (channel) + { + case 0: + base->INPUT_STORE_CTRL_CH0 = ctrlReg; + base->INPUT_STORE_SIZE_CH0 = sizeReg; + base->INPUT_STORE_PITCH = (base->INPUT_STORE_PITCH & PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK) | + (uint32_t)(config->pitchBytes); + base->INPUT_STORE_SHIFT_CTRL_CH0 = shiftCtrlReg; + base->INPUT_STORE_ADDR_0_CH0 = config->outputBaseAddr0; + base->INPUT_STORE_ADDR_1_CH0 = config->outputBaseAddr1; + base->INPUT_STORE_FILL_DATA_CH0 = config->fixedData; + dataShiftMaskRegAddr = (uint32_t) & (base->INPUT_STORE_D_MASK0_H_CH0); + dataShiftWidthRegAddr = (uint32_t) & (base->INPUT_STORE_D_SHIFT_L_CH0); + flagShiftMaskRegAddr = (uint32_t) & (base->INPUT_STORE_F_MASK_L_CH0); + flagShiftWidthRegAddr = (uint32_t) & (base->INPUT_STORE_F_SHIFT_L_CH0); + break; + + case 1: + base->INPUT_STORE_CTRL_CH1 = ctrlReg; + base->INPUT_STORE_SIZE_CH1 = sizeReg; + base->INPUT_STORE_PITCH = (base->INPUT_STORE_PITCH & PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK) | + ((uint32_t)(config->pitchBytes) << 16U); + base->INPUT_STORE_SHIFT_CTRL_CH1 = shiftCtrlReg; + base->INPUT_STORE_ADDR_0_CH1 = config->outputBaseAddr0; + base->INPUT_STORE_ADDR_1_CH1 = config->outputBaseAddr1; + dataShiftMaskRegAddr = (uint32_t) & (base->INPUT_STORE_D_MASK0_H_CH0); + dataShiftWidthRegAddr = (uint32_t) & (base->INPUT_STORE_D_SHIFT_L_CH0); + flagShiftMaskRegAddr = (uint32_t) & (base->INPUT_STORE_F_MASK_L_CH0); + flagShiftWidthRegAddr = (uint32_t) & (base->INPUT_STORE_F_SHIFT_L_CH0); + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_STORE_CTRL_CH0 = ctrlReg; + base->DITHER_STORE_SIZE_CH0 = sizeReg; + base->DITHER_STORE_PITCH = (base->DITHER_STORE_PITCH & PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK) | + (uint32_t)(config->pitchBytes); + base->DITHER_STORE_SHIFT_CTRL_CH0 = shiftCtrlReg; + base->DITHER_STORE_ADDR_0_CH0 = config->outputBaseAddr0; + base->DITHER_STORE_ADDR_1_CH0 = config->outputBaseAddr1; + base->DITHER_STORE_FILL_DATA_CH0 = config->fixedData; + dataShiftMaskRegAddr = (uint32_t) & (base->DITHER_STORE_D_MASK0_H_CH0); + dataShiftWidthRegAddr = (uint32_t) & (base->DITHER_STORE_D_SHIFT_L_CH0); + flagShiftMaskRegAddr = (uint32_t) & (base->DITHER_STORE_F_MASK_L_CH0); + flagShiftWidthRegAddr = (uint32_t) & (base->DITHER_STORE_F_SHIFT_L_CH0); + break; + + case 1: + base->DITHER_STORE_CTRL_CH1 = ctrlReg; + base->DITHER_STORE_SIZE_CH1 = sizeReg; + base->DITHER_STORE_PITCH = (base->DITHER_STORE_PITCH & PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK) | + ((uint32_t)(config->pitchBytes) << 16U); + base->DITHER_STORE_SHIFT_CTRL_CH1 = shiftCtrlReg; + base->DITHER_STORE_ADDR_0_CH1 = config->outputBaseAddr0; + base->DITHER_STORE_ADDR_1_CH1 = config->outputBaseAddr1; + dataShiftMaskRegAddr = (uint32_t) & (base->DITHER_STORE_D_MASK0_H_CH0); + dataShiftWidthRegAddr = (uint32_t) & (base->DITHER_STORE_D_SHIFT_L_CH0); + flagShiftMaskRegAddr = (uint32_t) & (base->DITHER_STORE_F_MASK_L_CH0); + flagShiftWidthRegAddr = (uint32_t) & (base->DITHER_STORE_F_SHIFT_L_CH0); + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + + /* Shift configuration */ + if (!config->shiftConfig.shiftBypass) + { + uint8_t i; + uint32_t dataShiftMaskAddr = (uint32_t) & (config->shiftConfig.pDataShiftMask); + uint32_t dataShiftWidthAddr = (uint32_t) & (config->shiftConfig.pDataShiftWidth); + uint32_t flagShiftMaskAddr = (uint32_t) & (config->shiftConfig.pFlagShiftMask); + uint32_t flagShiftWidthAddr = (uint32_t) & (config->shiftConfig.pFlagShiftWidth); + + /* Configure data shift mask */ + for (i = 0U; i < 8U; i++) + { + *(uint32_t *)dataShiftMaskRegAddr = (uint32_t)(*(uint64_t *)dataShiftMaskAddr >> 32U); + dataShiftMaskRegAddr += 0x10U; + *(uint32_t *)dataShiftMaskRegAddr = (uint32_t)(*(uint64_t *)dataShiftMaskAddr); + dataShiftMaskRegAddr += 0x10U; + dataShiftMaskAddr += 8U; + } + + /* Configure data shift width, flag shift mask/width */ + for (i = 0U; i < 8U; i++) + { + *(uint8_t *)dataShiftWidthRegAddr = *(uint8_t *)dataShiftWidthAddr; + *(uint8_t *)flagShiftMaskRegAddr = *(uint8_t *)flagShiftMaskAddr; + *(uint8_t *)flagShiftWidthRegAddr = *(uint8_t *)flagShiftWidthAddr; + dataShiftWidthRegAddr++; + flagShiftMaskRegAddr++; + flagShiftWidthRegAddr++; + dataShiftWidthAddr++; + flagShiftMaskAddr++; + flagShiftWidthAddr++; + if (i == 3U) + { + dataShiftWidthRegAddr += 12U; + flagShiftMaskRegAddr += 12U; + flagShiftWidthRegAddr += 12U; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Configures the pre-dither CFA engine. + * + * param base PXP peripheral base address. + * param config pointer to the configuration structure. + * retval kStatus_Success Successfully configured the engine. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config) +{ + assert(NULL != config); + /* The CFA array cannot be larger than 15x15. */ + if ((config->arrayWidth > 15U) || (config->arrayHeight > 15U)) + { + return kStatus_InvalidArgument; + } + + uint32_t cfaArrayRegAddr = (uint32_t) & (base->CFA_ARRAY0); + uint32_t cfaValueAddr = (uint32_t) & (config->cfaValue); + uint8_t wordCount = 0U; /* How many 32-bit word does the CFA array need. */ + + base->CFA_CTRL = PXP_CFA_CTRL_CFA_ARRAY_HSIZE((uint32_t)config->arrayWidth) | + PXP_CFA_CTRL_CFA_ARRAY_VSIZE((uint32_t)config->arrayHeight) | + PXP_CFA_CTRL_CFA_IN_RGB444((uint32_t)config->pixelInFormat) | + PXP_CFA_CTRL_CFA_BYPASS((uint32_t)config->bypass); + base->CFA_SIZE = ((uint32_t)(config->totalWidth) << 16U) | (uint32_t)(config->totalHeight); + + /* Configure the CFA array value. */ + wordCount = (config->arrayWidth * config->arrayHeight * 2U + 32U) / 32U; + + for (uint8_t i = 0U; i < wordCount; i++) + { + *(uint32_t *)cfaArrayRegAddr = *(uint32_t *)cfaValueAddr; + cfaArrayRegAddr += 0x10U; + cfaValueAddr += 4U; + } + + return kStatus_Success; +} + +/*! + * brief Configures histogram engine. + * + * param base PXP peripheral base address. + * param num instance number. + * param config pointer to the configuration structure. + * retval kStatus_Success Successfully configured the engine. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config) +{ + assert(NULL != config); + /* The LUT value width can not be larger than 6. */ + if ((uint32_t)config->lutValueWidth > 6U) + { + return kStatus_InvalidArgument; + } + + uint32_t ctrlReg = 0U; + uint32_t maskReg = 0U; + + ctrlReg = PXP_HIST_A_CTRL_ENABLE((uint32_t)config->enable) | + PXP_HIST_A_CTRL_PIXEL_OFFSET((uint32_t)config->lutValueOffset) | + PXP_HIST_A_CTRL_PIXEL_WIDTH((uint32_t)config->lutValueWidth); + maskReg = PXP_HIST_A_MASK_MASK_EN((uint32_t)config->enableMask) | + PXP_HIST_A_MASK_MASK_MODE((uint32_t)config->condition) | + PXP_HIST_A_MASK_MASK_OFFSET((uint32_t)config->maskOffset) | + PXP_HIST_A_MASK_MASK_WIDTH((uint32_t)config->maskWidth) | + PXP_HIST_A_MASK_MASK_VALUE0((uint32_t)config->maskValue0) | + PXP_HIST_A_MASK_MASK_VALUE1((uint32_t)config->maskValue1); + + switch (num) + { + case 0: + base->HIST_A_CTRL = ctrlReg; + base->HIST_A_MASK = maskReg; + base->HIST_A_BUF_SIZE = ((uint32_t)(config->totalHeight) << 16U) | (uint32_t)config->totalWidth; + break; + + case 1: + base->HIST_B_CTRL = ctrlReg; + base->HIST_B_MASK = maskReg; + base->HIST_B_BUF_SIZE = ((uint32_t)(config->totalHeight) << 16U) | (uint32_t)config->totalWidth; + break; + + default: + /* Only 2 histogram instances are supported. */ + assert(false); + break; + } + + /* Only configure the histogram params when user choose to, otherwise use the registers' reset value as default. */ + if (config->pParamValue != NULL) + { + uint32_t paramRegAddr = (uint32_t) & (base->HIST2_PARAM); + uint32_t paramValueAddr = (uint32_t) & (config->pParamValue); + /* Configure the 2/4/8/16/32-level histogram params. */ + for (uint8_t i = 0; i < 62U; i++) + { + *(uint8_t *)paramRegAddr = *(uint8_t *)paramValueAddr; + paramValueAddr += 1U; + paramRegAddr++; + if ((i % 4U) == 1U) + { + paramRegAddr += 12U; + if (i == 1U) + { + paramRegAddr += 2U; + } + } + } + } + + return kStatus_Success; +} + +/*! + * brief Gets the results of histogram mask operation. + * + * param base PXP peripheral base address. + * param num instance number. + * param result pointer to the result structure. + */ +void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result) +{ + assert(NULL != result); + /* Initializes the result structure to zero. */ + (void)memset(result, 0, sizeof(*result)); + + switch (num) + { + case 0: + result->pixelCount = base->HIST_A_TOTAL_PIXEL; + result->minX = (uint16_t)base->HIST_A_ACTIVE_AREA_X; + result->maxX = (uint16_t)(base->HIST_A_ACTIVE_AREA_X >> 16U); + result->minY = (uint16_t)base->HIST_A_ACTIVE_AREA_Y; + result->maxY = (uint16_t)(base->HIST_A_ACTIVE_AREA_Y >> 16U); + result->lutlist = (uint64_t)base->HIST_A_RAW_STAT0 | ((uint64_t)base->HIST_A_RAW_STAT1 << 32U); + break; + + case 1: + result->pixelCount = base->HIST_B_TOTAL_PIXEL; + result->minX = (uint16_t)base->HIST_B_ACTIVE_AREA_X; + result->maxX = (uint16_t)(base->HIST_B_ACTIVE_AREA_X >> 16U); + result->minY = (uint16_t)base->HIST_B_ACTIVE_AREA_Y; + result->maxY = (uint16_t)(base->HIST_B_ACTIVE_AREA_Y >> 16U); + result->lutlist = (uint64_t)base->HIST_B_RAW_STAT0 | ((uint64_t)base->HIST_B_RAW_STAT1 << 32U); + break; + + default: + /* Only 2 histogram instances are supported. */ + assert(false); + break; + } +} + +/*! + * brief Initializes the WFE-A engine for waveform process. + * + * param base PXP peripheral base address. + * param ditherHandshake true to enable handshake mode with upstream dither store engine. + */ +void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake) +{ + /* FETCH engine configuration, user fetch buffer1 for Y4 data buffer and buffer2 for working buffer. */ + /* Enable buffer1&2 fetch. 2 bytes in each pixel for the buffer2. + Other default configurations: fetch data from external axi bus, normal(not hanshake or by pass) mode, burst + length 4, normal border pixels select(not sw reg mode), 1 line fetch, done IRQ disabled. */ + base->WFA_FETCH_CTRL = PXP_WFA_FETCH_CTRL_BF1_EN(1UL) | PXP_WFA_FETCH_CTRL_BF2_EN(1UL) | + PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1UL) | + PXP_WFA_FETCH_CTRL_BF1_HSK_MODE((uint32_t)ditherHandshake); + /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 0/3 */ + /* Other default configurations: x/y offset=0, positive offset. */ + base->WFA_ARRAY_PIXEL0_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3UL); + /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 4/7 */ + base->WFA_ARRAY_PIXEL1_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(4UL) | + PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(7UL); + /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 8/9 */ + base->WFA_ARRAY_PIXEL2_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(8UL) | + PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(9UL); + /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 10/15 */ + base->WFA_ARRAY_PIXEL3_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(10UL) | + PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(15UL); + /* Select pixel from bufer 1, set the right/left bit position on the original pixel as 4/7 */ + base->WFA_ARRAY_PIXEL4_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(4UL) | PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(7UL); + /* Software define flag0=1, other flags 1~15 =0 */ + base->WFA_ARRAY_REG2 = 1UL; + + /* STORE engine configuration */ + /* Channel 0 y4, channel 1 wb */ + /* Enable channel 0, store data to memory, select low 32 bit shift out data to pack, enable combine 2 channel. */ + /* Other default configurations: Arbitration disable(if using 2 channels, will output 2 axi bus sets), 8 bytes in a + burst, fill data mode disable, block mode disable. */ + base->WFE_A_STORE_CTRL_CH0 = PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1UL) | PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1UL) | + PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1UL) | + PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1UL); + /* Enable channel 1, store data to memory, select low 32 bit shift out data to pack, 16 bytes in a write burst. */ + base->WFE_A_STORE_CTRL_CH1 = PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL) | PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1UL) | + PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1UL) | PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(1UL); + /* 8 Bpp, disable YUV planes, disable shift bypass. */ + base->WFE_A_STORE_SHIFT_CTRL_CH0 = 0UL; + /* 16 Bpp, disable YUV planes, disable shift bypass. */ + base->WFE_A_STORE_SHIFT_CTRL_CH1 = PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1); + base->WFE_A_STORE_FILL_DATA_CH0 = 0UL; + /* 8 data masks, mask 0-7. Only use mask 0-4 */ + /* mask 0: 0xF << 32; mask 1: 0xF00 << 28; mask 2: 0x0 << 24; mask 3: 0x3F00'0000 << 18; mask 4: 0xF'0000'0000 >> 28 + */ + base->WFE_A_STORE_D_MASK0_H_CH0 = 0UL; + base->WFE_A_STORE_D_MASK0_L_CH0 = PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xfUL); /* fetch CP */ + base->WFE_A_STORE_D_MASK1_H_CH0 = 0UL; + base->WFE_A_STORE_D_MASK1_L_CH0 = PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00UL); /* fetch NP */ + base->WFE_A_STORE_D_MASK2_H_CH0 = 0UL; + base->WFE_A_STORE_D_MASK2_L_CH0 = 0UL; + base->WFE_A_STORE_D_MASK3_H_CH0 = 0UL; + base->WFE_A_STORE_D_MASK3_L_CH0 = PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000UL); /* fetch LUT */ + base->WFE_A_STORE_D_MASK4_H_CH0 = PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xfUL); + base->WFE_A_STORE_D_MASK4_L_CH0 = 0UL; /* fetch Y4 */ + base->WFE_A_STORE_D_SHIFT_L_CH0 = + PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1UL) | + PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1UL) | + PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1UL) | + PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1UL); + base->WFE_A_STORE_D_SHIFT_H_CH0 = PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28UL); + + /* 8 flag masks, mask 0-7. Only use mask 0-3 */ + /* mask 0: 0x1 << 1; mask 1: 0x2 >> 1; mask 2: 0x4 << 38; mask 3: 0x8 << 38 */ + /* Switch flag bit 0&1, bit 2&3 << 38 */ + base->WFE_A_STORE_F_MASK_H_CH0 = 0UL; + base->WFE_A_STORE_F_MASK_L_CH0 = + PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1UL) | PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2UL) | + PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4UL) | PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8UL); + base->WFE_A_STORE_F_SHIFT_H_CH0 = 0UL; + base->WFE_A_STORE_F_SHIFT_L_CH0 = + PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1UL) | + PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0UL) | + PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32UL + 6UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1UL) | + PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32UL + 6UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1UL); + + /* Enable and bypass the ALU process. */ + base->ALU_A_INST_ENTRY = 0UL; + base->ALU_A_PARAM = 0UL; + base->ALU_A_CONFIG = 0UL; + base->ALU_A_LUT_CONFIG = 0UL; + base->ALU_A_LUT_DATA0 = 0UL; + base->ALU_A_LUT_DATA1 = 0UL; + base->ALU_A_CTRL = PXP_ALU_A_CTRL_BYPASS(1UL) | PXP_ALU_A_CTRL_ENABLE(1UL); + + /* WFE A */ + base->WFE_A_STAGE1_MUX0 = 0x3F3F0303UL; + base->WFE_A_STAGE1_MUX1 = 0x0C00000CUL; + base->WFE_A_STAGE1_MUX2 = 0x01040000UL; + base->WFE_A_STAGE1_MUX3 = 0x0A0A0904UL; + base->WFE_A_STAGE1_MUX4 = 0x00000B0BUL; + base->WFE_A_STAGE2_MUX0 = 0x1800280EUL; + base->WFE_A_STAGE2_MUX1 = 0x00280E01UL; + base->WFE_A_STAGE2_MUX2 = 0x280E0118UL; + base->WFE_A_STAGE2_MUX3 = 0x00011800UL; + base->WFE_A_STAGE2_MUX4 = 0UL; + base->WFE_A_STAGE2_MUX5 = 0x1800280EUL; + base->WFE_A_STAGE2_MUX6 = 0x00280E01UL; + base->WFE_A_STAGE2_MUX7 = 0x1A0E0118UL; + base->WFE_A_STAGE2_MUX8 = 0x1B012911UL; + base->WFE_A_STAGE2_MUX9 = 0x00002911UL; + base->WFE_A_STAGE2_MUX10 = 0UL; + base->WFE_A_STAGE2_MUX11 = 0UL; + base->WFE_A_STAGE2_MUX12 = 0UL; + base->WFE_A_STAGE3_MUX0 = 0x07060504UL; + base->WFE_A_STAGE3_MUX1 = 0x3F3F3F08UL; + base->WFE_A_STAGE3_MUX2 = 0x03020100UL; + base->WFE_A_STAGE3_MUX3 = 0x3F3F3F3FUL; + + /* WFE_A_STG1_8X1_OUT0_0/1 is used to store LUT occupation status */ + /* Set LUT64-255 to occupied since we only have 64 LUTs in EPDC */ + base->WFE_A_STG1_8X1_OUT0_2 = 0xFFFFFFFFUL; + base->WFE_A_STG1_8X1_OUT0_3 = 0xFFFFFFFFUL; + base->WFE_A_STG1_8X1_OUT0_4 = 0xFFFFFFFFUL; + base->WFE_A_STG1_8X1_OUT0_5 = 0xFFFFFFFFUL; + base->WFE_A_STG1_8X1_OUT0_6 = 0xFFFFFFFFUL; + base->WFE_A_STG1_8X1_OUT0_7 = 0xFFFFFFFFUL; + /* OUT1.2.3 LUT0-255 */ + base->WFE_A_STG1_8X1_OUT1_0 = 0UL; + base->WFE_A_STG1_8X1_OUT1_1 = 0UL; + base->WFE_A_STG1_8X1_OUT1_2 = 0UL; + base->WFE_A_STG1_8X1_OUT1_3 = 0UL; + base->WFE_A_STG1_8X1_OUT1_4 = 0UL; + base->WFE_A_STG1_8X1_OUT1_5 = 0UL; + base->WFE_A_STG1_8X1_OUT1_6 = 0UL; + base->WFE_A_STG1_8X1_OUT1_7 = 0UL; + base->WFE_A_STG1_8X1_OUT2_0 = 0UL; + base->WFE_A_STG1_8X1_OUT2_1 = 0UL; + base->WFE_A_STG1_8X1_OUT2_2 = 0UL; + base->WFE_A_STG1_8X1_OUT2_3 = 0UL; + base->WFE_A_STG1_8X1_OUT2_4 = 0UL; + base->WFE_A_STG1_8X1_OUT2_5 = 0UL; + base->WFE_A_STG1_8X1_OUT2_6 = 0UL; + base->WFE_A_STG1_8X1_OUT2_7 = 0UL; + base->WFE_A_STG1_8X1_OUT3_0 = 0UL; + base->WFE_A_STG1_8X1_OUT3_1 = 0UL; + base->WFE_A_STG1_8X1_OUT3_2 = 0UL; + base->WFE_A_STG1_8X1_OUT3_3 = 0UL; + base->WFE_A_STG1_8X1_OUT3_4 = 0UL; + base->WFE_A_STG1_8X1_OUT3_5 = 0UL; + base->WFE_A_STG1_8X1_OUT3_6 = 0UL; + base->WFE_A_STG1_8X1_OUT3_7 = 0UL; + /* LUTOUT0-31 for OUT0-3. + The 5x6 LUT output value for input value n. This output value determines which input to select (flag, data). */ + base->WFE_A_STG2_5X6_OUT0_0 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_1 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_2 = 0x04050505UL; + base->WFE_A_STG2_5X6_OUT0_3 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_4 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_5 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_6 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT0_7 = 0x04040404UL; + base->WFE_A_STG2_5X6_OUT1_0 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_1 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_2 = 0x05080808UL; + base->WFE_A_STG2_5X6_OUT1_3 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_4 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_5 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_6 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT1_7 = 0x05050505UL; + base->WFE_A_STG2_5X6_OUT2_0 = 0x07070707UL; + base->WFE_A_STG2_5X6_OUT2_1 = 0x07070707UL; + base->WFE_A_STG2_5X6_OUT2_2 = 0x070C0C0CUL; + base->WFE_A_STG2_5X6_OUT2_3 = 0x07070707UL; + base->WFE_A_STG2_5X6_OUT2_4 = 0X0F0F0F0FUL; + base->WFE_A_STG2_5X6_OUT2_5 = 0X0F0F0F0FUL; + base->WFE_A_STG2_5X6_OUT2_6 = 0X0F0F0F0FUL; + base->WFE_A_STG2_5X6_OUT2_7 = 0X0F0F0F0FUL; + base->WFE_A_STG2_5X6_OUT3_0 = 0UL; + base->WFE_A_STG2_5X6_OUT3_1 = 0UL; + base->WFE_A_STG2_5X6_OUT3_2 = 0UL; + base->WFE_A_STG2_5X6_OUT3_3 = 0UL; + base->WFE_A_STG2_5X6_OUT3_4 = 0UL; + base->WFE_A_STG2_5X6_OUT3_5 = 0UL; + base->WFE_A_STG2_5X6_OUT3_6 = 0UL; + base->WFE_A_STG2_5X6_OUT3_7 = 0UL; + /* MASK0-3, 5 bits each mask. + Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */ + base->WFE_A_STAGE2_5X6_MASKS_0 = 0x001F1F1FUL; + /* MUXADDR 0-3, 6 bits each. + Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT.*/ + base->WFE_A_STAGE2_5X6_ADDR_0 = 0x3f030100UL; + /* Flag of LUTOUT0-31 for OUT0-3. + The 5x1 LUT output value for input value n. This output value results in a flag that is added to the flag array. + */ + base->WFE_A_STG2_5X1_OUT0 = 0x00000700UL; + base->WFE_A_STG2_5X1_OUT1 = 0x00007000UL; + base->WFE_A_STG2_5X1_OUT2 = 0x0000A000UL; + base->WFE_A_STG2_5X1_OUT3 = 0x000000C0UL; + /* MASK0-3, 5 bits each mask. + Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ + base->WFE_A_STG2_5X1_MASKS = 0x071F1F1FUL; +} + +/*! + * brief Configure the WFE-A engine + * + * param base PXP peripheral base address. + * param config pointer to the configuration structure. + */ +void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config) +{ + /* Fetch */ + base->WFA_FETCH_BUF1_ADDR = config->y4Addr; + base->WFA_FETCH_BUF1_PITCH = config->updatePitch; + base->WFA_FETCH_BUF1_SIZE = PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight - 1UL) | + PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH((uint32_t)config->updateWidth - 1UL); + base->WFA_FETCH_BUF1_CORD = 0UL; + base->WFA_FETCH_BUF2_ADDR = config->wbAddr; + base->WFA_FETCH_BUF2_PITCH = (uint32_t)config->resX * 2U; /* 2 bytes per pixel */ + base->WFA_FETCH_BUF2_SIZE = PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight - 1UL) | + PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH((uint32_t)config->updateWidth - 1UL); + base->WFA_FETCH_BUF2_CORD = + PXP_WFA_FETCH_BUF2_CORD_YCORD((uint32_t)config->ulcY) | PXP_WFA_FETCH_BUF2_CORD_XCORD((uint32_t)config->ulcX); + + /* Store */ + base->WFE_A_STORE_SIZE_CH0 = PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->updateWidth - 1UL) | + PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->updateHeight - 1UL); + base->WFE_A_STORE_SIZE_CH1 = PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->updateWidth - 1UL) | + PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->updateHeight - 1UL); + /* Channel 1: 2 byte per pixel. */ + base->WFE_A_STORE_PITCH = PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH((uint32_t)config->resX) | + PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH((uint32_t)config->resX * 2U); + base->WFE_A_STORE_ADDR_0_CH0 = PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(config->y4cAddr); + base->WFE_A_STORE_ADDR_1_CH0 = 0U; + /* Channel 1: 2 bytes per pixel. */ + base->WFE_A_STORE_ADDR_0_CH1 = PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + (uint32_t)config->wbAddr + ((uint32_t)config->ulcX + (uint32_t)config->ulcY * (uint32_t)config->resX) * 2UL); + base->WFE_A_STORE_ADDR_1_CH1 = 0U; + + /* ALU */ + base->ALU_A_BUF_SIZE = PXP_ALU_A_BUF_SIZE_BUF_WIDTH((uint32_t)config->updateWidth) | + PXP_ALU_A_BUF_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight); + + /* WFE */ + /* Height and width of the updete region */ + base->WFE_A_DIMENSIONS = + PXP_WFE_A_DIMENSIONS_WIDTH(config->updateWidth) | PXP_WFE_A_DIMENSIONS_HEIGHT(config->updateHeight); + /* The distance from the frame origin to the update region origin in the X/Y direction. */ + base->WFE_A_OFFSET = PXP_WFE_A_OFFSET_X_OFFSET(config->ulcX) | PXP_WFE_A_OFFSET_Y_OFFSET(config->ulcY); + /* val3,val2=0, val1=F, val0=lutNum */ + base->WFE_A_SW_DATA_REGS = (config->lutNum & 0x000000FFUL) | 0x00000F00UL; + /* val3,val2=0, val1=0(disable reagl/-d), val0=partial(1)full(0) */ + base->WFE_A_SW_FLAG_REGS = ((uint32_t)(!config->fullUpdateEnable) | (0U << 1U)); + /* Enable and reset WFE-A state. Disable register of ALU inside waveform as default. */ + base->WFE_A_CTRL = PXP_WFE_A_CTRL_ENABLE(1UL) | PXP_WFE_A_CTRL_SW_RESET(1UL); + + if (config->alphaEnable) + { + base->WFA_ARRAY_FLAG0_MASK = 0U; + } + else + { + base->WFA_ARRAY_FLAG0_MASK = PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2UL); + } + + /* disable CH1 when only doing detection */ + if (config->detectionOnly) + { + base->WFE_A_STORE_CTRL_CH1 &= ~PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL); + } + else + { + base->WFE_A_STORE_CTRL_CH1 |= PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL); + } + /* Enable engine */ + base->CTRL_SET = PXP_CTRL_ENABLE_WFE_A(1UL); +} +#endif /* FSL_FEATURE_PXP_V3 */ + +#if PXP_USE_PATH +/*! + * brief Sets the path for one of the MUX + * + * param base PXP peripheral base address. + * param path the path configuration for one of the mux. + */ +void PXP_SetPath(PXP_Type *base, pxp_path_t path) +{ + volatile uint32_t *pathReg; + uint32_t mux = PXP_GET_MUX_FROM_PATH((uint32_t)path); + uint32_t sel = PXP_GET_SEL_FROM_PATH((uint32_t)path); + + if (mux > 15U) + { + pathReg = &(base->DATA_PATH_CTRL1); + mux -= 15U; + } + else + { + pathReg = &(base->DATA_PATH_CTRL0); + } + + /* Convert mux to the register shift. */ + mux *= 2U; + *pathReg = (*pathReg & ~(3UL << mux)) | (sel << mux); +} +#endif /* PXP_USE_PATH */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.h index e34a9daf05..a29aace158 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2021 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * @@ -42,13 +42,13 @@ ******************************************************************************/ /* PXP global LUT table is 16K. */ -#define PXP_LUT_TABLE_BYTE (16 * 1024) +#define PXP_LUT_TABLE_BYTE (16UL * 1024UL) /* Intenral memory for LUT, the size is 256 bytes. */ #define PXP_INTERNAL_RAM_LUT_BYTE (256) /*! @name Driver version */ /*@{*/ -#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*@}*/ /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */ @@ -58,15 +58,62 @@ #define PXP_SHARE_ROTATE 0 #endif +/* This macto indicates whether PXP needs mux the process path. */ +#if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_USE_PATH 1 +#else +#define PXP_USE_PATH 0 +#endif + +#if PXP_USE_PATH +#define PXP_PATH(mux, sel) (((mux) << 8U) | (sel)) +#define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U) +#define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U) +#endif /* PXP_USE_PATH */ + /*! @brief PXP interrupts to enable. */ enum _pxp_interrupt_enable { - kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set - by @ref PXP_SetNextCommand has been loaded. */ - kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. */ + kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. bit 1 */ + kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set by @ref + PXP_SetNextCommand has been loaded. bit 2 */ #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) - kPXP_LutDmaLoadInterruptEnable = PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. */ + kPXP_LutDmaLoadInterruptEnable = + PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. bit 3 */ #endif +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + kPXP_CompressDoneInterruptEnable = + PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U, /*!< Compress done interrupt enable. bit 15 */ + kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK + << 16U, /*!< Input fetch channel 0 completed. bit 16 */ + kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK + << 16U, /*!< Input fetch channel 1 completed. bit 17 */ + kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK + << 16U, /*!< Input store channel 0 completed. bit 18 */ + kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK + << 16U, /*!< Input store channel 1 completed. bit 19 */ + kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK + << 16U, /*!< Dither fetch channel 0 completed. bit 20 */ + kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK + << 16U, /*!< Dither fetch channel 1 completed. bit 21 */ + kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK + << 16U, /*!< Dither store channle 0 completed. bit 22 */ + kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK + << 16U, /*!< Dither store channle 1 completed. bit 23 */ + kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK + << 16U, /*!< WFE-A store channel 0 completed. bit 24 */ + kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK + << 16U, /*!< WFE-A store channel 1 completed. bit 25 */ + kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK + << 16U, /*!< WFE-B store channel 0 completed. bit 26 */ + kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK + << 16U, /*!< WFE-B store channel 1 completed. bit 27 */ + kPXP_InputStoreInterruptEnable = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U, /*!< Input store completed. bit 28 */ + kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK + << 16U, /*!< Dither store completed. bit 29 */ + kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U, /*!< WFE-A store completed. bit 30 */ + kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U, /*!< WFE-B store completed. bit 31 */ +#endif /* FSL_FEATURE_PXP_V3 */ }; /*! @@ -76,24 +123,149 @@ enum _pxp_interrupt_enable */ enum _pxp_flags { - kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand - has been loaded, could set new command. */ - kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. */ + kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. bit 0 */ + kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error and processing + has been terminated. bit 1*/ + kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error and processing has + been terminated. bit 2 */ + kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand has been loaded, + could set new command. bit 3 */ #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) - kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. */ + kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. bit 8 */ #endif - kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error - and processing has been terminated. */ - kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error - and processing has been terminated. */ #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) - kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error - and processing has been terminated. */ - kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error - and processing has been terminated. */ + kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error and processing + has been terminated. bit 9 */ + kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error and processing has + been terminated. bit 10 */ #endif +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + kPXP_CompressDoneFlag = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U, /*!< Compress done. bit 15 */ + kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK + << 16U, /*!< Input fetch channel 0 completed. bit 16 */ + kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK + << 16U, /*!< Input fetch channel 1 completed. bit 17 */ + kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK + << 16U, /*!< Input store channel 0 completed. bit 18 */ + kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK + << 16U, /*!< Input store channel 1 completed. bit 19 */ + kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK + << 16U, /*!< Dither fetch channel 0 completed. bit 20 */ + kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK + << 16U, /*!< Dither fetch channel 1 completed. bit 21 */ + kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK + << 16U, /*!< Dither store channel 0 completed. bit 22 */ + kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK + << 16U, /*!< Dither store channel 1 completed. bit 23 */ + kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK + << 16U, /*!< WFE-A store channel 0 completed. bit 24 */ + kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK + << 16U, /*!< WFE-A store channel 1 completed. bit 25 */ + kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK + << 16U, /*!< WFE-B store channel 0 completed. bit 26 */ + kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK + << 16U, /*!< WFE-B store channel 1 completed. bit 27 */ + kPXP_InputStoreCompleteFlag = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U, /*!< Input store completed. bit 28 */ + kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U, /*!< Dither store completed. bit 29 */ + kPXP_WfeaStoreCompleteFlag = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U, /*!< WFE-A store completed. bit 30 */ + kPXP_WfebStoreCompleteFlag = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U, /*!< WFE-B store completed. bit 31 */ +#endif /* FSL_FEATURE_PXP_V3 */ }; +#if PXP_USE_PATH +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +typedef enum _pxp_path +{ + kPXP_Mux0SelectProcessSurfaceEngine = PXP_PATH(0U, 0U), /*!< MUX0 select Process Surface engine. */ + kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U), /*!< MUX0 select input Fetch engine channel 0. */ + kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U), /*!< MUX0 select input Fetch engine channel 1. */ + kPXP_Mux0SelectNone = PXP_PATH(0U, 3U), /*!< MUX0 select no output. */ + kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U), /*!< MUX1 select input Fetch engine channel 0. */ + kPXP_Mux1SelectRotation1Engine = PXP_PATH(1U, 1U), /*!< MUX1 select Rotation1 engine output. */ + kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */ + kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U), /*!< MUX2 select input Fetch engine channel 1. */ + kPXP_Mux2SelectRotation1Engine = PXP_PATH(2U, 1U), /*!< MUX2 select Rotation1 engine output. */ + kPXP_Mux2SelectNone = PXP_PATH(2U, 2U), /*!< MUX2 select no output. */ + kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of CSC1 engine. */ + kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of Rotation1 engine. */ + kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */ + kPXP_Mux5SelectMux1 = PXP_PATH(5U, 0U), /*!< MUX5 select output of MUX1. */ + kPXP_Mux5SelectAlphaBlending1 = PXP_PATH(5U, 1U), /*!< MUX5 select output of alpha blending / color key 1. */ + kPXP_Mux5SelectNone = PXP_PATH(5U, 2U), /*!< MUX5 select no output. */ + kPXP_Mux6SelectAlphaBlending1 = PXP_PATH(6U, 0U), /*!< MUX6 select output of alpha blending / color key 1. */ + kPXP_Mux6SelectAlphaBlending0 = PXP_PATH(6U, 1U), /*!< MUX6 select output of alpha blending / color key 0. */ + kPXP_Mux6SelectNone = PXP_PATH(6U, 2U), /*!< MUX6 select no output. */ + kPXP_Mux7SelectMux5 = PXP_PATH(7U, 0U), /*!< MUX7 select output of MUX5. */ + kPXP_Mux7SelectCsc2Engine = PXP_PATH(7U, 1U), /*!< MUX7 select output of CSC2 engine. */ + kPXP_Mux7SelectNone = PXP_PATH(7U, 2U), /*!< MUX7 select no output. */ + kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */ + kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */ + kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */ + kPXP_Mux9SelectMux7 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX7. */ + kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */ + kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */ + kPXP_Mux10SelectMux7 = PXP_PATH(10U, 0U), /*!< MUX10 select output of MUX7. */ + kPXP_Mux10SelectLut = PXP_PATH(10U, 1U), /*!< MUX10 select output of LUT. */ + kPXP_Mux10SelectNone = PXP_PATH(10U, 2U), /*!< MUX10 select no output. */ + kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */ + kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */ + kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */ + kPXP_Mux12SelectMux10 = PXP_PATH(12U, 0U), /*!< MUX12 select output of MUX10. */ + kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */ + kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */ + kPXP_Mux13SelectNone = PXP_PATH(13U, 0U), /*!< MUX13 select no output. */ + kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U), /*!< MUX13 select input Fetch engine channel 1. */ + kPXP_Mux14SelectRotation0Engine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Rotation0 engine. */ + kPXP_Mux14SelectMux11 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX11. */ + kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */ + kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U), /*!< MUX15 select input Fetch engine channel 0. */ + kPXP_Mux15SelectMux10 = PXP_PATH(15U, 1U), /*!< MUX15 select output of MUX10. */ + kPXP_Mux15SelectNone = PXP_PATH(15U, 2U), /*!< MUX15 select no output. */ + kPXP_Mux16SelectAluA = PXP_PATH(16U, 0U), /*!< MUX16 select output of ALU A. */ + kPXP_Mux16SelectOutput = PXP_PATH(16U, 1U), /*!< MUX16 select output of legacy output. */ + kPXP_Mux16SelectAluB = PXP_PATH(16U, 2U), /*!< MUX16 select output of ALU B. */ + kPXP_Mux16SelectNone = PXP_PATH(16U, 3U), /*!< MUX16 select no output. */ + kPXP_Mux17SelectAluA = PXP_PATH(17U, 0U), /*!< MUX17 select output of ALU A. */ + kPXP_Mux17SelectAluB = PXP_PATH(17U, 1U), /*!< MUX17 select output of ALU B. */ + kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */ +} pxp_path_t; +#else +typedef enum _pxp_path +{ + kPXP_Mux0SelectFetchDataArray = PXP_PATH(0U, 0U), /*!< MUX0 select Fetch Data Array. */ + kPXP_Mux0SelectAlu = PXP_PATH(0U, 1U), /*!< MUX0 select output of ALU. */ + kPXP_Mux0SelectNone = PXP_PATH(0U, 2U), /*!< MUX0 select no output. */ + kPXP_Mux1SelectLut = PXP_PATH(1U, 0U), /*!< MUX1 select output of LUT. */ + kPXP_Mux1SelectMux0 = PXP_PATH(1U, 1U), /*!< MUX1 select output of MUX0. */ + kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */ + kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of Rotation1 engine. */ + kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of CSC1 engine. */ + kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */ + kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */ + kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */ + kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */ + kPXP_Mux9SelectMux0 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX0. */ + kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */ + kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */ + kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */ + kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */ + kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */ + kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U), /*!< MUX12 select output of Rotation0 engine. */ + kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */ + kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */ + kPXP_Mux14SelectDitherEngine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Dither engine. */ + kPXP_Mux14SelectMux12 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX12. */ + kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */ + kPXP_Mux16SelectOutputBuffer = PXP_PATH(16U, 0U), /*!< MUX16 select output of output buffer. */ + kPXP_Mux16SelectStoreEngine = PXP_PATH(16U, 1U), /*!< MUX16 select output of store engine. */ + kPXP_Mux16SelectNone = PXP_PATH(16U, 2U), /*!< MUX16 select no output. */ + kPXP_Mux17SelectOutputBuffer = PXP_PATH(17U, 0U), /*!< MUX17 select output of output buffer. */ + kPXP_Mux17SelectStoreEngine = PXP_PATH(17U, 1U), /*!< MUX17 select output of store engine. */ + kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */ +} pxp_path_t; +#endif /* FSL_FEATURE_PXP_V3 */ +#endif /* PXP_USE_PATH */ + /*! @brief PXP output flip mode. */ typedef enum _pxp_flip_mode { @@ -272,6 +444,18 @@ typedef struct _pxp_as_blend_config pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */ } pxp_as_blend_config_t; +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief PXP secondary alpha surface blending engine configuration. + */ +typedef struct _pxp_as_blend_secondary_config +{ + bool invertAlpha; /*!< Set true to invert the alpha. */ + bool ropEnable; /*!< Enable rop mode. */ + pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when ropEnable is true. */ +} pxp_as_blend_secondary_config_t; +#endif /* FSL_FEATURE_PXP_V3 */ + /*! @brief PXP process block size. */ typedef enum _pxp_block_size { @@ -372,14 +556,25 @@ typedef enum _pxp_ram kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */ kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */ kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */ +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + kPXP_RamDither0Err0 = 1U, /*!< Dither 0 ERR0 memory. */ + kPXP_RamDither0Err1 = 2U, /*!< Dither 0 ERR1 memory. */ + kPXP_RamAluA = 5U, /*!< ALU A instr memory. */ + kPXP_RamAluB = 6U, /*!< ALU B instr memory. */ + kPXP_WfeAFetch = 7U, /*!< WFE-A fetch memory. */ + kPXP_WfeBFetch = 8U, /*!< WFE-B fetch memory. */ +#endif /* FSL_FEATURE_PXP_V3 */ } pxp_ram_t; /*! @brief PXP dither mode. */ enum _pxp_dither_mode { - kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */ - kPXP_DitherOrdered = 3U, /*!< Ordered dither. */ - kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */ + kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */ + kPXP_DitherFloydSteinberg = 1U, /*!< Floyd-Steinberg. For dither engine 0 only. */ + kPXP_DitherAtkinson = 2U, /*!< Atkinson. For dither engine 0 only. */ + kPXP_DitherOrdered = 3U, /*!< Ordered dither. */ + kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */ + kPXP_DitherSierra = 5U, /*!< Sierra. For dither engine 0 only. */ }; /*! @brief PXP dither LUT mode. */ @@ -394,7 +589,8 @@ enum _pxp_dither_lut_mode /*! @brief PXP dither matrix size. */ enum _pxp_dither_matrix_size { - kPXP_DitherMatrix8 = 1, /*!< The dither index matrix is 8x8. */ + kPXP_DitherMatrix4 = 0, /*!< The dither index matrix is 4x4. */ + kPXP_DitherMatrix8, /*!< The dither index matrix is 8x8. */ kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */ }; @@ -529,6 +725,347 @@ typedef struct _pxp_pic_copy_config pxp_as_pixel_format_t pixelFormat; /*!< Buffer pixel format. */ } pxp_pic_copy_config_t; +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + +/*! + * @brief PXP process engine enumeration + */ +typedef enum _pxp_process_engine_name +{ + kPXP_PsAsOutEngine = PXP_CTRL_ENABLE_PS_AS_OUT_MASK, + kPXP_DitherEngine = PXP_CTRL_ENABLE_DITHER_MASK, + kPXP_WfeaEngine = PXP_CTRL_ENABLE_WFE_A_MASK, + kPXP_WfebEngine = PXP_CTRL_ENABLE_WFE_B_MASK, + kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK, + kPXP_Alpha1Engine = PXP_CTRL_ENABLE_ALPHA_B_MASK, + kPXP_Csc2Engine = PXP_CTRL_ENABLE_CSC2_MASK, + kPXP_LutEngine = PXP_CTRL_ENABLE_LUT_MASK, + kPXP_Rotate0Engine = PXP_CTRL_ENABLE_ROTATE0_MASK, + kPXP_Rotate1Engine = PXP_CTRL_ENABLE_ROTATE1_MASK, +} pxp_process_engine_name_t; + +/* Fetch engine configuration. */ +/*! + * @brief PXP fetch engine enumeration + * + * There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, + * whose registers are reserved from developer. + */ +typedef enum _pxp_fetch_engine_name +{ + kPXP_FetchInput, + kPXP_FetchDither, +} pxp_fetch_engine_name_t; + +/*! @brief PXP fetch engine interface mode with the upstream store engine. */ +typedef enum _pxp_fetch_interface_mode +{ + kPXP_FetchModeNormal = 0U, + kPXP_FetchModeHandshake = 0x1U, + kPXP_FetchModeBypass = 0x2U, +} pxp_fetch_interface_mode_t; + +/*! @brief PXP fetch/store engine burst length for scanline mode. */ +typedef enum _pxp_scanline_burst +{ + kPXP_Scanline8bytes, + kPXP_Scanline16bytes, + kPXP_Scanline32bytes, + kPXP_Scanline64bytes, +} pxp_scanline_burst_t; + +/*! @brief PXP fetch engine block configuration. */ +typedef struct _pxp_block_format_config +{ + bool + enableblock; /*!< Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or + flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If + LUT processing is in the path between the fetch and store engind, block mode must be enabled. */ + bool blockSize16; /*!< Enable to use 16*16 block, otherwise it will be 8*8 block. */ + pxp_scanline_burst_t burstLength; /*!< When using scanline mode, configure this for burst length. */ +} pxp_block_config_t; + +/*! + * @brief PXP fetch/store engine input/output active bits configuration. + * + * Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input + * mode. And expand configuration will have no effect. + */ +typedef enum _pxp_activeBits +{ + kPXP_Active8Bits = 0x0, + kPXP_Active16Bits = 0x1, + kPXP_Active32Bits = 0x2, + kPXP_Active64Bits = 0x3, +} pxp_active_bits_t; + +/*! @brief PXP fetch engine output word order when using 2 channels for 64-bit mode. */ +typedef enum _pxp_fetch_output_word_order +{ + kPXP_FetchOutputChannel1channel0 = 0x0, /*!< In 64bit mode, channel 1 output high byte. */ + kPXP_FetchOutputChannel0channel1 = 0x1, /*!< In 64bit mode, channel 0 output high byte. */ +} pxp_fetch_output_word_order_t; + +/*! + * @brief PXP fetch engine shift component configuration. + * + * Fetch engine can divded each word into 4 components and shift them. + */ +typedef struct _pxp_fetch_shift_component +{ + uint8_t offset; + uint8_t width; +} pxp_fetch_shift_component_t; + +/*! + * @brief PXP fetch engine shift configuration. + * + * Fetch engine can divded each word into 4 components and shift them. + * For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, + * OFFSET3=24, WIDTH0/1/2/3=8 + */ +typedef struct _pxp_fetch_shift_config +{ + bool shiftBypass; /* Bypass the shift */ + pxp_fetch_shift_component_t component0; + pxp_fetch_shift_component_t component1; + pxp_fetch_shift_component_t component2; + pxp_fetch_shift_component_t component3; +} pxp_fetch_shift_config_t; + +/*! @brief PXP fetch engine input pixel format. */ +typedef enum _pxp_fetch_pixel_format +{ + kPXP_FetchFormatRGB565 = 0x0, + kPXP_FetchFormatRGB555 = 0x1, + kPXP_FetchFormatARGB1555 = 0x2, + kPXP_FetchFormatRGB444 = 0x3, + kPXP_FetchFormatARGB4444 = 0x4, + kPXP_FetchFormatYUYVorYVYU = 0x5, + kPXP_FetchFormatUYVYorVYUY = 0x6, + kPXP_FetchFormatYUV422_2P = 0x7, +} pxp_fetch_pixel_format_t; + +/*! @brief PXP fetch engine configuration for one of the channel. */ +typedef struct _pxp_fetch_engine_config +{ + bool channelEnable; /*!< Enable channel. */ + /* Address configuration */ + uint32_t inputBaseAddr0; /*!< The input base address. Used for Y plane input when pixel format is YUV422_2p. */ + uint32_t inputBaseAddr1; /*!< Must configure this for UV plane when input pixel format is YUV422_2p. */ + /* Size configuration */ + uint16_t totalHeight; /*!< Total height for the actual fetch size. */ + uint16_t totalWidth; /*!< Total width for the actual fetch size. */ + uint16_t pitchBytes; /*!< Channel input pitch */ + uint16_t + ulcX; /*!< X coordinate of upper left coordinate in pixels of the active surface of the total input memory */ + uint16_t + ulcY; /*!< Y coordinate of upper left coordinate in pixels of the active surface of the total input memory */ + uint16_t + lrcX; /*!< X coordinate of Lower right coordinate in pixels of the active surface of the total input memory */ + uint16_t + lrcY; /*!< Y coordinate of Lower right coordinate in pixels of the active surface of the total input memory */ + /* Interface configuration */ + pxp_fetch_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake */ + /* Pixel configuration */ + pxp_active_bits_t activeBits; /*!< Input active bits. */ + pxp_fetch_pixel_format_t pixelFormat; /*!< Input pixel fetch format */ + bool expandEnable; /*!< If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at + the output. */ + /* Fetch format configuration */ + pxp_flip_mode_t flipMode; /*!< Flip the fetched input. */ + pxp_rotate_degree_t rotateDegree; /*!< Rotate the fetched input. */ + pxp_block_config_t + fetchFormat; /*!< Block mode configuration. Make sure to enable block if rotate or flip mode is enabled. */ + /* Output configuration. */ + pxp_fetch_shift_config_t shiftConfig; /*!< Shift operation configuration. */ + pxp_fetch_output_word_order_t wordOrder; /*!< Output word order when using 2 channels for 64-bit mode. */ +} pxp_fetch_engine_config_t; + +/* Store engine configuration. */ + +/*! + * @brief PXP store engine enumeration + * + * There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, + * whose registers are reserved from developer. + */ +typedef enum _pxp_store_engine_name +{ + kPXP_StoreInput, + kPXP_StoreDither, +} pxp_store_engine_name_t; + +/*! @brief PXP store engine interface mode with the downstream fetch engine. */ +typedef enum _pxp_store_interface_mode +{ + kPXP_StoreModeBypass = 0x20U, + kPXP_StoreModeNormal = 0x40U, + kPXP_StoreModeHandshake = 0x43U, + kPXP_StoreModeDual = 0x60U, /*!< Store engine outputs data directly to downstream fetch engine(Bypass) but also + storing it to memory at the same time. */ +} pxp_store_interface_mode_t; + +/*! @brief PXP store engine YUV output mode. */ +typedef enum _pxp_store_yuv_mode +{ + kPXP_StoreYUVDisable = 0U, /*!< Do not output YUV pixel format. */ + kPXP_StoreYUVPlane1 = + 0x1U, /*!< Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel + component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}. */ + kPXP_StoreYUVPlane2 = + 0x2U, /*!< Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel + component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}. */ +} pxp_store_yuv_mode_t; + +/*! @brief Shift configuration for PXP store engine. */ +typedef struct _pxp_store_shift_config +{ + /* Data/Flag shift */ + bool shiftBypass; /*!< Bypass the data shift */ + uint64_t *pDataShiftMask; /*!< Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then + shifted according to width. */ + uint8_t *pDataShiftWidth; /*!< Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for + shift width. */ + uint8_t *pFlagShiftMask; /*!< Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then + shifted according to width. */ + uint8_t *pFlagShiftWidth; /*!< Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for + shift width. */ +} pxp_store_shift_config_t; + +/*! @brief PXP store engine configuration for one of the channel. */ +typedef struct _pxp_store_engine_config +{ + bool channelEnable; /*!< Enable channel. */ + /* Address configuration */ + uint32_t outputBaseAddr0; /*!< The channel 0 output address if using 2 channels. If using 1 channel(must be channel + 0) and YUV422_2p output format, is for Y plane address. */ + uint32_t outputBaseAddr1; /*!< The channel 1 output address if using 2 channels. If using 1 channel(must be channel + 0) and YUV422_2p output format, is for UV plane address. */ + /* Size configuration */ + uint16_t totalHeight; /*!< Total height for the actual store size. */ + uint16_t totalWidth; /*!< Total width for the actual store size. */ + uint16_t pitchBytes; /*!< Channel input pitch */ + /* Interface configuration */ + pxp_store_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use + the same mode if both enabled. */ + /* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When + block is disabled, the scanline can only be 1. TODO no need now. */ + /* Pixel configuration */ + pxp_active_bits_t activeBits; /*!< Output active bits. */ + pxp_store_yuv_mode_t yuvMode; /*!< Whether to output YUV pixel format. */ + /* Fixed data configuration, only apply for channel 0. */ + bool useFixedData; /*!< Whether to use fixed value for the output data. Can be used to write fixed value to specific + memory location for memory initialization. */ + uint32_t fixedData; /*!< The value of the fixed data. */ + /* Data packing */ + bool packInSelect; /*!< When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select + high 32 bit, otherwise all 64bit of data will be selected. */ + /* Data store format */ + pxp_block_config_t storeFormat; /*!< The format to store data, block or otherwise. */ + pxp_store_shift_config_t shiftConfig; /*!< Shift operation configuration. */ +} pxp_store_engine_config_t; + +/* Pre-dither CFA engine configuration */ + +/*! @brief PXP pre-dither CFA engine input pixel format. */ +typedef enum _pxp_cfa_input_format +{ + kPXP_CfaRGB888, + kPXP_CfaRGB444, +} pxp_cfa_input_format_t; + +/*! @brief PXP pre-dither CFA engine configuration. */ +typedef struct _pxp_cfa_config +{ + bool bypass; /*!< Bypass the CFA process */ + pxp_cfa_input_format_t pixelInFormat; /*!< The pixel input format for CFA. */ + uint8_t arrayWidth; /*!< CFA array vertical size in pixels, min 3 max 15. */ + uint8_t arrayHeight; /*!< CFA array horizontal size in pixels, min 3 max 15. */ + uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the dither fetch engine + and dither engine. */ + uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the dither fetch engine and + dither engine. */ + uint32_t *cfaValue; /*!< Pointer to the value for the CFA array. 2-bit per component: 00-R,01-G,10-B,11-W. For a 4x4 + array, 32 bits are need. */ +} pxp_cfa_config_t; + +/* Histogram configuration and status */ + +/*! @brief PXP histogram mask condition. */ +typedef enum _pxp_histogram_mask_condition +{ + kPXP_HistogramMaskEqual = 0x0U, /*!< Value that equal to value0 will pass the mask operation. */ + kPXP_HistogramMaskNotequal = 0x1U, /*!< Value that not equal to value0 will pass the mask operation. */ + kPXP_HistogramMaskIn = 0x2U, /*!< Value that within the range of value0-value1 will pass the mask operation. */ + kPXP_HistogramMaskOut = 0x3U, /*!< Value that without the range of value0-value1 will pass the mask operation. */ +} pxp_histogram_mask_condition_t; + +/*! @brief PXP Histogram configuration. */ +typedef struct _pxp_histogram_config +{ + bool enable; /*!< Enable histogram process. */ + uint8_t *pParamValue; /*!< Pointer to the 62(2+4+8+16+32) byte of param value for 2-level, 4-level.....32-level + parameters. Only low 5-bit of each byte is valid. */ + uint8_t lutValueOffset; /*!< The starting bit position of the LUT value. */ + uint8_t lutValueWidth; /*!< The bit width of the LUT value, should be no more than 6 bits since only 63 LUTs are + supported. */ + /* Mask configuration */ + bool enableMask; /*!< Enable mask operation. */ + uint8_t maskValue0; /*!< Value 0 for the condition judgement. */ + uint8_t maskValue1; /*!< Value 1 for the condition judgement. */ + uint8_t maskOffset; /*!< The starting bit position of the field to be checked against mask condition. */ + uint8_t maskWidth; /*!< The width of the field to be checked against mask condition. */ + pxp_histogram_mask_condition_t condition; /*!< The mask condition. */ + /* Size configuration */ + uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the output of legacy flow + or the WFE-A/B engine. */ + uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the output of legacy flow or + the WFE-A/B engine. */ +} pxp_histogram_config_t; + +/*! @brief PXP Histogram mask result. */ +typedef struct _pxp_histogram_mask_result +{ + uint32_t pixelCount; /*!< The total count of the pixels that pass the mask(collided pixels). */ + uint32_t minX; /*!< The x offset of the ULC of the minimal histogram that covers all passed pixels. */ + uint32_t minY; /*!< The y offset of the ULC of the minimal histogram that covers all passed pixels. */ + uint32_t maxX; /*!< The x offset of the LRC of the minimal histogram that covers all passed pixels. */ + uint32_t maxY; /*!< The y offset of the LRC of the minimal histogram that covers all passed pixels. */ + uint64_t lutlist; /*!< The 64-bit LUT list of collided pixels, if pixel of LUT17 is collided, bit17 in the list is + set. */ +} pxp_histogram_mask_result_t; + +/*! @brief PXP Histogram operation result flags. */ +enum _pxp_histgram_flags +{ + kPXP_Histogram2levelMatch = 1 << 0U, /* Bitmap pixels are fully contained within the HIST2 histogram. */ + kPXP_Histogram4levelMatch = 1 << 1U, /* Bitmap pixels are fully contained within the HIST4 histogram. */ + kPXP_Histogram8levelMatch = 1 << 2U, /* Bitmap pixels are fully contained within the HIST8 histogram. */ + kPXP_Histogram16levelMatch = 1 << 3U, /* Bitmap pixels are fully contained within the HIST16 histogram. */ + kPXP_Histogram32levelMatch = 1 << 4U, /* Bitmap pixels are fully contained within the HIST32 histogram. */ +}; + +/*! @brief PXP WFE-A engine configuration. */ +typedef struct _pxp_wfea_engine_config +{ + uint32_t y4Addr; /*!< Address for Y4 buffer. */ + uint32_t y4cAddr; /*!< Address for Y4C buffer, {Y4[3:0],3'b000,collision}, 8bpp. */ + uint32_t wbAddr; /*!< Address for EPDC working buffer. */ + uint16_t updateWidth; /*!< Width of the update area. */ + uint16_t updateHeight; /*!< Height of the update area. */ + uint16_t updatePitch; /*!< Pitch of the update area. */ + uint16_t ulcX; /*!< X coordinate of upper left coordinate of the total input memory */ + uint16_t ulcY; /*!< Y coordinate of upper left coordinate of the total input memory */ + uint16_t resX; /*!< Horizontal resolution in pixels. */ + uint8_t lutNum; /*!< The EPDC LUT number for the update. */ + bool fullUpdateEnable; /*!< Enable full update. */ + bool alphaEnable; /*!< Enable alpha field, upd is {Y4[3:0],3'b000,alpha} format, otherwise its {Y4[3:0],4'b0000}. */ + bool detectionOnly; /*!< Detection only, do not write working buffer. */ +} pxp_wfea_engine_config_t; + +#endif /* FSL_FEATURE_PXP_V3 */ + /******************************************************************************* * API ******************************************************************************/ @@ -658,6 +1195,39 @@ static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size); } +#if PXP_USE_PATH +/*! + * @brief Sets the path for one of the MUX + * + * @param base PXP peripheral base address. + * @param path the path configuration for one of the mux. + */ +void PXP_SetPath(PXP_Type *base, pxp_path_t path); +#endif /* PXP_USE_PATH */ + +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief Enables or disables PXP engines in the process flow. + * + * @param base PXP peripheral base address. + * @param mask The engines to enable. Logical OR of @ref pxp_process_engine_name_t. + * @param enable true to enable, false to disable. + */ +static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable) +{ + mask &= 0xF3F0000UL; + + if (enable) + { + base->CTRL_SET = mask; + } + else + { + base->CTRL_CLR = mask; + } +} +#endif /* FSL_FEATURE_PXP_V3 */ + /* @} */ /*! @@ -685,13 +1255,17 @@ static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size static inline uint32_t PXP_GetStatusFlags(PXP_Type *base) { #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) - return base->STAT & - (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | - PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | PXP_STAT_AXI_WRITE_ERROR_1_MASK); + uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | + PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | + PXP_STAT_AXI_WRITE_ERROR_1_MASK); #else - return base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | - PXP_STAT_AXI_WRITE_ERROR_0_MASK); + uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | + PXP_STAT_AXI_WRITE_ERROR_0_MASK); #endif +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + status |= (base->IRQ >> 16U | base->IRQ << 16U); +#endif /* FSL_FEATURE_PXP_V3 */ + return status; } /*! @@ -705,6 +1279,10 @@ static inline uint32_t PXP_GetStatusFlags(PXP_Type *base) static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask) { base->STAT_CLR = statusMask; +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + statusMask &= 0xFFFF8000UL; + base->IRQ_CLR = (statusMask >> 16U | statusMask << 16U); +#endif /* FSL_FEATURE_PXP_V3 */ } /*! @@ -719,7 +1297,7 @@ static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask) static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex) { #if defined(PXP_STAT_AXI_ERROR_ID_1_MASK) - if (0 == axiIndex) + if (0U == axiIndex) { return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT); } @@ -755,7 +1333,11 @@ static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex) */ static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask) { - base->CTRL_SET = mask; + base->CTRL_SET = (mask & 0xEUL); +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + mask &= 0xFFFF8000UL; + base->IRQ_MASK_SET = (mask >> 16U | mask << 16U); +#endif /* FSL_FEATURE_PXP_V3 */ } /*! @@ -769,7 +1351,11 @@ static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask) */ static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask) { - base->CTRL_CLR = mask; + base->CTRL_CLR = (mask & 0xEUL); +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + mask &= 0xFFFF8000UL; + base->IRQ_MASK_CLR = (mask >> 16U | mask << 16U); +#endif /* FSL_FEATURE_PXP_V3 */ } /* @} */ @@ -795,6 +1381,15 @@ void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_ */ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config); +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief Set the alpha surface blending configuration for the secondary engine. + * + * @param base PXP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config); + /*! * @brief Set the alpha surface overlay color key. * @@ -804,6 +1399,51 @@ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t * matches its colorkey range, the PS background color is used. * * @param base PXP peripheral base address. + * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + * + * @note Colorkey operations are higher priority than alpha or ROP operations + */ +void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh); + +/*! + * @brief Enable or disable the alpha surface color key. + * + * @param base PXP peripheral base address. + * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * @param enable True to enable, false to disable. + */ +static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable) +{ + switch (num) + { + case 0: + base->AS_CTRL = + (base->AS_CTRL & ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK) | PXP_AS_CTRL_ENABLE_COLORKEY((uint32_t)enable); + break; + + case 1: + base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) | + PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable); + break; + + default: + /* Only 2 alpha process engine instances are supported. */ + assert(false); + break; + } +} +#else +/*! + * @brief Set the alpha surface overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface + * pixel value for that location. If no PS image is present or if the PS image also + * matches its colorkey range, the PS background color is used. + * + * @param base PXP peripheral base address. * @param colorKeyLow Color key low range. * @param colorKeyHigh Color key high range. * @@ -828,6 +1468,7 @@ static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool en base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK; } } +#endif /* FSL_FEATURE_PXP_V3 */ /*! * @brief Set the alpha surface position in output buffer. @@ -846,7 +1487,33 @@ void PXP_SetAlphaSurfacePosition( * @name Process surface * @{ */ +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief Set the back ground color of PS. + * + * @param base PXP peripheral base address. + * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * @param backGroundColor Pixel value of the background color. + */ +static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor) +{ + switch (num) + { + case 0: + base->PS_BACKGROUND_0 = backGroundColor; + break; + + case 1: + base->PS_BACKGROUND_1 = backGroundColor; + break; + default: + /* Only 2 alpha process engine instances are supported. */ + assert(false); + break; + } +} +#else /*! * @brief Set the back ground color of PS. * @@ -861,6 +1528,7 @@ static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t base->PS_BACKGROUND = backGroundColor; #endif } +#endif /* FSL_FEATURE_PXP_V3 */ /*! * @brief Set the process surface input buffer configuration. @@ -896,6 +1564,20 @@ void PXP_SetProcessSurfaceScaler( void PXP_SetProcessSurfacePosition( PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief Set the process surface color key. + * + * If the PS image matches colorkey range, the PS background color is output. Set + * @p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying. + * + * @param base PXP peripheral base address. + * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + */ +void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh); +#else /*! * @brief Set the process surface color key. * @@ -907,6 +1589,7 @@ void PXP_SetProcessSurfacePosition( * @param colorKeyHigh Color key high range. */ void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); +#endif /* FSL_FEATURE_PXP_V3 */ /*! * @brief Set the process surface input pixel format YUV or YCbCr. @@ -1014,35 +1697,15 @@ static inline void PXP_SetRotateConfig(PXP_Type *base, (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) | PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT); #else - uint32_t ctrl = base->CTRL; + uint32_t ctrl = base->CTRL; if (kPXP_RotateOutputBuffer == position) { - if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable)) - { - base->DATA_PATH_CTRL0 = - (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(0); - } - else - { - base->DATA_PATH_CTRL0 = - (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(1); - } ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK); ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT)); } else { - if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable)) - { - base->DATA_PATH_CTRL0 = - (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(1); - } - else - { - base->DATA_PATH_CTRL0 = - (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(0); - } ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK); ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT)); } @@ -1050,6 +1713,25 @@ static inline void PXP_SetRotateConfig(PXP_Type *base, base->CTRL = ctrl; #endif } + +/*! + * @brief Build a solid rectangle of given pixel value. + * + * @param base PXP peripheral base address. + * @param outFormat output pixel format. + * @param value The value of the pixel to be filled in the rectangle in ARGB8888 format. + * @param width width of the rectangle. + * @param height height of the rectangle. + * @param pitch output pitch in byte. + * @param outAddr address of the memory to store the rectangle. + */ +void PXP_BuildRect(PXP_Type *base, + pxp_output_pixel_format_t outFormat, + uint32_t value, + uint16_t width, + uint16_t height, + uint16_t pitch, + uint32_t outAddr); /* @} */ /*! @@ -1122,7 +1804,9 @@ static inline bool PXP_IsNextCommandPending(PXP_Type *base) static inline void PXP_CancelNextCommand(PXP_Type *base) { /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */ - *((volatile uint32_t *)(&(base->NEXT)) + 2U) = PXP_NEXT_ENABLED_MASK; + uint32_t regAddr = (uint32_t) & (base->NEXT); + regAddr += 8U; + *(uint32_t *)regAddr = PXP_NEXT_ENABLED_MASK; } /* @} */ @@ -1318,7 +2002,16 @@ void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t */ static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config) { - base->DITHER_CTRL = *((const uint32_t *)config) & 0x00FFFFFFU; + typedef union + { + pxp_dither_config_t _dither_config; + uint32_t _u32; + } pxp_reg_convert_t; + + pxp_reg_convert_t pid; + + pid._dither_config = *config; + base->DITHER_CTRL = pid._u32 & 0x00FFFFFFU; } /*! @@ -1344,7 +2037,18 @@ void PXP_EnableDither(PXP_Type *base, bool enable); * @name Porter Duff * @{ */ +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 +/*! + * @brief Set the Porter Duff configuration for one of the alpha process engine. + * + * @param base PXP peripheral base address. + * @param num instance number. + * @param config Pointer to the configuration. + */ +void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config); +#endif /* FSL_FEATURE_PXP_V3 */ +#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) /*! * @brief Set the Porter Duff configuration. * @@ -1352,7 +2056,10 @@ void PXP_EnableDither(PXP_Type *base, bool enable); * @param config Pointer to the configuration. */ void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config); +#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ +#if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \ + (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3) /*! * @brief Get the Porter Duff configuration by blend mode. * @@ -1370,6 +2077,9 @@ void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *con status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config); /* @} */ +#endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ + +/* @} */ /*! * @name Buffer copy @@ -1447,8 +2157,545 @@ status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *confi */ status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size); +/*! + * @brief Copy continous memory. + * + * @note This function resets the old PXP settings, which means the settings + * like rotate, flip, will be reseted to disabled status. + * + * @note Compare with @PXP_StartMemCopy, this function supports size not aligned to + * 512 bytes. This function returns when copy finished, upper layer doesn't need to + * wait @ref kPXP_CompleteFlag. + * + * @param base PXP peripheral base address. + * @param srcAddr Source memory address. + * @param destAddr Destination memory address. + * @param size How many bytes to copy, should be 512 byte aligned. + * @retval kStatus_Success Successfully started the copy process. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size); + +/* @} */ + +#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 + +/*! + * @name Fetch engine + * @{ + */ +/*! + * @brief Configures one channel of some block's fetch engine. + * + * Fetch engine is 64-bit input and 32-bit output per channel + * + * @param base PXP peripheral base address. + * @param name which block the fetch engine belongs to. + * @param channel channel number. + * @param config pointer to the configuration structure. + * @retval kStatus_Success Successfully configured the engine. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetFetchEngineConfig(PXP_Type *base, + pxp_fetch_engine_name_t name, + uint8_t channel, + const pxp_fetch_engine_config_t *config); + +/*! + * @brief Enables/disables the fetch engine. + * + * @param base PXP peripheral base address. + * @param name which block the fetch engine belongs to. + * @param channel channel number. + * @param enable true to enable, false to disable. + */ +static inline void PXP_EnableFetchEngine(PXP_Type *base, pxp_fetch_engine_name_t name, uint8_t channel, bool enable) +{ + if (enable) + { + if (name == kPXP_FetchInput) + { + switch (channel) + { + case 0: + base->INPUT_FETCH_CTRL_CH0_SET = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->INPUT_FETCH_CTRL_CH1_SET = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_FETCH_CTRL_CH0_SET = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->DITHER_FETCH_CTRL_CH1_SET = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + } + else + { + if (name == kPXP_FetchInput) + { + switch (channel) + { + case 0: + base->INPUT_FETCH_CTRL_CH0_CLR = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->INPUT_FETCH_CTRL_CH1_CLR = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_FETCH_CTRL_CH0_CLR = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->DITHER_FETCH_CTRL_CH1_CLR = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + } +} +/* @} */ + +/*! + * @name Store engine + * @{ + */ + +/*! + * @brief Configures one channel of some block's store engine. + * + * Store engine is 32-bit input and 64-bit output per channel. + * @note: If there is only one channel used for data input, channel 0 must be used rather than channel 1. + * + * @param base PXP peripheral base address. + * @param name the store engine belongs to which block. + * @param channel channel number. + * @param config pointer to the configuration structure. + * @retval kStatus_Success Successfully configured the engine. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetStoreEngineConfig(PXP_Type *base, + pxp_store_engine_name_t name, + uint8_t channel, + const pxp_store_engine_config_t *config); + +/*! + * @brief Enables/disables the store engine. + * + * @param base PXP peripheral base address. + * @param name which block the store engine belongs to. + * @param channel channel number. + * @param enable true to enable, false to disable. + */ +static inline void PXP_EnableStoreEngine(PXP_Type *base, pxp_store_engine_name_t name, uint8_t channel, bool enable) +{ + if (enable) + { + if (name == kPXP_StoreInput) + { + switch (channel) + { + case 0: + base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->INPUT_STORE_CTRL_CH1_SET = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->DITHER_STORE_CTRL_CH1_SET = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + } + else + { + if (name == kPXP_StoreInput) + { + switch (channel) + { + case 0: + base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->INPUT_STORE_CTRL_CH1_CLR = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + else + { + switch (channel) + { + case 0: + base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK; + break; + + case 1: + base->DITHER_STORE_CTRL_CH1_CLR = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK; + break; + + default: + /* Only 2 channels are supported per fetch engine. */ + assert(false); + break; + } + } + } +} + +/*! + * @brief Combines the 2 channels of some store engine. + * + * Store engine is 32-bit input and 64-bit output per channel. If both channels of store engine's + * input and 8 bits flag contain valid data, then need set combine to true to support total 64-bit input. + * + * @param base PXP peripheral base address. + * @param name the store engine belongs to which block. + * @param combine true to combine the 2 channels. + */ +static inline void PXP_CombineStoreEngineChannel(PXP_Type *base, pxp_store_engine_name_t name, bool combine) +{ + if (name == kPXP_StoreInput) + { + if (combine) + { + base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; + } + else + { + base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; + } + } + else + { + if (combine) + { + base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; + } + else + { + base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; + } + } +} /* @} */ +/*! + * @name Pre-dither CFA engine + * @{ + */ +/*! + * @brief Configures the pre-dither CFA engine. + * + * @param base PXP peripheral base address. + * @param config pointer to the configuration structure. + * @retval kStatus_Success Successfully configured the engine. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config); + +/*! + * @brief Enables/disables the CFA block. + * + * @param base PXP peripheral base address. + * @param enable true to enable, false to disable. + */ +static inline void PXP_EnableCfa(PXP_Type *base, bool enable) +{ + if (enable) + { + base->CFA_CTRL_CLR = PXP_CFA_CTRL_CFA_BYPASS_MASK; + } + else + { + base->CFA_CTRL_SET = PXP_CFA_CTRL_CFA_BYPASS_MASK; + } +} +/* @} */ + +/*! + * @name Histogram engine + * @{ + */ +/*! + * @brief Configures histogram engine. + * + * @param base PXP peripheral base address. + * @param num instance number. + * @param config pointer to the configuration structure. + * @retval kStatus_Success Successfully configured the engine. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config); + +/*! + * @brief Enables/disables the histogram engine. + * + * @param base PXP peripheral base address. + * @param num instance number. + * @param enable true to enable, false to disable. + */ +static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable) +{ + switch (num) + { + case 0: + base->HIST_A_CTRL = + (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable); + break; + + case 1: + base->HIST_B_CTRL = + (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable); + break; + + default: + /* Only 2 instances are supported per fetch engine. */ + assert(false); + break; + } +} + +/*! + * @brief Gets the results of histogram mask operation. + * + * @param base PXP peripheral base address. + * @param num instance number. + * @param result pointer to the result structure. + */ +void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result); + +/*! + * @brief Gets the PXP Histogram operation result + * + * @param base PXP peripheral base address. + * @param num instance number. + * @return bit map of the match result in @ref _pxp_histgram_flags ORed together + */ +static inline uint8_t PXP_GetHistogramMatchResult(PXP_Type *base, uint8_t num) +{ + uint8_t result = 0U; + switch (num) + { + case 0: + result = (uint8_t)((base->HIST_A_CTRL & PXP_HIST_A_CTRL_STATUS_MASK) >> PXP_HIST_A_CTRL_STATUS_SHIFT); + break; + + case 1: + result = (uint8_t)((base->HIST_B_CTRL & PXP_HIST_B_CTRL_STATUS_MASK) >> PXP_HIST_B_CTRL_STATUS_SHIFT); + break; + + default: + /* Only 2 histogram instances are supported. */ + assert(false); + break; + } + + return result; +} + +/*! + * @brief Clears the current histogram operation result. + * + * Clears the current histogram operation result, including mask operation result and from 2-level to 32-level match + * result. + * + * @param base PXP peripheral base address. + * @param num instance number. + */ +static inline void PXP_ClearHistogramResult(PXP_Type *base, uint8_t num) +{ + switch (num) + { + case 0: + base->HIST_A_CTRL |= PXP_HIST_A_CTRL_CLEAR_MASK; + break; + + case 1: + base->HIST_B_CTRL |= PXP_HIST_B_CTRL_CLEAR_MASK; + break; + + default: + /* Only 2 histogram instances are supported. */ + assert(false); + break; + } +} + +/*! + * @brief Gets the results of histogram mask operation. + * + * @param base PXP peripheral base address. + * @param num instance number. + * @param width the width of the updated block + * @param height the height of the updated block + */ +static inline void PXP_SetHistogramSize(PXP_Type *base, uint8_t num, uint16_t width, uint16_t height) +{ + switch (num) + { + case 0: + base->HIST_A_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width; + break; + + case 1: + base->HIST_B_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width; + break; + + default: + /* Only 2 histogram instances are supported. */ + assert(false); + break; + } +} +/* @} */ + +/*! + * @name WFE engine + * @{ + */ + +/*! + * @brief Initializes the WFE-A engine for waveform process. + * + * @param base PXP peripheral base address. + * @param ditherHandshake true to enable handshake mode with upstream dither store engine. + */ +void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake); + +/*! + * @brief Enables/disables hanshake mode with upstream dither engine. + * + * @param base PXP peripheral base address. + * @param enable true to enable handshake mode with upstream dither store engine. + */ +static inline void PXP_WfeaEnableDitherHandshake(PXP_Type *base, bool enable) +{ + if (enable) + { + base->WFA_FETCH_CTRL |= PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK; + } + else + { + base->WFA_FETCH_CTRL &= ~PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK; + } +} + +/*! + * @brief Configure the WFE-A engine + * + * @param base PXP peripheral base address. + * @param config pointer to the configuration structure. + */ +void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config); + +/*! + * @brief Sets the LUT usage status for waveform engine. + * + * If any EPDC LUT(s) has been occupied, use this API to set its usage for PXP WFE-A. + * + * @param base PXP base pointer + * @param lutStatus the status mask of the LUT(s) to be set, can be a single flag or several flags up to all 64 LUTs. + * If user wants to set LUT17 usage, set bit 17 in the lutStatus. + */ +static inline void PXP_SetLutUsage(PXP_Type *base, uint64_t lutStatus) +{ + base->WFE_A_STG1_8X1_OUT0_0 |= (uint32_t)lutStatus; + base->WFE_A_STG1_8X1_OUT0_1 |= (uint32_t)(lutStatus >> 32U); +} + +/*! + * @brief Clears the LUT usage status for waveform engine. + * + * If any EPDC LUT(s) has finished processing and is(are) free, use this API to clear its usage for PXP WFE-A. + * + * @param base PXP base pointer + * @param lutStatus the status mask of the LUT(s) to be cleared, can be a single flag or several flags up to all 64 + * LUTs. If user wants to clear LUT17, set bit 17. + */ +static inline void PXP_ClearLutUsage(PXP_Type *base, uint64_t lutStatus) +{ + base->WFE_A_STG1_8X1_OUT0_0 &= ~(uint32_t)lutStatus; + base->WFE_A_STG1_8X1_OUT0_1 &= ~(uint32_t)(lutStatus >> 32U); +} + +/*! + * @brief Gets the occupied LUT list. + * + * @param base PXP base pointer + * @return lutStatus the status mask of the LUT(s) that is(are) occupied + */ +static inline uint64_t PXP_GetLutUsage(PXP_Type *base) +{ + return ((uint64_t)base->WFE_A_STG1_8X1_OUT0_0 | (uint64_t)base->WFE_A_STG1_8X1_OUT0_1 << 32U); +} + +/* @} */ + +#endif /* FSL_FEATURE_PXP_V3 */ + #if defined(__cplusplus) } #endif diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c index 44b7867441..24b9becec7 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -525,6 +525,8 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin * depending on the count direction * 2. User can call the utility macros provided in fsl_common.h to convert to ticks * 3. This function supports cases, providing only primary source clock without secondary source clock. + * 4. The load register is reset before the counter is reinitialized to the value + specified in the load register. * * param base Quad Timer peripheral base address * param channel Quad Timer channel number @@ -535,6 +537,34 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1 /* Set the length bit to reinitialize the counters on a match */ base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; + /* Reset LOAD register to reinitialize the counters */ + base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK); + + if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U) + { + /* Counting down */ + base->CHANNEL[channel].COMP2 = ticks - 1U; + } + else + { + /* Counting up */ + base->CHANNEL[channel].COMP1 = ticks - 1U; + } +} + +/*! + * brief Set compare value. + * + * This function sets the value used for comparison with the counter value. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param ticks Timer period in units of ticks. + */ +void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) +{ + base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; + if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U) { /* Counting down */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h index 2f517cbbf7..ad214b2117 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,7 +20,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version */ +#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version */ /*@}*/ /*! @brief Quad Timer primary clock source selection*/ @@ -349,6 +349,32 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); /*! + * @brief Set compare value. + * + * This function sets the value used for comparison with the counter value. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param ticks Timer period in units of ticks. + */ +void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); + +/*! + * @brief Set load value. + * + * This function sets the value used to initialize the counter after a counter comparison. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param value Load register initialization value. + */ +static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value) +{ + base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK); + base->CHANNEL[channel].LOAD = value; +} + +/*! * @brief Reads the current timer counting value. * * This function returns the real-time timer counting value, in a range from 0 to a diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c index 4301935dd5..b77e482dac 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -363,7 +363,7 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config, /* frame sync default configurations */ config->frameSync.frameSyncWidth = (uint8_t)bitWidth; config->frameSync.frameSyncEarly = true; -#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE config->frameSync.frameSyncGenerateOnDemand = false; #endif config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow; @@ -865,11 +865,11 @@ void SAI_RxEnable(I2S_Type *base, bool enable) * This function will also clear all the error flags such as FIFO error, sync error etc. * * param base SAI base pointer - * param type Reset type, FIFO reset or software reset + * param resetType Reset type, FIFO reset or software reset */ -void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType) { - base->TCSR |= (uint32_t)type; + base->TCSR |= (uint32_t)resetType; /* Clear the software reset */ base->TCSR &= ~I2S_TCSR_SR_MASK; @@ -884,11 +884,11 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) * This function will also clear all the error flags such as FIFO error, sync error etc. * * param base SAI base pointer - * param type Reset type, FIFO reset or software reset + * param resetType Reset type, FIFO reset or software reset */ -void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType) { - base->RCSR |= (uint32_t)type; + base->RCSR |= (uint32_t)resetType; /* Clear the software reset */ base->RCSR &= ~I2S_RCSR_SR_MASK; @@ -1318,7 +1318,7 @@ void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); -#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE tcr4 &= ~I2S_TCR4_ONDEM_MASK; tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand); #endif @@ -1347,7 +1347,7 @@ void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK); -#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE rcr4 &= ~I2S_RCR4_ONDEM_MASK; rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand); #endif @@ -2133,7 +2133,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint } SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); - buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord); i += bytesPerWord; } @@ -2188,7 +2188,7 @@ void SAI_WriteMultiChannelBlocking( SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, bytesPerWord * channelNums); - buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums); j += bytesPerWord * channelNums; } @@ -2241,7 +2241,7 @@ void SAI_ReadMultiChannelBlocking( SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, bytesPerWord * channelNums); - buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums); j += bytesPerWord * channelNums; } } @@ -2273,7 +2273,7 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8 } SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); - buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord); i += bytesPerWord; } } @@ -2745,7 +2745,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); } #else if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)) @@ -2757,7 +2757,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) /* Update internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); } #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ @@ -2821,7 +2821,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) /* Update the internal counter */ handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); } #else if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK)) @@ -2833,7 +2833,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) /* Update internal state */ handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size); + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); } #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h index 37cf0d00f9..d69e13ac9d 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) /*!< Version 2.3.4 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) /*!< Version 2.3.6 */ /*@}*/ /*! @brief _sai_status_t, SAI return status.*/ @@ -365,7 +365,7 @@ typedef struct _sai_frame_sync bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame */ -#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */ #endif @@ -940,9 +940,9 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) * This function will also clear all the error flags such as FIFO error, sync error etc. * * @param base SAI base pointer - * @param type Reset type, FIFO reset or software reset + * @param tresetType Reset type, FIFO reset or software reset */ -void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType); /*! * @brief Do software reset or FIFO reset . @@ -953,9 +953,9 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); * This function will also clear all the error flags such as FIFO error, sync error etc. * * @param base SAI base pointer - * @param type Reset type, FIFO reset or software reset + * @param resetType Reset type, FIFO reset or software reset */ -void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type); +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType); /*! * @brief Set the Tx channel FIFO enable mask. @@ -1218,9 +1218,9 @@ static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) * @param channel Which data channel used. * @return data register address. */ -static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) { - return (uint32_t)(&(base->TDR)[channel]); + return (uintptr_t)(&(base->TDR)[channel]); } /*! @@ -1232,9 +1232,9 @@ static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t cha * @param channel Which data channel used. * @return data register address. */ -static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) { - return (uint32_t)(&(base->RDR)[channel]); + return (uintptr_t)(&(base->RDR)[channel]); } /*! @} */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c index 8384f4a95f..0b62c40d14 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h index 22c3f67e1e..e457271986 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c index 68baf38421..84b54317b8 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,11 +24,15 @@ #else #define SEMC_IOCR_PINMUXBITWIDTH (0x3UL) #endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */ -#define SEMC_IOCR_NAND_CE (4UL) -#define SEMC_IOCR_NOR_CE (5UL) -#define SEMC_IOCR_NOR_CE_A8 (2UL) -#define SEMC_IOCR_PSRAM_CE (6UL) -#define SEMC_IOCR_PSRAM_CE_A8 (3UL) +#define SEMC_IOCR_NAND_CE (4UL) +#define SEMC_IOCR_NOR_CE (5UL) +#define SEMC_IOCR_NOR_CE_A8 (2UL) +#define SEMC_IOCR_PSRAM_CE (6UL) +#if defined(SEMC_IOCR_PINMUXBITWIDTH) && (SEMC_IOCR_PINMUXBITWIDTH == 0x4UL) +#define SEMC_IOCR_PSRAM_CE_A8 (6UL) +#else +#define SEMC_IOCR_PSRAM_CE_A8 (3UL) +#endif /* SEMC_IOCR_PINMUXBITWIDTH */ #define SEMC_IOCR_DBI_CSX (7UL) #define SEMC_IOCR_DBI_CSX_A8 (4UL) #define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) @@ -63,12 +67,11 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base); /*! * @brief Covert the input memory size to internal register set value. * - * @param base SEMC peripheral base address * @param size_kbytes SEMC memory size in unit of kbytes. * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. * @return Execution status. */ -static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); +static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted); /*! * @brief Covert the external timing nanosecond to internal clock cycle. @@ -131,7 +134,7 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base) return instance; } -static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) +static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted) { assert(sizeConverted != NULL); uint32_t memsize; @@ -408,7 +411,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->csxPinMux)); /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize); if (result != kStatus_Success) { return result; @@ -541,14 +544,14 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_ { base->MCR &= ~SEMC_MCR_WPOL1_MASK; } - result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->axiMemsize_kbytes, &memsize); if (result != kStatus_Success) { return result; } base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->ipgMemsize_kbytes, &memsize); if (result != kStatus_Success) { return result; @@ -689,7 +692,7 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t { base->MCR &= ~SEMC_MCR_WPOL0_MASK; } - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize); if (result != kStatus_Success) { return result; @@ -843,7 +846,7 @@ status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base, } } /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize); if (result != kStatus_Success) { return result; @@ -1076,7 +1079,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t /* IOMUX setting. */ base->IOCR = iocReg | (muxCsx << (uint32_t)config->csxPinMux); /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize); if (result != kStatus_Success) { return result; @@ -1114,7 +1117,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t * brief SEMC IP command access. * * param base SEMC peripheral base address. - * param type SEMC memory type. refer to "semc_mem_type_t" + * param memType SEMC memory type. refer to "semc_mem_type_t" * param address SEMC device address. * param command SEMC IP command. * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. @@ -1125,7 +1128,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t * param read Data pointer for read data out. */ status_t SEMC_SendIPCommand( - SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read) + SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read) { uint32_t cmdMode; bool readCmd = false; @@ -1139,7 +1142,7 @@ status_t SEMC_SendIPCommand( /* Check command mode. */ cmdMode = (uint32_t)command & 0x0FU; - switch (type) + switch (memType) { case kSEMC_MemType_NAND: readCmd = (cmdMode == (uint32_t)kSEMC_NANDCM_CommandAddressRead) || diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h index 7394840ba2..e6efec0d8e 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,8 +20,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief SEMC driver version 2.3.1. */ -#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @brief SEMC driver version. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*@}*/ /*! @brief SEMC status, _semc_status. */ @@ -479,7 +479,7 @@ typedef struct _semc_nor_config uint8_t latencyCount; /*!< Latency count for sync mode. */ #endif #if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) - uint8_t readCycle; /*!< Read cycle time for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ #endif #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than @@ -832,7 +832,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base) * @brief SEMC IP command access. * * @param base SEMC peripheral base address. - * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param memType SEMC memory type. refer to "semc_mem_type_t" * @param address SEMC device address. * @param command SEMC IP command. * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. @@ -843,7 +843,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base) * @param read Data pointer for read data out. */ status_t SEMC_SendIPCommand( - SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read); + SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read); /*! * @brief Build SEMC IP command for NAND. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c index 1fcec43e9f..485ba01b58 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2017-2019, 2021 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -278,11 +278,7 @@ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) { assert(config != NULL); -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) - uint32_t instance = SNVS_HP_GetInstance(base); - CLOCK_EnableClock(s_snvsHpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + SNVS_HP_Init(base); base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK; @@ -304,11 +300,7 @@ void SNVS_HP_RTC_Deinit(SNVS_Type *base) { base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) - uint32_t instance = SNVS_HP_GetInstance(base); - CLOCK_DisableClock(s_snvsHpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + SNVS_HP_Deinit(base); } /*! diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h index e5f7b52bc7..713f16b037 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2017-2021, NXP + * Copyright 2017-2022, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*!< Version 2.3.2 */ /*@}*/ /*! @brief List of SNVS interrupts */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c index f0e49e951f..c9a703eebe 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2017-2021, NXP + * Copyright 2017-2022, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -285,11 +285,7 @@ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) { assert(config != NULL); -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) - uint32_t instance = SNVS_LP_GetInstance(base); - CLOCK_EnableClock(s_snvsLpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + SNVS_LP_Init(base); if (config->srtcCalEnable) { @@ -318,11 +314,7 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base) { base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) - uint32_t instance = SNVS_LP_GetInstance(base); - CLOCK_DisableClock(s_snvsLpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + SNVS_LP_Deinit(base); } /*! diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h index f487567d59..44b9aa02d6 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2017-2021, NXP + * Copyright 2017-2022, NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*!< Version 2.4.3 */ +#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4 */ /*@}*/ /*! @brief Define of SNVS_LP Zeroizable Master Key registers */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h index 1aeb4fc86d..71756e4769 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019, 2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -28,6 +28,9 @@ /* Set the XBARA_SELx_SELx field to a new value. */ #define XBARA_WR_SELx_SELx(base, input, output) XBARA_SetSignalsConnection((base), (input), (output)) +/* For driver backward compatibility. */ +#define kXBARA_RequestInterruptEnalbe kXBARA_RequestInterruptEnable + /*! * @brief XBARA active edge for detection */ @@ -46,7 +49,7 @@ typedef enum _xbar_request { kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ - kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ + kXBARA_RequestInterruptEnable = 2U /*!< Interrupt enabled, DMA disabled. */ } xbara_request_t; /*! diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.c new file mode 100644 index 0000000000..80dd21425d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.c @@ -0,0 +1,475 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "generic_list.h" + +static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + list_element_handle_t element = list->head; + + if ((list->max != 0U) && (list->max == list->size)) + { + listStatus = kLIST_Full; /*List is full*/ + } + else + { + while (element != NULL) /*Scan list*/ + { + /* Determine if element is duplicated */ + if (element == newElement) + { + listStatus = kLIST_DuplicateError; + break; + } + element = element->next; + } + } + + return listStatus; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initialises the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = (uint16_t)max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t element) +{ + return element->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + if (list->size == 0U) + { + list->head = element; + } + else + { + list->tail->next = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + element->prev = list->tail; +#endif + element->list = list; + element->next = NULL; + list->tail = element; + list->size++; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + /* Links element to the head of the list */ + if (list->size == 0U) + { + list->tail = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + list->head->prev = element; + } + element->prev = NULL; +#endif + element->list = list; + element->next = list->head; + list->head = element; + list->size++; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t element; + + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((NULL == list) || (list->size == 0U)) + { + element = NULL; /*LIST_ is empty*/ + } + else + { + element = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + element->next->prev = NULL; + } +#endif + element->list = NULL; + list->head = element->next; /*Is NULL if element is head*/ + } + + EnableGlobalIRQ(regPrimask); + return element; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t element) +{ + return element->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element) +{ +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + return NULL; +#else + return element->prev; +#endif +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t element) +{ + list_status_t listStatus = kLIST_Ok; + uint32_t regPrimask = DisableGlobalIRQ(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (element_list) + { + if (element->list->head == element) + { + element->list->head = element_list->next; + break; + } + if (element_list->next == element) + { + element_list->next = element->next; + break; + } + element_list = element_list->next; + } +#else + if (element->prev == NULL) /*Element is head or solo*/ + { + element->list->head = element->next; /*is null if solo*/ + } + if (element->next == NULL) /*Element is tail or solo*/ + { + element->list->tail = element->prev; /*is null if solo*/ + } + if (element->prev != NULL) /*Element is not head*/ + { + element->prev->next = element->next; + } + if (element->next != NULL) /*Element is not tail*/ + { + element->next->prev = element->prev; + } +#endif + element->list->size--; + element->list = NULL; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + uint32_t regPrimask = DisableGlobalIRQ(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { + listStatus = LIST_Error_Check(element->list, newElement); + if (listStatus == kLIST_Ok) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (element_list) + { + if ((element_list->next == element) || (element_list == element)) + { + if (element_list == element) + { + element->list->head = newElement; + } + else + { + element_list->next = newElement; + } + newElement->list = element->list; + newElement->next = element; + element->list->size++; + break; + } + element_list = element_list->next; + } + +#else + if (element->prev == NULL) /*Element is list head*/ + { + element->list->head = newElement; + } + else + { + element->prev->next = newElement; + } + newElement->list = element->list; + element->list->size++; + newElement->next = element; + newElement->prev = element->prev; + element->prev = newElement; +#endif + } + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/ +} diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.h new file mode 100644 index 0000000000..def00efe8e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.h @@ -0,0 +1,203 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +#include "fsl_common.h" +/*! + * @addtogroup GenericList + * @{ + */ + +/*!********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public macro definitions +************************************************************************************* +********************************************************************************** */ +#ifndef GENERIC_LIST_LIGHT +#define GENERIC_LIST_LIGHT (0) +#endif +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief The list status */ +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ + kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */ +} list_status_t; + +/*! @brief The list structure*/ +typedef struct list_label +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint16_t size; /*!< list size */ + uint16_t max; /*!< list max number of elements */ +} list_label_t, *list_handle_t; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#else +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#endif +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param element - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t element); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t element); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element); + +/*! + * @brief Unlinks an element from its list. + * + * @param element - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t element); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h index 894d2a5dde..3feb56d8de 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -16,7 +16,7 @@ * The CPU macro should be declared in the project or makefile. */ #if (defined(CPU_MIMXRT1062CVJ5A) || defined(CPU_MIMXRT1062CVL5A) || defined(CPU_MIMXRT1062DVJ6A) || \ - defined(CPU_MIMXRT1062DVL6A)) + defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVN6B) || defined(CPU_MIMXRT1062XVN5B)) #define MIMXRT1062_SERIES diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld index f819d1e8d9..633f7dd6dc 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld index d421d281cd..0c006d2925 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_ram.ld b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_ram.ld index 5624397254..553148c72b 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_ram.ld +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_ram.ld @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram.ld b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram.ld index 1139fece24..0c3c2c0fe7 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram.ld +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram.ld @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram_txt.ld b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram_txt.ld index f8fb6712e4..317a1d0fde 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram_txt.ld +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_sdram_txt.ld @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compiler: GNU C Compiler -** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 -** Version: rev. 0.1, 2017-01-10 -** Build: b210709 +** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 +** Version: rev. 0.2, 2022-03-25 +** Build: b220401 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/startup_MIMXRT1062.S b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/startup_MIMXRT1062.S index da3d5675f6..cc40aab745 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/startup_MIMXRT1062.S +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/startup_MIMXRT1062.S @@ -2,13 +2,13 @@ /* @file: startup_MIMXRT1062.s */ /* @purpose: CMSIS Cortex-M7 Core Device Startup File */ /* MIMXRT1062 */ -/* @version: 1.2 */ -/* @date: 2019-4-29 */ -/* @build: b190919 */ +/* @version: 1.4 */ +/* @date: 2022-3-25 */ +/* @build: b220425 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2019 NXP */ +/* Copyright 2016-2022 NXP */ /* All rights reserved. */ /* */ /* SPDX-License-Identifier: BSD-3-Clause */ @@ -111,7 +111,7 @@ __isr_vector: .long ADC2_IRQHandler /* ADC2 interrupt*/ .long DCDC_IRQHandler /* DCDC interrupt*/ .long Reserved86_IRQHandler /* Reserved interrupt*/ - .long Reserved87_IRQHandler /* Reserved interrupt*/ + .long GPIO10_Combined_0_31_IRQHandler /* Combined interrupt indication for GPIO10 signal 0 throughout 31*/ .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ @@ -149,7 +149,7 @@ __isr_vector: .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ .long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/ .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ - .long SEMC_IRQHandler /* Reserved interrupt*/ + .long SEMC_IRQHandler /* SEMC interrupt*/ .long USDHC1_IRQHandler /* USDHC1 interrupt*/ .long USDHC2_IRQHandler /* USDHC2 interrupt*/ .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ @@ -281,7 +281,7 @@ __isr_vector: .long DefaultISR /* 254*/ .long 0xFFFFFFFF /* Reserved for user TRIM value*/ - .size __isr_vector, . - __isr_vector + .size __isr_vector, . - __isr_vector .text .thumb @@ -960,7 +960,6 @@ FLEXIO3_IRQHandler: .weak \handler_name .set \handler_name, DefaultISR .endm - /* Exception Handlers */ def_irq_handler MemManage_Handler def_irq_handler BusFault_Handler @@ -1037,7 +1036,7 @@ FLEXIO3_IRQHandler: def_irq_handler ADC2_IRQHandler def_irq_handler DCDC_IRQHandler def_irq_handler Reserved86_IRQHandler - def_irq_handler Reserved87_IRQHandler + def_irq_handler GPIO10_Combined_0_31_IRQHandler def_irq_handler GPIO1_INT0_IRQHandler def_irq_handler GPIO1_INT1_IRQHandler def_irq_handler GPIO1_INT2_IRQHandler diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor.icf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor.icf index 8d8829fdc7..3c50fb3f76 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor.icf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor.icf @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-** Version: rev. 0.1, 2017-01-10
-** Build: b210709
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2021 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor_sdram.icf index d17e603975..8794b4752c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_flexspi_nor_sdram.icf @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-** Version: rev. 0.1, 2017-01-10
-** Build: b210709
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2021 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_ram.icf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_ram.icf index 67dd06f1f8..08e8bb6793 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_ram.icf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_ram.icf @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-** Version: rev. 0.1, 2017-01-10
-** Build: b210709
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2021 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram.icf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram.icf index e34c78b409..6d3f522c0b 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram.icf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram.icf @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-** Version: rev. 0.1, 2017-01-10
-** Build: b210709
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2021 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram_txt.icf b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram_txt.icf index b0bf225617..6c4eb4c471 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram_txt.icf +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/MIMXRT1062xxxxx_sdram_txt.icf @@ -4,17 +4,19 @@ ** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
+** MIMXRT1062DVN6B
+** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-** Version: rev. 0.1, 2017-01-10
-** Build: b210709
+** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+** Version: rev. 0.2, 2022-03-25
+** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2021 NXP
+** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/startup_MIMXRT1062.s b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/startup_MIMXRT1062.s index e64f8114c7..0551d40402 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/startup_MIMXRT1062.s +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/iar/startup_MIMXRT1062.s @@ -2,13 +2,13 @@ ; @file: startup_MIMXRT1062.s ; @purpose: CMSIS Cortex-M7 Core Device Startup File ; MIMXRT1062 -; @version: 1.2 -; @date: 2019-4-29 -; @build: b200319 +; @version: 1.4 +; @date: 2022-3-25 +; @build: b220425 ; ------------------------------------------------------------------------- ; ; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2020 NXP +; Copyright 2016-2022 NXP ; All rights reserved. ; ; SPDX-License-Identifier: BSD-3-Clause @@ -140,7 +140,7 @@ __vector_table_0x1c DCD ADC2_IRQHandler ;ADC2 interrupt DCD DCDC_IRQHandler ;DCDC interrupt DCD Reserved86_IRQHandler ;Reserved interrupt - DCD Reserved87_IRQHandler ;Reserved interrupt + DCD GPIO10_Combined_0_31_IRQHandler ;Combined interrupt indication for GPIO10 signal 0 throughout 31 DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO @@ -178,7 +178,7 @@ __vector_table_0x1c DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt DCD FLEXSPI2_IRQHandler ;FlexSPI2 interrupt DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt - DCD SEMC_IRQHandler ;Reserved interrupt + DCD SEMC_IRQHandler ;SEMC interrupt DCD USDHC1_IRQHandler ;USDHC1 interrupt DCD USDHC2_IRQHandler ;USDHC2 interrupt DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 @@ -692,7 +692,7 @@ SPDIF_IRQHandler PUBWEAK ADC2_IRQHandler PUBWEAK DCDC_IRQHandler PUBWEAK Reserved86_IRQHandler - PUBWEAK Reserved87_IRQHandler + PUBWEAK GPIO10_Combined_0_31_IRQHandler PUBWEAK GPIO1_INT0_IRQHandler PUBWEAK GPIO1_INT1_IRQHandler PUBWEAK GPIO1_INT2_IRQHandler @@ -924,7 +924,7 @@ ADC1_IRQHandler ADC2_IRQHandler DCDC_IRQHandler Reserved86_IRQHandler -Reserved87_IRQHandler +GPIO10_Combined_0_31_IRQHandler GPIO1_INT0_IRQHandler GPIO1_INT1_IRQHandler GPIO1_INT2_IRQHandler diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.c index 8401a9e562..ad52864092 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.c @@ -1,10 +1,10 @@ //***************************************************************************** // MIMXRT1062 startup code for use with MCUXpresso IDE // -// Version : 150621 +// Version : 250422 //***************************************************************************** // -// Copyright 2016-2021 NXP +// Copyright 2016-2022 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -148,7 +148,7 @@ WEAK void ADC1_IRQHandler(void); WEAK void ADC2_IRQHandler(void); WEAK void DCDC_IRQHandler(void); WEAK void Reserved86_IRQHandler(void); -WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO10_Combined_0_31_IRQHandler(void); WEAK void GPIO1_INT0_IRQHandler(void); WEAK void GPIO1_INT1_IRQHandler(void); WEAK void GPIO1_INT2_IRQHandler(void); @@ -313,7 +313,7 @@ void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_Combined_0_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -432,20 +432,20 @@ void (* const g_pfnVectors[])(void) = { // Core Level - CM7 &_vStackTop, // The initial stack pointer ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler 0, // Reserved 0, // Reserved 0, // Reserved 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler // Chip Level - MIMXRT1062 DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete @@ -519,7 +519,7 @@ void (* const g_pfnVectors[])(void) = { ADC2_IRQHandler, // 84 : ADC2 interrupt DCDC_IRQHandler, // 85 : DCDC interrupt Reserved86_IRQHandler, // 86 : Reserved interrupt - Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO10_Combined_0_31_IRQHandler, // 87 : Combined interrupt indication for GPIO10 signal 0 throughout 31 GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO @@ -557,7 +557,7 @@ void (* const g_pfnVectors[])(void) = { PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt FLEXSPI2_IRQHandler, // 123: FlexSPI2 interrupt FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt - SEMC_IRQHandler, // 125: Reserved interrupt + SEMC_IRQHandler, // 125: SEMC interrupt USDHC1_IRQHandler, // 126: USDHC1 interrupt USDHC2_IRQHandler, // 127: USDHC2 interrupt USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 @@ -1074,8 +1074,8 @@ WEAK void Reserved86_IRQHandler(void) { Reserved86_DriverIRQHandler(); } -WEAK void Reserved87_IRQHandler(void) -{ Reserved87_DriverIRQHandler(); +WEAK void GPIO10_Combined_0_31_IRQHandler(void) +{ GPIO10_Combined_0_31_DriverIRQHandler(); } WEAK void GPIO1_INT0_IRQHandler(void) diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.cpp b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.cpp index 8401a9e562..ad52864092 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.cpp +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/mcuxpresso/startup_mimxrt1062.cpp @@ -1,10 +1,10 @@ //***************************************************************************** // MIMXRT1062 startup code for use with MCUXpresso IDE // -// Version : 150621 +// Version : 250422 //***************************************************************************** // -// Copyright 2016-2021 NXP +// Copyright 2016-2022 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -148,7 +148,7 @@ WEAK void ADC1_IRQHandler(void); WEAK void ADC2_IRQHandler(void); WEAK void DCDC_IRQHandler(void); WEAK void Reserved86_IRQHandler(void); -WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO10_Combined_0_31_IRQHandler(void); WEAK void GPIO1_INT0_IRQHandler(void); WEAK void GPIO1_INT1_IRQHandler(void); WEAK void GPIO1_INT2_IRQHandler(void); @@ -313,7 +313,7 @@ void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO10_Combined_0_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -432,20 +432,20 @@ void (* const g_pfnVectors[])(void) = { // Core Level - CM7 &_vStackTop, // The initial stack pointer ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - MemManage_Handler, // The MPU fault handler - BusFault_Handler, // The bus fault handler - UsageFault_Handler, // The usage fault handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler 0, // Reserved 0, // Reserved 0, // Reserved 0, // Reserved - SVC_Handler, // SVCall handler - DebugMon_Handler, // Debug monitor handler + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler + PendSV_Handler, // PendSV Handler + SysTick_Handler, // SysTick Handler // Chip Level - MIMXRT1062 DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete @@ -519,7 +519,7 @@ void (* const g_pfnVectors[])(void) = { ADC2_IRQHandler, // 84 : ADC2 interrupt DCDC_IRQHandler, // 85 : DCDC interrupt Reserved86_IRQHandler, // 86 : Reserved interrupt - Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO10_Combined_0_31_IRQHandler, // 87 : Combined interrupt indication for GPIO10 signal 0 throughout 31 GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO @@ -557,7 +557,7 @@ void (* const g_pfnVectors[])(void) = { PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt FLEXSPI2_IRQHandler, // 123: FlexSPI2 interrupt FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt - SEMC_IRQHandler, // 125: Reserved interrupt + SEMC_IRQHandler, // 125: SEMC interrupt USDHC1_IRQHandler, // 126: USDHC1 interrupt USDHC2_IRQHandler, // 127: USDHC2 interrupt USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 @@ -1074,8 +1074,8 @@ WEAK void Reserved86_IRQHandler(void) { Reserved86_DriverIRQHandler(); } -WEAK void Reserved87_IRQHandler(void) -{ Reserved87_DriverIRQHandler(); +WEAK void GPIO10_Combined_0_31_IRQHandler(void) +{ GPIO10_Combined_0_31_DriverIRQHandler(); } WEAK void GPIO1_INT0_IRQHandler(void) diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/board.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/board.c index 0b7d07e805..586741062c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/board.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/board.c @@ -258,7 +258,7 @@ void BOARD_ConfigMPU(void) * Use MACROS defined in mpu_armv7.h: * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache * 0 x 0 0 Strongly Ordered shareable * 0 x 0 1 Device shareable * 0 0 1 0 Normal not shareable Outer and inner write diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.c index 4f22bdc91e..3044416255 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.c @@ -4,6 +4,8 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler @@ -12,8 +14,8 @@ ** MCUXpresso Compiler ** ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 -** Version: rev. 1.3, 2021-08-10 -** Build: b210811 +** Version: rev. 1.4, 2022-03-25 +** Build: b220425 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -21,7 +23,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,14 +42,16 @@ ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. ** - rev. 1.3 (2021-08-10) ** Update header files to align with IMXRT1060RM Rev.3. +** - rev. 1.4 (2022-03-25) +** Add RT1060X device ** ** ################################################################### */ /*! * @file MIMXRT1062 - * @version 1.3 - * @date 2021-08-10 + * @version 1.4 + * @date 2022-03-25 * @brief Device specific configuration file for MIMXRT1062 (implementation file) * * Provides a system configuration function and a global variable that contains diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.h index 9607b3e118..3a89e63b15 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/system_MIMXRT1062.h @@ -4,6 +4,8 @@ ** MIMXRT1062CVL5A ** MIMXRT1062DVJ6A ** MIMXRT1062DVL6A +** MIMXRT1062DVN6B +** MIMXRT1062XVN5B ** ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler @@ -12,8 +14,8 @@ ** MCUXpresso Compiler ** ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0 -** Version: rev. 1.3, 2021-08-10 -** Build: b210811 +** Version: rev. 1.4, 2022-03-25 +** Build: b220425 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -21,7 +23,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,14 +42,16 @@ ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. ** - rev. 1.3 (2021-08-10) ** Update header files to align with IMXRT1060RM Rev.3. +** - rev. 1.4 (2022-03-25) +** Add RT1060X device ** ** ################################################################### */ /*! * @file MIMXRT1062 - * @version 1.3 - * @date 2021-08-10 + * @version 1.4 + * @date 2022-03-25 * @brief Device specific configuration file for MIMXRT1062 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.c index b73be3f75b..1efdbbbbdf 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.c @@ -73,7 +73,7 @@ #endif #endif -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) #define DEBUG_CONSOLE_FUNCTION_PREFIX #else #define DEBUG_CONSOLE_FUNCTION_PREFIX static @@ -282,7 +282,7 @@ int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); int DbgConsole_ReadLine(uint8_t *buf, size_t size); int DbgConsole_ReadCharacter(uint8_t *ch); -#if ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ +#if ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))) DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); #endif @@ -597,7 +597,7 @@ int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) sendDataLength = totalLength; } - sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength); + sentLength = DbgConsole_SendData(&ch[size - totalLength], (size_t)sendDataLength); if (sentLength > 0) { totalLength = totalLength - (uint32_t)sentLength; @@ -737,7 +737,7 @@ static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, { if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) { - (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator)); + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (size_t)(*indicator)); *indicator = 0; } @@ -757,15 +757,10 @@ static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG .baudRate = BOARD_DEBUG_UART_BAUDRATE, .parityMode = kSerialManager_UartParityDisabled, .stopBitCount = kSerialManager_UartOneStopBit, -#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - .mode = kSerialManager_UartBlockMode, -#endif -#endif - .enableRx = 1U, - .enableTx = 1U, - .enableRxRTS = 0U, - .enableTxCTS = 0U, + .enableRx = 1U, + .enableTx = 1U, + .enableRxRTS = 0U, + .enableTxCTS = 0U, #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) .txFifoWatermark = 0U, .rxFifoWatermark = 0U @@ -776,8 +771,8 @@ static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG /* See fsl_debug_console.h for documentation of this function. */ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) { - serial_manager_config_t serialConfig; - serial_manager_status_t status = kStatus_SerialManager_Success; + serial_manager_config_t serialConfig = {0}; + serial_manager_status_t status = kStatus_SerialManager_Success; #if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) #if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) @@ -787,15 +782,10 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t .baudRate = baudRate, .parityMode = kSerialManager_UartParityDisabled, .stopBitCount = kSerialManager_UartOneStopBit, -#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - .mode = kSerialManager_UartBlockMode, -#endif -#endif - .enableRx = 1, - .enableTx = 1, - .enableRxRTS = 0U, - .enableTxCTS = 0U, + .enableRx = 1, + .enableTx = 1, + .enableRxRTS = 0U, + .enableTxCTS = 0U, #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) .txFifoWatermark = 0U, .rxFifoWatermark = 0U @@ -1004,8 +994,8 @@ status_t DbgConsole_Deinit(void) } #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ -#if ((SDK_DEBUGCONSOLE > 0U) || \ - ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE > DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN))) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) { @@ -1044,7 +1034,7 @@ DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) } #endif -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) /* See fsl_debug_console.h for documentation of this function. */ int DbgConsole_Printf(const char *fmt_s, ...) { diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.h index 1aa16568bc..374148ff85 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console.h @@ -191,7 +191,7 @@ static inline status_t DbgConsole_ExitLowpower(void) #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) /*! * @brief Writes formatted output to the standard output stream. * diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.c index 0cad5f81fd..5388ae2be3 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.c @@ -43,7 +43,7 @@ typedef struct DebugConsoleState hal_uart_status_t (*getChar)(hal_uart_handle_t handle, uint8_t *data, size_t length); /*!< get char function pointer */ - serial_port_type_t type; /*!< The initialized port of the debug console. */ + serial_port_type_t serial_port_type; /*!< The initialized port of the debug console. */ } debug_console_state_t; /*! @brief Type of KSDK printf function pointer. */ @@ -91,13 +91,14 @@ enum _debugconsole_scanf_flag /******************************************************************************* * Variables ******************************************************************************/ +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) /*! @brief Debug UART state information. */ static debug_console_state_t s_debugConsole; - +#endif /******************************************************************************* * Prototypes ******************************************************************************/ -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap); static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr); #endif /* SDK_DEBUGCONSOLE */ @@ -120,7 +121,7 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t } /* Set debug console to initialized to avoid duplicated initialized operation. */ - s_debugConsole.type = device; + s_debugConsole.serial_port_type = device; usrtConfig.srcClock_Hz = clkSrcFreq; usrtConfig.baudRate_Bps = baudRate; @@ -147,20 +148,20 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t /* See fsl_debug_console.h for documentation of this function. */ status_t DbgConsole_Deinit(void) { - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return kStatus_Success; } (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); - s_debugConsole.type = kSerialPort_None; + s_debugConsole.serial_port_type = kSerialPort_None; return kStatus_Success; } #endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */ -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) /* See fsl_debug_console.h for documentation of this function. */ int DbgConsole_Printf(const char *fmt_s, ...) { @@ -180,7 +181,7 @@ int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) int result = 0; /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -194,7 +195,7 @@ int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) int DbgConsole_Putchar(int ch) { /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -213,7 +214,7 @@ int DbgConsole_Scanf(char *fmt_s, ...) char result; /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -267,7 +268,7 @@ int DbgConsole_Getchar(void) { char ch; /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1170,7 +1171,7 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt } p++; } - return count; + return (int)count; } /*! @@ -1685,7 +1686,7 @@ size_t __write(int handle, const unsigned char *buffer, size_t size) */ ret = (size_t)-1; } - else if (kSerialPort_None == s_debugConsole.type) + else if (kSerialPort_None == s_debugConsole.serial_port_type) { /* Do nothing if the debug UART is not initialized. */ ret = (size_t)-1; @@ -1709,7 +1710,7 @@ size_t __read(int handle, unsigned char *buffer, size_t size) { ret = ((size_t)-1); } - else if (kSerialPort_None == s_debugConsole.type) + else if (kSerialPort_None == s_debugConsole.serial_port_type) { /* Do nothing if the debug UART is not initialized. */ ret = ((size_t)-1); @@ -1743,7 +1744,7 @@ int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) } /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1758,7 +1759,7 @@ int __attribute__((weak)) __sys_readc(void) { char tmp; /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1794,7 +1795,7 @@ FILE __stdin; int fputc(int ch, FILE *f) { /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1809,7 +1810,7 @@ int fgetc(FILE *f) { char ch; /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1867,7 +1868,7 @@ int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size } /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1888,7 +1889,7 @@ int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size) } /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1920,7 +1921,7 @@ int __attribute__((weak)) _write(int handle, char *buffer, int size) } /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } @@ -1941,7 +1942,7 @@ int __attribute__((weak)) _read(int handle, char *buffer, int size) } /* Do nothing if the debug UART is not initialized. */ - if (kSerialPort_None == s_debugConsole.type) + if (kSerialPort_None == s_debugConsole.serial_port_type) { return -1; } diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.h index 707e4249a0..72f9a86d18 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console_lite/fsl_debug_console.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2018, 2020 NXP + * Copyright 2017-2018, 2020, 2022 NXP * All rights reserved. * * @@ -24,8 +24,8 @@ #include "fsl_common.h" -/* - * @addtogroup debugconsole +/*! + * @addtogroup debugconsolelite * @{ */ @@ -76,10 +76,14 @@ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. */ #if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ -#define PRINTF -#define SCANF -#define PUTCHAR -#define GETCHAR +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() #elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ #define PRINTF DbgConsole_Printf #define SCANF DbgConsole_Scanf @@ -92,13 +96,33 @@ #define PUTCHAR putchar #define GETCHAR getchar #endif /* SDK_DEBUGCONSOLE */ +/*! @} */ +/*! @brief serial port type + * + * The serial port type aligned with the definition in serial manager, but please note + * only kSerialPort_Uart can be supported in debug console lite. + */ +#ifndef _SERIAL_PORT_T_ +#define _SERIAL_PORT_T_ typedef enum _serial_port_type { kSerialPort_None = 0U, /*!< Serial port is none */ kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_Virtual, /*!< Serial port Virtual */ + kSerialPort_Rpmsg, /*!< Serial port RPMSG */ + kSerialPort_UartDma, /*!< Serial port UART DMA*/ + kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/ + kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/ } serial_port_type_t; +#endif +/*! + * @addtogroup debugconsolelite + * @{ + */ /******************************************************************************* * Prototypes ******************************************************************************/ @@ -173,7 +197,7 @@ static inline status_t DbgConsole_Deinit(void) #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ -#if SDK_DEBUGCONSOLE +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) /*! * @brief Writes formatted output to the standard output stream. * @@ -233,5 +257,4 @@ int DbgConsole_Getchar(void); #endif /* __cplusplus */ /*! @} */ - #endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_memcpy.S b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_memcpy.S new file mode 100644 index 0000000000..de2b4d674d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_memcpy.S @@ -0,0 +1,279 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .syntax unified + + .text + .thumb + + .align 2 + +#ifndef MSDK_MISC_OVERRIDE_MEMCPY +#define MSDK_MISC_OVERRIDE_MEMCPY 1 +#endif + +/* + This mempcy function is used to replace the GCC newlib function for these purposes: + 1. The newlib nano memcpy function use byte by byte copy, it is slow. + 2. The newlib memcpy function for CM4, CM7, CM33 does't check address alignment, + so it may run to fault when the address is unaligned, and the memory region + is device memory, which does not support unaligned access. + + This function is manually optimized base on assembly result of the c function. + The workflow is: + 1. Return directly if length is 0. + 2. If the source address is not 4-byte aligned, copy the unaligned part first byte by byte. + 3. If the destination address is 4-byte aligned, then copy the 16-byte aligned part first, + copy 16-byte each loop, and then copy 8-byte, 4-byte, 2-byte and 1-byte. + 4. If the destination address is not 4-byte aligned, load source data into register word + by word first, then store to memory based on alignement requirement. For the left part, + copy them byte by byte. + + The source code of the c function is: + + #define __CPY_WORD(dst, src) \ + *(uint32_t *)(dst) = *(uint32_t *)(src); \ + (dst) = ((uint32_t *)dst) + 1; \ + (src) = ((uint32_t *)src) + 1 + + #define __CPY_HWORD(dst, src) \ + *(uint16_t *)(dst) = *(uint16_t *)(src); \ + (dst) = ((uint16_t *)dst) + 1; \ + (src) = ((uint16_t *)src) + 1 + + #define __CPY_BYTE(dst, src) \ + *(uint8_t *)(dst) = *(uint8_t *)(src); \ + (dst) = ((uint8_t *)dst) + 1; \ + (src) = ((uint8_t *)src) + 1 + + void * memcpy(void *restrict dst, const void * restrict src, size_t n) + { + void *ret = dst; + uint32_t tmp; + + if (0 == n) return ret; + + while (((uintptr_t)src & 0x03UL) != 0UL) + { + __CPY_BYTE(dst, src); + n--; + + if (0 == n) return ret; + } + + if (((uintptr_t)dst & 0x03UL) == 0UL) + { + while (n >= 16UL) + { + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + n-= 16UL; + } + + if ((n & 0x08UL) != 0UL) + { + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + } + + if ((n & 0x04UL) != 0UL) + { + __CPY_WORD(dst, src); + } + + if ((n & 0x02UL) != 0UL) + { + __CPY_HWORD(dst, src); + } + + if ((n & 0x01UL) != 0UL) + { + __CPY_BYTE(dst, src); + } + } + else + { + if (((uintptr_t)dst & 1UL) == 0UL) + { + while (n >= 4) + { + tmp = *(uint32_t *)src; + src = ((uint32_t *)src) + 1; + + *(volatile uint16_t *)dst = (uint16_t)tmp; + dst = ((uint16_t *)dst) + 1; + *(volatile uint16_t *)dst = (uint16_t)(tmp>>16U); + dst = ((uint16_t *)dst) + 1; + + n-=4; + } + } + else + { + while (n >= 4) + { + tmp = *(uint32_t *)src; + src = ((uint32_t *)src) + 1; + + *(volatile uint8_t *)dst = (uint8_t)tmp; + dst = ((uint8_t *)dst) + 1; + *(volatile uint16_t *)dst = (uint16_t)(tmp>>8U); + dst = ((uint16_t *)dst) + 1; + *(volatile uint8_t *)dst = (uint8_t)(tmp>>24U); + dst = ((uint8_t *)dst) + 1; + n-=4; + } + } + + while (n > 0) + { + __CPY_BYTE(dst, src); + n--; + } + } + + return ret; + } + + The test function is: + + void test_memcpy(uint8_t *dst, const uint8_t * src, size_t n) + { + uint8_t * ds; + uint8_t * de; + const uint8_t *ss; + const uint8_t *se; + uint8_t * ret; + + for (ss = src; ss < src+n; ss++) + { + for (se = ss; se < src + n; se ++) + { + size_t nn = (uintptr_t)se - (uintptr_t)ss; + + for (ds = dst; ds + nn < dst+n; ds++) + { + de = ds + nn; + + memset(dst, 0, n); + + ret = memcpy(ds, ss, nn); + + assert(ret == ds); + + for (const uint8_t *data = dst; data < ds; data++) + { + assert(0 == *data); + } + + for (const uint8_t *data = de; data < dst+n; data++) + { + assert(0 == *data); + } + + assert(memcmp(ds, ss, nn) == 0); + } + } + } + } + + test_memcpy((uint8_t *)0x20240000, (const uint8_t *)0x202C0000, 48); + + */ + +#if MSDK_MISC_OVERRIDE_MEMCPY + + .thumb_func + .align 2 + .global memcpy + .type memcpy, %function + +memcpy: + push {r0, r4, r5, r6, r7, lr} + cmp r2, #0 + beq ret /* If copy size is 0, return. */ + +src_word_unaligned: + ands r3, r1, #3 /* Make src 4-byte align. */ + beq.n src_word_aligned /* src is 4-byte aligned, jump. */ + ldrb r4, [r1], #1 + subs r2, r2, #1 /* n-- */ + strb r4, [r0], #1 + beq.n ret /* n=0, return. */ + b.n src_word_unaligned + +src_word_aligned: + ands r3, r0, #3 /* Check dest 4-byte align. */ + bne.n dst_word_unaligned + +dst_word_aligned: + cmp r2, #16 + blt.n size_ge_8 +size_ge_16: /* size greater or equal than 16, use ldm and stm. */ + subs r2, r2, #16 /* n -= 16 */ + ldmia r1!, { r4, r5, r6, r7 } + cmp r2, #16 + stmia r0!, { r4, r5, r6, r7 } + bcs.n size_ge_16 +size_ge_8: /* size greater or equal than 8 */ + lsls r3, r2, #28 + itt mi + ldmiami r1!, { r4, r5 } + stmiami r0!, { r4, r5 } +size_ge_4: /* size greater or equal than 4 */ + lsls r3, r2, #29 + itt mi + ldrmi r4, [r1], #4 + strmi r4, [r0], #4 +size_ge_2: /* size greater or equal than 2 */ + lsls r3, r2, #30 + itt mi + ldrhmi r4, [r1], #2 + strhmi r4, [r0], #2 +size_ge_1: /* size greater or equal than 1 */ + lsls r3, r2, #31 + itt mi + ldrbmi r4, [r1] + strbmi r4, [r0] + b.n ret + +dst_word_unaligned: + lsls r3, r0, #31 + bmi.n dst_half_word_unaligned +dst_half_word_aligned: + cmp r2, #4 + bcc.n size_lt_4 + ldr r4, [r1], #4 + subs r2, r2, #4 + strh r4, [r0], #2 + lsrs r5, r4, #16 + strh r5, [r0], #2 + b dst_half_word_aligned +dst_half_word_unaligned: + cmp r2, #4 + bcc.n size_lt_4 + ldr r4, [r1], #4 + subs r2, r2, #4 + strb r4, [r0], #1 + lsrs r5, r4, #8 + strh r5, [r0], #2 + lsrs r6, r4, #24 + strb r6, [r0], #1 + b dst_half_word_unaligned +size_lt_4: /* size less than 4. */ + cmp r2, #0 + ittt ne + ldrbne r4, [r1], #1 + strbne r4, [r0], #1 + subne r2, r2, #1 + bne size_lt_4 +ret: + pop {r0, r4, r5, r6, r7, pc} + +#endif /* MSDK_MISC_OVERRIDE_MEMCPY */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_sbrk.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_sbrk.c index 5727b2f869..55363fd59e 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_sbrk.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_sbrk.c @@ -35,7 +35,7 @@ caddr_t _sbrk(int incr) prev_heap_end = heap_end; - if ((unsigned int)heap_end + (unsigned int)incr > (unsigned int)(&heap_limit)) + if ((uintptr_t)heap_end + (uintptr_t)incr > (uintptr_t)(&heap_limit)) { errno = ENOMEM; @@ -43,7 +43,7 @@ caddr_t _sbrk(int incr) } else { - heap_end = (char *)((unsigned int)heap_end + (unsigned int)incr); + heap_end = (char *)((uintptr_t)heap_end + (uintptr_t)incr); ret = (caddr_t)prev_heap_end; } diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_shell.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_shell.c index 6d092f1286..5057050a29 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_shell.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/fsl_shell.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -972,7 +972,7 @@ shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHand (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(help)); (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(exit)); SHELL_MUTEX_CREATE(); - (void)SHELL_Write(shellContextHandle, "\r\nCopyright 2020 NXP\r\n", strlen("\r\nCopyright 2020 NXP\r\n")); + (void)SHELL_Write(shellContextHandle, "\r\nCopyright 2022 NXP\r\n", strlen("\r\nCopyright 2022 NXP\r\n")); SHELL_PrintPrompt(shellContextHandle); return kStatus_SHELL_Success; diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/str/fsl_str.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/str/fsl_str.c index fcd9ae8159..1c0dccf905 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/str/fsl_str.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/str/fsl_str.c @@ -1062,7 +1062,7 @@ int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) p++; } - return count; + return (int)count; } #if SCANF_FLOAT_ENABLE diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/xip/fsl_flexspi_nor_boot.h index c76afeceb7..38d5d1833e 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/xip/fsl_flexspi_nor_boot.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/xip/fsl_flexspi_nor_boot.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -9,13 +9,15 @@ #define __FLEXSPI_NOR_BOOT_H__ #include <stdint.h> -#include "board.h" #include "fsl_common.h" +#ifndef BOARD_FLASH_SIZE +#include "board.h" +#endif /*! @name Driver version */ /*@{*/ -/*! @brief XIP_DEVICE driver version 2.0.2. */ -#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief XIP_DEVICE driver version 2.0.3. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /************************************* @@ -100,7 +102,12 @@ typedef struct _boot_data_ uint32_t placeholder; /* placehoder to make even 0x10 size */ } BOOT_DATA_T; +#ifdef FlexSPI1_AMBA_BASE +#define FLASH_BASE FlexSPI1_AMBA_BASE +#else #define FLASH_BASE FlexSPI_AMBA_BASE +#endif + #if defined(BOARD_FLASH_SIZE) #define FLASH_SIZE BOARD_FLASH_SIZE #else diff --git a/bsp/imxrt/libraries/MIMXRT1060/SConscript b/bsp/imxrt/libraries/MIMXRT1060/SConscript index 707f78f660..f17ae03486 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/SConscript +++ b/bsp/imxrt/libraries/MIMXRT1060/SConscript @@ -103,8 +103,8 @@ src += ['MIMXRT1060/drivers/fsl_xbara.c'] src += ['MIMXRT1060/drivers/fsl_xbarb.c'] # #fsl os abstract files -# src += ['MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c'] -# src += ['MIMXRT1060/drivers/generic_list.c'] +src += ['MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c'] +src += ['MIMXRT1060/drivers/generic_list.c'] if rtconfig.PLATFORM in ['gcc']: group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS') diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index 695e143d60..df22eab181 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -30,13 +30,10 @@ #include <netif/ethernetif.h> #include "lwipopts.h" -#ifdef SOC_IMXRT1170_SERIES + #define ENET_RXBD_NUM (5) #define ENET_TXBD_NUM (3) -#else -#define ENET_RXBD_NUM (4) -#define ENET_TXBD_NUM (4) -#endif + #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) @@ -52,20 +49,21 @@ #define DBG_LEVEL DBG_INFO #include <rtdbg.h> +#define RING_ID 0 +#define ENET_RING_NUM 1U #define MAX_ADDR_LEN 6 -#ifdef SOC_IMXRT1170_SERIES -#define ENET_RING_NUM 1U -#define RING_ID 0 +//#ifdef SOC_IMXRT1170_SERIES + typedef uint8_t rx_buffer_t[RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; typedef uint8_t tx_buffer_t[RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; #ifndef ENET_RXBUFF_NUM #define ENET_RXBUFF_NUM (ENET_RXBD_NUM * 2) #endif -#endif +//#endif -#ifdef SOC_IMXRT1170_SERIES +//#ifdef SOC_IMXRT1170_SERIES typedef void (*pbuf_free_custom_fn)(struct pbuf *p); /** A custom pbuf: like a pbuf, but following a function pointer to free it. */ @@ -84,7 +82,7 @@ typedef struct rx_pbuf_wrapper volatile bool buffer_used; /*!< Wrapped buffer is used by ENET */ } rx_pbuf_wrapper_t; -#endif +//#endif struct rt_imxrt_eth { /* inherit from ethernet device */ @@ -102,22 +100,41 @@ struct rt_imxrt_eth enet_mii_speed_t speed; enet_mii_duplex_t duplex; -#ifdef SOC_IMXRT1170_SERIES +//#ifdef SOC_IMXRT1170_SERIES enet_rx_bd_struct_t *RxBuffDescrip; enet_tx_bd_struct_t *TxBuffDescrip; rx_buffer_t *RxDataBuff; tx_buffer_t *TxDataBuff; rx_pbuf_wrapper_t RxPbufs[ENET_RXBUFF_NUM]; -#endif +//#endif }; +//#if defined(__ICCARM__) /* IAR Workbench */ +//#pragma location = "enet_mem_section" +//ALIGN(ENET_BUFF_ALIGNMENT) +//static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM]; +// +//ALIGN(ENET_BUFF_ALIGNMENT) +//rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; +// +//#pragma location = "enet_mem_section" +//ALIGN(ENET_BUFF_ALIGNMENT) +//static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM]; +// +//ALIGN(ENET_BUFF_ALIGNMENT) +//rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; +// +//#else AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT); + rt_align(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT); rt_align(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; +//#endif + static struct rt_imxrt_eth imxrt_eth_device; @@ -142,7 +159,6 @@ void _enet_tx_callback(struct rt_imxrt_eth *eth) } } -#ifdef SOC_IMXRT1170_SERIES static void _enet_callback(ENET_Type *base, enet_handle_t *handle, #if FSL_FEATURE_ENET_QUEUE > 1 @@ -151,9 +167,6 @@ static void _enet_callback(ENET_Type *base, enet_event_t event, enet_frame_info_t *frameInfo, void *userData) -#else -void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) -#endif { switch (event) { @@ -219,15 +232,21 @@ static void _enet_clk_init(void) IOMUXC_GPR->GPR4 |= 0x3; #endif #else - const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1}; +// const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1}; +// CLOCK_InitEnetPll(&config); +// +// IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); +// IOMUXC_GPR->GPR1 |= 1 << 23; + /* Set 50MHz output clock required by PHY. */ + const clock_enet_pll_config_t config = {.enableClkOutput = true, .loopDivider = 1}; CLOCK_InitEnetPll(&config); + /* Output 50M clock to PHY. */ IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); - IOMUXC_GPR->GPR1 |= 1 << 23; #endif } -#ifdef SOC_IMXRT1170_SERIES +//#ifdef SOC_IMXRT1170_SERIES static void *_enet_rx_alloc(ENET_Type *base, void *userData, uint8_t ringId) { void *buffer = NULL; @@ -280,7 +299,7 @@ static void _enet_rx_release(struct pbuf *p) rx_pbuf_wrapper_t *wrapper = (rx_pbuf_wrapper_t *)p; _enet_rx_free(imxrt_eth_device.enet_base, wrapper->buffer, &imxrt_eth_device, 0); } -#endif +//#endif static void _enet_config(void) { @@ -288,42 +307,61 @@ static void _enet_config(void) uint32_t sysClock; /* prepare the buffer configuration. */ -#ifndef SOC_IMXRT1170_SERIES - enet_buffer_config_t buffConfig = - { - ENET_RXBD_NUM, - ENET_TXBD_NUM, - SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - &g_rxBuffDescrip[0], - &g_txBuffDescrip[0], - &g_rxDataBuff[0][0], - &g_txDataBuff[0][0], - }; - /* Get default configuration. */ - /* - * config.miiMode = kENET_RmiiMode; - * config.miiSpeed = kENET_MiiSpeed100M; - * config.miiDuplex = kENET_MiiFullDuplex; - * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; - */ - ENET_GetDefaultConfig(&config); - config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; - config.miiSpeed = imxrt_eth_device.speed; - config.miiDuplex = imxrt_eth_device.duplex; - - /* Set SMI to get PHY link status. */ - sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); - - dbg_log(DBG_LOG, "deinit\n"); - ENET_Deinit(imxrt_eth_device.enet_base); - dbg_log(DBG_LOG, "init\n"); - ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); - dbg_log(DBG_LOG, "set call back\n"); - ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); - dbg_log(DBG_LOG, "active read\n"); - ENET_ActiveRead(imxrt_eth_device.enet_base); -#else +//#ifndef SOC_IMXRT1170_SERIES +// enet_buffer_config_t buffConfig[] = +// { +// ENET_RXBD_NUM, +// ENET_TXBD_NUM, +// SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), +// SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), +// &g_rxBuffDescrip[0], +// &g_txBuffDescrip[0], +// &g_rxDataBuff[0][0], +// &g_txDataBuff[0][0], +// }; +// /* Get default configuration. */ +// /* +// * config.miiMode = kENET_RmiiMode; +// * config.miiSpeed = kENET_MiiSpeed100M; +// * config.miiDuplex = kENET_MiiFullDuplex; +// * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +// */ +// +// ENET_GetDefaultConfig(&config); +// config.ringNum = ENET_RING_NUM; +// config.miiSpeed = imxrt_eth_device.speed; +// config.miiDuplex = imxrt_eth_device.duplex; +// +////#ifdef PHY_USING_RTL8211F +//// config.miiMode = kENET_RgmiiMode; +//// EnableIRQ(ENET_1G_MAC0_Tx_Rx_1_IRQn); +//// EnableIRQ(ENET_1G_MAC0_Tx_Rx_2_IRQn); +////#else +//// config.miiMode = kENET_RmiiMode; +////#endif +// +// +// config.interrupt |= kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; +// config.callback = _enet_callback; +// +//// ENET_GetDefaultConfig(&config); +// config.ringNum = ENET_RING_NUM; +//// config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; +// config.miiSpeed = imxrt_eth_device.speed; +// config.miiDuplex = imxrt_eth_device.duplex; +// +// /* Set SMI to get PHY link status. */ +// sysClock = CLOCK_GetFreq(kCLOCK_IpgClk); +// +// dbg_log(DBG_LOG, "deinit\n"); +// ENET_Deinit(imxrt_eth_device.enet_base); +// dbg_log(DBG_LOG, "init\n"); +// ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig[0], &imxrt_eth_device.dev_addr[0], sysClock); +//// dbg_log(DBG_LOG, "set call back\n"); +//// ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); +// dbg_log(DBG_LOG, "active read\n"); +// ENET_ActiveRead(imxrt_eth_device.enet_base); +//#else int i; enet_buffer_config_t buffConfig[ENET_RING_NUM]; imxrt_eth_device.RxBuffDescrip = &g_rxBuffDescrip[0]; @@ -366,9 +404,12 @@ static void _enet_config(void) config.rxBuffAlloc = _enet_rx_alloc; config.rxBuffFree = _enet_rx_free; config.userData = &imxrt_eth_device; +#ifdef SOC_IMXRT1170_SERIES /* Set SMI to get PHY link status. */ sysClock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); - +#else + sysClock = CLOCK_GetFreq(kCLOCK_IpgClk); +#endif config.interrupt |= kENET_TxFrameInterrupt | kENET_RxFrameInterrupt | kENET_TxBufferInterrupt | kENET_LateCollisionInterrupt; config.callback = _enet_callback; @@ -387,7 +428,7 @@ static void _enet_config(void) // ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); dbg_log(DBG_LOG, "active read\n"); ENET_ActiveRead(imxrt_eth_device.enet_base); -#endif +//#endif } #if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) @@ -482,7 +523,6 @@ static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) return RT_EOK; } -#ifdef SOC_IMXRT1170_SERIES static bool _ENET_TxDirtyRingAvailable(enet_tx_dirty_ring_t *txDirtyRing) { return !txDirtyRing->isFull; @@ -546,32 +586,7 @@ static void _ENET_ActiveSendRing(ENET_Type *base, uint8_t ringId) /* Write to active tx descriptor */ *txDesActive = 0; } -#else -static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId) -{ - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - switch (ringId) - { - case 0: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; -#if FSL_FEATURE_ENET_QUEUE > 1 - case 1: - base->TDAR1 = ENET_TDAR1_TDAR_MASK; - break; - case 2: - base->TDAR2 = ENET_TDAR2_TDAR_MASK; - break; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - default: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; - } -} -#endif -#ifdef SOC_IMXRT1170_SERIES static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, @@ -703,7 +718,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, if (sizeleft > handle->txBuffSizeAlign[ringId]) { /* Data copy. */ - (void)rt_memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, + (void)memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, handle->txBuffSizeAlign[ringId]); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL if (handle->txMaintainEnable[ringId]) @@ -733,7 +748,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, } else { - (void)rt_memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, sizeleft); + (void)memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, sizeleft); #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL if (handle->txMaintainEnable[ringId]) { @@ -778,166 +793,6 @@ static status_t _ENET_SendFrame(ENET_Type *base, } return result; } -#else -static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) -{ - assert(handle); - assert(data); - - volatile enet_tx_bd_struct_t *curBuffDescrip; - uint32_t len = 0; - uint32_t sizeleft = 0; - uint32_t address; - - /* Check the frame length. */ - if (length > ENET_FRAME_MAX_FRAMELEN) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Check if the transmit buffer is ready. */ - curBuffDescrip = handle->txBdCurrent[0]; - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - bool isPtpEventMessage = false; - /* Check PTP message with the PTP header. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* One transmit buffer is enough for one frame. */ - if (handle->txBuffSizeAlign[0] >= length) - { - /* Copy data to the buffer for uDMA transfer. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - - pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); - - /* Set data length. */ - curBuffDescrip->length = length; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - else - { - /* One frame requires more than one transmit buffers. */ - do - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } - /* update the size left to be transmit. */ - sizeleft = length - len; - if (sizeleft > handle->txBuffSizeAlign[0]) - { - /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - rt_memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); - /* Data length update. */ - curBuffDescrip->length = handle->txBuffSizeAlign[0]; - len += handle->txBuffSizeAlign[0]; - /* Sets the control flag. */ - curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; - /* Active the transmit buffer descriptor*/ - _ENET_ActiveSend(base, 0); - } - else - { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - rt_memcpy((void *)address, data + len, sizeleft); - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - - /* Get the current buffer descriptor address. */ - curBuffDescrip = handle->txBdCurrent[0]; - - } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); - - return kStatus_ENET_TxFrameBusy; - } -} -#endif /* ethernet device interface */ /* transmit packet. */ @@ -957,11 +812,7 @@ rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) do { -#ifdef SOC_IMXRT1170_SERIES result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len, RING_ID, false, NULL); -#else - result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); -#endif if (result == kStatus_ENET_TxFrameBusy) { @@ -986,11 +837,7 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; /* Get the Frame size */ -#ifdef SOC_IMXRT1170_SERIES status = ENET_GetRxFrameSize(enet_handle, &length, RING_ID); -#else - status = ENET_GetRxFrameSize(enet_handle, &length); -#endif /* Call ENET_ReadFrame when there is a received frame. */ if (length != 0) @@ -1000,11 +847,8 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) if (p != NULL) { -#ifdef SOC_IMXRT1170_SERIES status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length, RING_ID, NULL); -#else - status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); -#endif + if (status == kStatus_Success) { #ifdef ETH_RX_DUMP @@ -1027,17 +871,11 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) { dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); /* Update the received buffer when error happened. */ -#ifdef SOC_IMXRT1170_SERIES + /* Get the error information of the received g_frame. */ ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic, RING_ID); /* update the receive buffer. */ ENET_ReadFrame(enet_base, enet_handle, NULL, 0, RING_ID, NULL); -#else - /* Get the error information of the received g_frame. */ - ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); - /* update the receive buffer. */ - ENET_ReadFrame(enet_base, enet_handle, NULL, 0); -#endif } ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); @@ -1071,7 +909,7 @@ static void phy_monitor_thread_entry(void *parameter) } #endif #else - phy_dev = (struct rt_phy_device *)rt_device_find("rtt-phy"); + phy_dev = (struct rt_phy_device *)rt_device_find("ksz8081"); if ((RT_NULL == phy_dev) || (RT_NULL == phy_dev->ops)) { // TODO print warning information @@ -1092,7 +930,7 @@ static void phy_monitor_thread_entry(void *parameter) rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_KSZ8081_ADDRESS, CLOCK_GetRootClockFreq(kCLOCK_Root_Bus)); #endif #else - rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_DEVICE_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_KSZ8081_ADDRESS, CLOCK_GetFreq(kCLOCK_IpgClk)); #endif if (PHY_STATUS_OK != status) { @@ -1158,6 +996,7 @@ static void phy_monitor_thread_entry(void *parameter) } rt_thread_delay(RT_TICK_PER_SECOND * 2); +// rt_thread_mdelay(300); } } #endif @@ -1178,19 +1017,19 @@ static int rt_hw_imxrt_eth_init(void) imxrt_eth_device.dev_addr[4] = 0x22; imxrt_eth_device.dev_addr[5] = 0x33; - imxrt_eth_device.speed = kENET_MiiSpeed1000M; + imxrt_eth_device.speed = kENET_MiiSpeed100M;//Ҫ֧��ǧ�ף�ֱ�ӽ���ֵ��ΪkENET_MiiSpeed1000M imxrt_eth_device.duplex = kENET_MiiFullDuplex; imxrt_eth_device.enet_base = ENET_1G; #else /* NXP (Freescale) MAC OUI */ - imxrt_eth_device.dev_addr[0] = 0x00; - imxrt_eth_device.dev_addr[1] = 0x04; - imxrt_eth_device.dev_addr[2] = 0x9F; + imxrt_eth_device.dev_addr[0] = 0x54; + imxrt_eth_device.dev_addr[1] = 0x27; + imxrt_eth_device.dev_addr[2] = 0x8d; /* generate MAC addr from 96bit unique ID (only for test). */ - imxrt_eth_device.dev_addr[3] = 0x05; - imxrt_eth_device.dev_addr[4] = 0x44; - imxrt_eth_device.dev_addr[5] = 0xE5; + imxrt_eth_device.dev_addr[3] = 0x00; + imxrt_eth_device.dev_addr[4] = 0x00; + imxrt_eth_device.dev_addr[5] = 0x00; imxrt_eth_device.speed = kENET_MiiSpeed100M; imxrt_eth_device.duplex = kENET_MiiFullDuplex; @@ -1238,7 +1077,8 @@ static int rt_hw_imxrt_eth_init(void) phy_monitor_thread_entry, RT_NULL, 4096, - RT_THREAD_PRIORITY_MAX - 2, + /*RT_THREAD_PRIORITY_MAX - 2,*/ + 15, 2); if (tid != RT_NULL) rt_thread_startup(tid); @@ -1368,7 +1208,7 @@ void enet_reg_dump(void) DUMP_REG(RMON_T_P1024TO2047); DUMP_REG(RMON_T_P_GTE2048); DUMP_REG(RMON_T_OCTETS); - DUMP_REG(IEEE_T_DROP); +// DUMP_REG(IEEE_T_DROP); DUMP_REG(IEEE_T_FRAME_OK); DUMP_REG(IEEE_T_1COL); DUMP_REG(IEEE_T_MCOL); diff --git a/bsp/imxrt/libraries/drivers/drv_ksz8081.c b/bsp/imxrt/libraries/drivers/drv_ksz8081.c index 3d89bdd86f..1a4c2aaf2a 100644 --- a/bsp/imxrt/libraries/drivers/drv_ksz8081.c +++ b/bsp/imxrt/libraries/drivers/drv_ksz8081.c @@ -72,12 +72,7 @@ #define PHY_TIMEOUT_COUNT 0x3FFFFFFU /* defined the Reset pin, PORT and PIN config by menuconfig */ -#ifdef SOC_IMXRT1170_SERIES #define RESET_PIN GET_PIN(PHY_RESET_KSZ8081_PORT, PHY_RESET_KSZ8081_PIN) -#else -#define RESET_PIN GET_PIN(PHY_RESET_PORT, PHY_RESET_PIN) -#endif - /******************************************************************************* * Prototypes diff --git a/bsp/imxrt/libraries/drivers/drv_sdio.c b/bsp/imxrt/libraries/drivers/drv_sdio.c index 6cd2817bcd..bac2766639 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdio.c +++ b/bsp/imxrt/libraries/drivers/drv_sdio.c @@ -60,14 +60,13 @@ static int enable_log = 1; /* Endian mode. */ #define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle -#ifdef SOC_IMXRT1170_SERIES +//#ifdef SOC_IMXRT1170_SERIES #define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */ #define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ -#else -#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN 0 -#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ -#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ -#endif +//#else +//#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +//#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +//#endif //rt_align(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable"); AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN); @@ -138,7 +137,7 @@ static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd) static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd) { CLOCK_EnableClock(mmcsd->ip_clock); -#ifndef SOC_IMXRT1170_SERIES +#if !defined(SOC_IMXRT1170_SERIES) && !defined(SOC_MIMXRT1062DVL6A) CLOCK_SetDiv(mmcsd->usdhc_div, 5U); #endif } @@ -362,6 +361,14 @@ static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *i rootCfg.div = 2; CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); src_clk = CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1); +#elif defined(SOC_MIMXRT1062DVL6A) + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + /* Configure USDHC clock source and divider */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); + src_clk = 396000000U / 2U; #else src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U)); #endif @@ -403,7 +410,10 @@ rt_int32_t _imxrt_mci_init(void) { struct rt_mmcsd_host *host; struct imxrt_mmcsd *mmcsd; + +#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE)) uint32_t hs400Capability = 0U; +#endif host = mmcsd_alloc_host(); if (!host) @@ -420,9 +430,9 @@ rt_int32_t _imxrt_mci_init(void) rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd)); mmcsd->usdhc_host.base = USDHC1; -#ifndef SOC_IMXRT1170_SERIES - mmcsd->usdhc_div = kCLOCK_Usdhc1Div; -#endif +//#ifndef SOC_IMXRT1170_SERIES +// mmcsd->usdhc_div = kCLOCK_Usdhc1Div; +//#endif mmcsd->usdhc_adma2_table = g_usdhcAdma2Table; host->ops = &ops; @@ -431,8 +441,8 @@ rt_int32_t _imxrt_mci_init(void) host->valid_ocr = VDD_32_33 | VDD_33_34; host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; -#ifdef SOC_IMXRT1170_SERIES -#if defined FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn + +#if defined(FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) && (FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) hs400Capability = (uint32_t)FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(mmcsd->usdhc_host.base); #endif #if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE)) @@ -442,16 +452,16 @@ rt_int32_t _imxrt_mci_init(void) } #endif -#endif + host->max_seg_size = 65535; host->max_dma_segs = 2; -#ifdef SOC_IMXRT1170_SERIES +//#ifdef SOC_IMXRT1170_SERIES host->max_blk_size = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH; host->max_blk_count = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT; -#else - host->max_blk_size = 512; - host->max_blk_count = 4096; -#endif +//#else +// host->max_blk_size = 512; +// host->max_blk_count = 4096; +//#endif mmcsd->host = host; #ifndef CODE_STORED_ON_SDCARD diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.c b/bsp/imxrt/libraries/drivers/drv_sdram.c index d8a80af0f1..25b7169dbc 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdram.c +++ b/bsp/imxrt/libraries/drivers/drv_sdram.c @@ -13,9 +13,16 @@ #include "fsl_semc.h" #include "drv_sdram.h" -#define DRV_DEBUG -#define LOG_TAG "drv.sdram" -#include <drv_log.h> +//#define DBG_COLOR +//#define DRV_DEBUG +//#define LOG_TAG "drv.sdram" +//#include <drv_log.h> + +#define DBG_ENABLE +#define DBG_SECTION_NAME "[drv.sdram]" +#define DBG_COLOR +#define DBG_LEVEL DBG_INFO +#include <rtdbg.h> #ifdef RT_USING_MEMHEAP static struct rt_memheap system_heap; @@ -71,7 +78,7 @@ int rt_hw_sdram_init(void) } else { - LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); + LOG_I("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); #ifdef RT_USING_MEMHEAP /* * If RT_USING_MEMHEAP is enabled, SDRAM is initialized to the heap. @@ -89,7 +96,7 @@ int rt_hw_sdram_init(void) } INIT_PREV_EXPORT(rt_hw_sdram_init); -#ifdef DRV_DEBUG +#ifdef DBG_ENABLE #ifdef FINSH_USING_MSH #define SEMC_DATALEN (0x1000U) @@ -119,7 +126,7 @@ static void sdram_test(void) sdram_readBuffer[index] = sdram[index]; } - LOG_D("SEMC SDRAM 32 bit Data Write and Read Compare Start!"); + LOG_I("SEMC SDRAM 32 bit Data Write and Read Compare Start!"); /* Compare the two buffers. */ while (datalen--) { @@ -136,7 +143,7 @@ static void sdram_test(void) } else { - LOG_D("SEMC SDRAM 32 bit Data Write and Read Compare Succeed!"); + LOG_I("SEMC SDRAM 32 bit Data Write and Read Compare Succeed!"); } } MSH_CMD_EXPORT(sdram_test, sdram test) diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h index c6df838fc6..3f9a5a4b20 100644 --- a/bsp/imxrt/libraries/drivers/usb/host/usb_host.h +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h @@ -105,13 +105,8 @@ typedef struct _usb_host_process_descriptor_param uint8_t descriptorIndex; /*!< The descriptor index is used to select a specific descriptor (only for configuration and string descriptors) when several descriptors of the same type are implemented in a device */ -#ifdef SOC_IMXRT1170_SERIES uint16_t languageId; /*!< It specifies the language ID for string descriptors or is reset to zero for other descriptors */ -#else - uint8_t languageId; /*!< It specifies the language ID for string descriptors or is reset to zero for other - descriptors */ -#endif uint8_t *descriptorBuffer; /*!< Buffer pointer */ uint16_t descriptorLength; /*!< Buffer data length */ } usb_host_process_descriptor_param_t; @@ -724,7 +719,7 @@ extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb */ extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle, - uint8_t sleeptype); + uint8_t sleepType); /*! * @brief Send a bus or device resume request. diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c index 2798434f6e..4692f10ed1 100644 --- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c @@ -182,7 +182,7 @@ static const usb_host_enum_process_entry_t s_EnumEntries[] = { /******************************************************************************* * Code ******************************************************************************/ -#ifdef SOC_IMXRT1170_SERIES + static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) { /* 0 - retry current transfer, 1 - transfer success process, @@ -1508,1284 +1508,4 @@ usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle return kStatus_USB_Success; } -#else -static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) -{ - /* 0 - retry current transfer, 1 - transfer success process, - * 2 - retry whole process, 3 - fail process - */ - uint8_t nextStep = 0U; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param; - usb_status_t failReason = kStatus_USB_Success; - uint32_t dataLength; - - dataLength = transfer->transferSofar; - (void)USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */ - - if (status == kStatus_USB_Success) - { - nextStep = 1U; - } - else if (status == kStatus_USB_TransferStall) - { -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - (void)usb_echo("no response from device\r\n"); -#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ - if (deviceInstance->stallRetries > 0U) /* retry same transfer when stall */ - { - nextStep = 0U; - deviceInstance->stallRetries--; - } - else - { - failReason = kStatus_USB_TransferFailed; - nextStep = 2U; - } - } - else if (status == kStatus_USB_TransferCancel) - { - failReason = kStatus_USB_TransferCancel; - nextStep = 3U; - } - else - { - failReason = kStatus_USB_TransferFailed; - nextStep = 2U; - } - - if (nextStep == 1U) - { - deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - if (s_EnumEntries[deviceInstance->state - 1U].process == NULL) - { - deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].successState; /* next state */ - } - else - { - status = s_EnumEntries[deviceInstance->state - 1U].process( - deviceInstance, dataLength); /* process the previous state result */ - if (status == kStatus_USB_Success) /* process success */ - { - deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].successState; - } - else if (status == kStatus_USB_Retry) /* need retry */ - { - deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].retryState; - } - else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */ - { - return; /* unrecoverable fail */ - } - else /* process error, next retry */ - { - /* kStatus_USB_Error or kStatus_USB_AllocFail */ - failReason = status; - nextStep = 2U; - } - } - } - - if (nextStep == 2U) - { - if (deviceInstance->enumRetries > 0U) /* next whole retry */ - { - deviceInstance->enumRetries--; - deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - deviceInstance->configurationValue = 0U; - deviceInstance->state = (uint8_t)kStatus_DEV_GetDes8; - } - else - { -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - usb_echo("Device No Response\r\n"); -#endif - nextStep = 3U; - } - } - - /* process the state */ - if (nextStep != 3U) - { - if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("enumation setup error\r\n"); -#endif - failReason = kStatus_USB_Error; - nextStep = 3U; - } - } - - if (nextStep == 3U) - { - (void)USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)failReason); - } -} - -static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_process_descriptor_param_t getDescriptorParam; - usb_host_transfer_t *transfer; - usb_host_device_enumeration_status_t state; - - /* malloc transfer */ - state = (usb_host_device_enumeration_status_t)deviceInstance->state; - if (state != kStatus_DEV_EnumDone) - { - if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("error to get transfer\r\n"); -#endif - return kStatus_USB_Error; - } - transfer->callbackFn = USB_HostEnumerationTransferCallback; - transfer->callbackParam = deviceInstance; - - /* reset transfer fields */ - transfer->setupPacket->bmRequestType = 0x00U; - transfer->setupPacket->wIndex = 0U; - transfer->setupPacket->wLength = 0U; - transfer->setupPacket->wValue = 0U; - } - - switch (state) - { - case kStatus_DEV_GetDes8: - case kStatus_DEV_GetDes: /* get descriptor state */ - getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); - if (deviceInstance->state == (uint8_t)kStatus_DEV_GetDes8) - { - getDescriptorParam.descriptorLength = 8U; - } - getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; - getDescriptorParam.descriptorIndex = 0U; - getDescriptorParam.languageId = 0U; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - case kStatus_DEV_SetAddress: /* set address state */ - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_ADDRESS; - status = USB_HostStandardSetAddress(deviceInstance, transfer, &deviceInstance->allocatedAddress); - break; - - case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */ - getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; - getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; - getDescriptorParam.descriptorLength = 9; - getDescriptorParam.languageId = 0; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - - case kStatus_DEV_GetCfg: /* get configuration state */ - getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; - getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; - getDescriptorParam.descriptorLength = deviceInstance->configurationLen; - getDescriptorParam.languageId = 0; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - - case kStatus_DEV_SetCfg: /* set configuration state */ - transfer->setupPacket->wValue = - USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue); - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION; - status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0); - break; - - case kStatus_DEV_EnumDone: /* enumeration done state */ - /* notify device enumeration done */ - status = USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, - (uint32_t)kUSB_HostEventEnumerationDone, (uint32_t)kStatus_USB_Success); - if (status == kStatus_USB_Success) - { - deviceInstance->state = (uint8_t)kStatus_DEV_AppUsed; - } - break; - - default: - /*no action*/ - break; - } - - return status; -} - -static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance, uint32_t dataLength) -{ - usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe; - usb_status_t status = kStatus_USB_Success; - usb_descriptor_configuration_t *configureDesc; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - void *temp; - usb_host_device_enumeration_status_t state; - - state = (usb_host_device_enumeration_status_t)deviceInstance->state; - switch (state) - { - case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */ - if (dataLength != 8u) - { - return kStatus_USB_Error; - } - pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0; - /* the callbackFn is initialized in USB_HostGetControllerInterface */ - (void)hostInstance->controllerTable->controllerIoctl( - hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe); - break; - - case kStatus_DEV_SetAddress: /* process set address result */ - deviceInstance->setAddress = deviceInstance->allocatedAddress; - /* the callbackFn is initialized in USB_HostGetControllerInterface */ - (void)hostInstance->controllerTable->controllerIoctl( - hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe); - break; - - case kStatus_DEV_GetDes: /* process get full device descriptor result */ - if (dataLength != sizeof(usb_descriptor_device_t)) - { - return kStatus_USB_Error; - } - break; - - case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */ - if (dataLength != 9u) - { - return kStatus_USB_Error; - } - temp = (void *)&deviceInstance->enumBuffer[0]; - configureDesc = (usb_descriptor_configuration_t *)temp; - - deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength); - if (deviceInstance->configurationDesc != NULL) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->configurationDesc); -#else - OSA_MemoryFree(deviceInstance->configurationDesc); -#endif - deviceInstance->configurationDesc = NULL; - } - - /* fix misra 4.14 */ - if (deviceInstance->configurationLen > USB_HOST_CONFIG_MAX_CONFIGURATION_DESCRIPTOR_LENGTH) - { - return kStatus_USB_Error; - } - /* for KHCI, the start address and the length should be 4 byte align */ - if ((deviceInstance->configurationLen & 0x03U) != 0U) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - deviceInstance->configurationDesc = - (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFCu) + 4, USB_CACHE_LINESIZE); -#else - deviceInstance->configurationDesc = - (uint8_t *)OSA_MemoryAllocate((((uint32_t)deviceInstance->configurationLen) & 0xFFFCU) + 4UL); -#endif - } - else - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - deviceInstance->configurationDesc = - (uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE); -#else - deviceInstance->configurationDesc = (uint8_t *)OSA_MemoryAllocate(deviceInstance->configurationLen); -#endif - } - if (deviceInstance->configurationDesc == NULL) - { - return kStatus_USB_AllocFail; - } - break; - - case kStatus_DEV_GetCfg: /* process get configuration result */ - if (dataLength != deviceInstance->configurationLen) - { - return kStatus_USB_Error; - } - temp = (void *)deviceInstance->configurationDesc; - if (((usb_descriptor_configuration_t *)temp)->bMaxPower > USB_HOST_CONFIG_MAX_POWER) - { - return kStatus_USB_Error; - } - deviceInstance->configurationValue++; - if (USB_HostParseDeviceConfigurationDescriptor(deviceInstance) != - kStatus_USB_Success) /* parse configuration descriptor */ - { - return kStatus_USB_Error; - } - - status = USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, (uint32_t)kUSB_HostEventAttach, - (uint32_t)kStatus_USB_Success); - - if (status != kStatus_USB_Success) - { - /* next configuration */ - if (deviceInstance->configurationValue < deviceInstance->deviceDescriptor->bNumConfigurations) - { - return kStatus_USB_Retry; - } - else - { - /* notify application device is not supported */ - (void)USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, - (uint32_t)kUSB_HostEventNotSupported, (uint32_t)kStatus_USB_Success); - return kStatus_USB_NotSupported; - } - } - break; - - case kStatus_DEV_SetCfg: - /* NULL */ - break; - - default: - /*no action*/ - break; - } - - return status; -} - -static usb_status_t USB_HostNotifyDevice(usb_host_handle hostHandle, - usb_host_device_instance_t *deviceInstance, - uint32_t eventCode, - uint32_t eventParameter) -{ - usb_host_instance_t *hostInstance; - usb_status_t status1 = kStatus_USB_Error; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - usb_status_t status2 = kStatus_USB_Error; - uint8_t haveHub; - uint8_t haveNoHub; - uint8_t interfaceIndex; -#endif /* USB_HOST_CONFIG_HUB */ - - eventCode = (((uint32_t)eventParameter << 16U) | (uint32_t)eventCode); - hostInstance = (usb_host_instance_t *)hostHandle; - if (deviceInstance == NULL) - { - (void)hostInstance->deviceCallback(NULL, NULL, eventCode); - return kStatus_USB_InvalidHandle; - } - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - haveHub = 0U; - haveNoHub = 0U; - for (interfaceIndex = 0U; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc) - ->bInterfaceClass == USB_HOST_HUB_CLASS_CODE) - { - haveHub = 1U; - } - else - { - haveNoHub = 1U; - } - } - - if ((hostInstance->deviceCallback != NULL) && - ((haveNoHub == 1U) || (deviceInstance->configuration.interfaceCount == 0U))) - { - /* call host callback function, function is initialized in USB_HostInit */ - status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, eventCode); - } - if (0U != haveHub) - { - status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration, - eventCode); /* notify hub event */ - } - - if ((status1 == kStatus_USB_Success) || (status2 == kStatus_USB_Success)) /* the device is supported */ - { - return kStatus_USB_Success; - } - else if (eventCode == (uint32_t)kUSB_HostEventAttach) /* attach event */ - { - status1 = kStatus_USB_NotSupported; - } - else - { - status1 = kStatus_USB_Error; - } -#else - if (hostInstance->deviceCallback != NULL) - { - /* call host callback function, function is initialized in USB_HostInit */ - status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, eventCode); - } -#endif - return status1; -} - -static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance) -{ - uint8_t address = 0U; - uint8_t addressIndex; - uint8_t addressBitIndex; - for (addressIndex = 0U; addressIndex < 8U; ++addressIndex) /* find the idle address position byte */ - { - if (hostInstance->addressBitMap[addressIndex] != 0xFFU) - { - break; - } - } - if (addressIndex < 8U) - { - for (addressBitIndex = 0U; addressBitIndex < 8U; ++addressBitIndex) /* find the idle address position bit */ - { - if (0U == (hostInstance->addressBitMap[addressIndex] & (0x01U << addressBitIndex))) - { - hostInstance->addressBitMap[addressIndex] |= (0x01U << addressBitIndex); /* set the allocated bit */ - address = addressIndex * 8U + addressBitIndex + 1U; /* the address minimum is 1 */ - break; - } - } - } - return address; -} - -static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address) -{ - (void)USB_HostLock(); - hostInstance->addressBitMap[((uint32_t)address - 1U) >> 3U] &= - (~(0x01U << (((uint32_t)address - 1U) & 0x07U))); /* reset the allocated bit */ - (void)USB_HostUnlock(); -} - -static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *currentInstance; - usb_host_device_instance_t *prevInstance; - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* search and remove device instance */ - prevInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - if (prevInstance == deviceHandle) - { - hostInstance->deviceList = prevInstance->next; - return kStatus_USB_Success; - } - else - { - currentInstance = prevInstance->next; - } - - while (currentInstance != NULL) - { - if (currentInstance == deviceHandle) - { - prevInstance->next = currentInstance->next; - return kStatus_USB_Success; - } - prevInstance = currentInstance; - currentInstance = currentInstance->next; - } - - return kStatus_USB_Success; -} - -static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb_host_device_instance_t *deviceInstance) -{ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - uint8_t level = 0; -#endif - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - if (deviceInstance == hostInstance->suspendedDevice) - { - hostInstance->suspendedDevice = NULL; - } -#endif - /* release device's address */ - if (deviceInstance->setAddress != 0U) - { - USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress); - } - else - { - if (deviceInstance->allocatedAddress != 0U) - { - USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress); - } - } - - /* close control pipe */ - if (deviceInstance->controlPipe != NULL) - { - (void)USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); - if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("error when close pipe\r\n"); -#endif - } - deviceInstance->controlPipe = NULL; - } - - /* free configuration buffer */ - if (deviceInstance->configurationDesc != NULL) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->configurationDesc); -#else - OSA_MemoryFree(deviceInstance->configurationDesc); -#endif - } - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - level = deviceInstance->level; -#endif -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->deviceDescriptor); -#else - OSA_MemoryFree(deviceInstance->deviceDescriptor); -#endif - /* free device instance buffer */ - OSA_MemoryFree(deviceInstance); - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - /* enable controller attach if root hub */ - if (level == 1U) - { - (void)USB_HostControlBus(hostInstance, (uint8_t)kUSB_HostBusEnableAttach); - } -#else - /* enable controller attach */ - USB_HostControlBus(hostInstance, (uint8_t)kUSB_HostBusEnableAttach); -#endif -} - -static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - uint32_t endPos; - usb_descriptor_union_t *unionDes; - usb_host_interface_t *interfaceParse = NULL; - usb_host_ep_t *epParse; - uint8_t *buffer; - void *temp; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidParameter; - } - - temp = (void *)&deviceInstance->configuration; - buffer = (uint8_t *)temp; - /* clear the previous parse result, note: end_pos means buffer index here*/ - for (endPos = 0U; endPos < sizeof(usb_host_configuration_t); endPos++) - { - buffer[endPos] = 0U; - } - for (endPos = 0U; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos) - { - deviceInstance->interfaceStatus[endPos] = 0U; - } - - /* parse configuration descriptor */ - temp = (void *)deviceInstance->configurationDesc; - unionDes = (usb_descriptor_union_t *)temp; - endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen); - - if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) && - (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE)) - { - /* configuration descriptor */ - temp = (void *)unionDes; - deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)temp; - deviceInstance->configuration.configurationExtensionLength = 0; - deviceInstance->configuration.configurationExtension = NULL; - deviceInstance->configuration.interfaceCount = 0; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) - { - if (deviceInstance->configuration.configurationExtension == NULL) - { - deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00U) || - (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - deviceInstance->configuration.configurationExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - - /* interface descriptor */ - deviceInstance->configuration.interfaceCount = 0U; - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) - { - if (unionDes->interface.bAlternateSetting == 0x00U) - { - if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE) - { -#if (((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) || defined(HOST_ECHO)) - (void)usb_echo( - "Unsupported Device attached\r\n too many interfaces in one configuration, please increase " - "the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n"); -#endif - return kStatus_USB_Error; - } - interfaceParse = - &deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount]; - deviceInstance->configuration.interfaceCount++; - interfaceParse->alternateSettingNumber = 0; - interfaceParse->epCount = 0; - interfaceParse->interfaceDesc = &unionDes->interface; - interfaceParse->interfaceExtensionLength = 0; - interfaceParse->interfaceExtension = NULL; - interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber; - if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { - if (interfaceParse->interfaceExtension == NULL) - { - interfaceParse->interfaceExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00U) || - (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - - /* endpoint descriptor */ - if (interfaceParse->interfaceDesc->bNumEndpoints != 0U) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || - (interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) - { -#ifdef HOST_ECHO - usb_echo("interface descriptor error\n"); -#endif - return kStatus_USB_Error; - } - for (; interfaceParse->epCount < interfaceParse->interfaceDesc->bNumEndpoints; - (interfaceParse->epCount)++) - { - if (((uint32_t)unionDes >= endPos) || - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { -#ifdef HOST_ECHO - usb_echo("endpoint descriptor error\n"); -#endif - return kStatus_USB_Error; - } - temp = (void *)&interfaceParse->epList[interfaceParse->epCount]; - epParse = (usb_host_ep_t *)temp; - temp = (void *)unionDes; - epParse->epDesc = (usb_descriptor_endpoint_t *)temp; - epParse->epExtensionLength = 0U; - epParse->epExtension = NULL; - if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) - { - if (epParse->epExtension == NULL) - { - epParse->epExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00U) || - (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - epParse->epExtensionLength += unionDes->common.bLength; - unionDes = - (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - } - } - } - else - { - if (interfaceParse == NULL) - { - return kStatus_USB_Error; /* in normal situation this cannot reach */ - } - interfaceParse->alternateSettingNumber++; - if (interfaceParse->interfaceExtension == NULL) - { - interfaceParse->interfaceExtension = (uint8_t *)unionDes; - } - if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) - { - if ((unionDes->common.bDescriptorType == 0x00U) || - (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - } - } - else - { - return kStatus_USB_Error; - } - } - } - - for (endPos = 0U; endPos < deviceInstance->configuration.interfaceCount; ++endPos) - { - deviceInstance->interfaceStatus[endPos] = (uint8_t)kStatus_interface_Attached; - } - - return kStatus_USB_Success; -} - -usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, - uint8_t speed, - uint8_t hubNumber, - uint8_t portNumber, - uint8_t level, - usb_device_handle *deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *newInstance; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - usb_host_device_instance_t *currentInstance; -#endif - uint8_t address; - usb_host_pipe_init_t pipeInit; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - -/* check whether is the device attached? */ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - currentInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - while (currentInstance != NULL) - { - if ((currentInstance->hubNumber == hubNumber) && (currentInstance->portNumber == portNumber)) - { - *deviceHandle = NULL; -#ifdef HOST_ECHO - usb_echo("device has attached\r\n"); -#endif - return kStatus_USB_Busy; - } - else - { - currentInstance = currentInstance->next; - } - } -#else - if (hostInstance->deviceList != NULL) - { - *deviceHandle = NULL; - usb_echo("device has attached\r\n"); - return kStatus_USB_Busy; - } -#endif - - /* Allocate new device instance */ - newInstance = (usb_host_device_instance_t *)OSA_MemoryAllocate(sizeof(usb_host_device_instance_t)); - if (newInstance == NULL) - { -#ifdef HOST_ECHO - usb_echo("allocate dev instance fail\r\n"); -#endif - (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)kStatus_USB_AllocFail); - return kStatus_USB_AllocFail; - } - - /* new instance fields init */ - newInstance->hostHandle = hostHandle; - newInstance->speed = speed; - newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES; - newInstance->setAddress = 0; - newInstance->deviceAttachState = (uint8_t)kStatus_device_Attached; -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - newInstance->deviceDescriptor = - (usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE); -#else - newInstance->deviceDescriptor = (usb_descriptor_device_t *)OSA_MemoryAllocate(sizeof(usb_descriptor_device_t) + 9U); -#endif - if (newInstance->deviceDescriptor == NULL) - { -#ifdef HOST_ECHO - usb_echo("allocate newInstance->deviceDescriptor fail\r\n"); -#endif -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - OSA_MemoryFree(newInstance->deviceDescriptor); -#endif - OSA_MemoryFree(newInstance); - (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)kStatus_USB_AllocFail); - return kStatus_USB_AllocFail; - } - newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t)); -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - newInstance->hubNumber = hubNumber; - newInstance->portNumber = portNumber; - newInstance->level = level; - - if ((speed != USB_SPEED_HIGH) && (level > 1U)) - { - newInstance->hsHubNumber = (uint8_t)USB_HostHubGetHsHubNumber(hostHandle, hubNumber); - newInstance->hsHubPort = (uint8_t)USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber); - } - else - { - newInstance->hsHubNumber = hubNumber; - newInstance->hsHubPort = portNumber; - } -#endif /* USB_HOST_CONFIG_HUB */ - - (void)USB_HostLock(); - /* allocate address && insert to the dev list */ - address = USB_HostAllocateDeviceAddress(hostInstance); - if (address == 0U) - { -#ifdef HOST_ECHO - usb_echo("allocate address fail\r\n"); -#endif - (void)USB_HostUnlock(); -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - OSA_MemoryFree(newInstance->deviceDescriptor); -#endif - OSA_MemoryFree(newInstance); - (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)kStatus_USB_Error); - return kStatus_USB_Error; - } - newInstance->allocatedAddress = address; - - newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList; - hostInstance->deviceList = newInstance; - newInstance->state = (uint8_t)kStatus_DEV_Initial; - (void)USB_HostUnlock(); - - /* open control pipe */ - pipeInit.devInstance = newInstance; - pipeInit.pipeType = USB_ENDPOINT_CONTROL; - pipeInit.direction = 0; - pipeInit.endpointAddress = 0; - pipeInit.interval = 0; - pipeInit.maxPacketSize = 8; - pipeInit.numberPerUframe = 0; - pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK; - if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success) - { - /* don't need release resource, resource is released when detach */ - *deviceHandle = newInstance; -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - OSA_MemoryFree(newInstance->deviceDescriptor); -#endif - OSA_MemoryFree(newInstance); - (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)kStatus_USB_Error); - return kStatus_USB_Error; - } - - /* start enumeration */ - newInstance->state = (uint8_t)kStatus_DEV_GetDes8; - /* process enumeration state machine */ - if (USB_HostProcessState(newInstance) != kStatus_USB_Success) - { - (void)USB_HostNotifyDevice(hostInstance, newInstance, (uint32_t)kUSB_HostEventEnumerationFail, - (uint32_t)kStatus_USB_Error); - } - - *deviceHandle = newInstance; - return kStatus_USB_Success; -} - -usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber) -{ - usb_host_device_instance_t *deviceInstance; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - (void)USB_HostLock(); -/* search for device instance handle */ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - while (deviceInstance != NULL) - { - if ((deviceInstance->hubNumber == hubNumber) && (deviceInstance->portNumber == portNumber)) - { - break; - } - deviceInstance = deviceInstance->next; - } -#else - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; -#endif - (void)USB_HostUnlock(); - if (deviceInstance != NULL) - { - return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */ - } - return kStatus_USB_Success; -} - -usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - deviceInstance->deviceAttachState = (uint8_t)kStatus_device_Detached; /* mark the device is detached from host */ - - if (deviceInstance->state >= (uint8_t)kStatus_DEV_Initial) /* device instance is valid */ - { - /* detach internally */ - if (deviceInstance->state < (uint8_t)kStatus_DEV_AppUsed) /* enumeration is not done */ - { - if (deviceInstance->controlPipe != NULL) - { - (void)USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); - } - - /* remove device instance from host */ - (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - USB_HostReleaseDeviceResource(hostInstance, deviceInstance); - } - else /* enumeration has be done and notified application */ - { - /* notify application device detach */ - (void)USB_HostNotifyDevice(hostInstance, deviceInstance, (uint32_t)kUSB_HostEventDetach, - (uint32_t)kStatus_USB_Success); - } - } - - return kStatus_USB_Success; -} -uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle) -{ - return (NULL != deviceHandle) ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0U; -} - -usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *searchDev; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidParameter; - } - /* search for the device */ - searchDev = (usb_host_device_instance_t *)((usb_host_instance_t *)hostHandle)->deviceList; - while ((searchDev != NULL) && ((usb_device_handle)searchDev != deviceHandle)) - { - searchDev = searchDev->next; - } - - if (NULL != searchDev) - { - return kStatus_USB_Success; - } - return kStatus_USB_Error; -} - -static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - /* the callbackFn is initialized in USB_HostGetControllerInterface */ - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, - &controlType); - - return status; -} - -usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = NULL; - uint8_t interfaceIndex; - uint8_t index = 0; - - if ((deviceHandle == NULL) || (interfaceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - (void)USB_HostLock(); - /* check host_instance valid? */ - for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) - { - if ((g_UsbHostInstance[index].occupied == 1U) && - ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) - { - break; - } - } - if (index >= USB_HOST_CONFIG_MAX_HOST) - { - (void)USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* check deviceHandle valid? */ - if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) - { - (void)USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* search interface and set the interface as opened */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) - { - deviceInstance->interfaceStatus[interfaceIndex] = (uint8_t)kStatus_interface_Opened; - break; - } - } - (void)USB_HostUnlock(); - - return kStatus_USB_Success; -} - -usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = NULL; - uint8_t interfaceIndex; - uint8_t removeLabel = 1; - uint8_t index = 0; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - (void)USB_HostLock(); - /* check host_instance valid? */ - for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) - { - if ((g_UsbHostInstance[index].occupied == 1U) && - ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) - { - break; - } - } - if (index >= USB_HOST_CONFIG_MAX_HOST) - { - (void)USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* check deviceHandle valid? */ - if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) - { - (void)USB_HostUnlock(); - return kStatus_USB_Error; - } - - if (interfaceHandle != NULL) - { - /* search interface and set the interface as detached */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) - { - deviceInstance->interfaceStatus[interfaceIndex] = (uint8_t)kStatus_interface_Detached; - break; - } - } - } - - if (deviceInstance->deviceAttachState == (uint8_t)kStatus_device_Detached) /* device is removed from host */ - { - removeLabel = 1; - /* check all the interfaces of the device are not opened */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (deviceInstance->interfaceStatus[interfaceIndex] == (uint8_t)kStatus_interface_Opened) - { - removeLabel = 0U; - break; - } - } - if (removeLabel == 1U) - { - /* remove device instance from host */ - (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - } - (void)USB_HostUnlock(); - - if (removeLabel == 1U) - { - USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle, - deviceInstance); /* release device resource */ - } - } - else - { - (void)USB_HostUnlock(); - } - - return kStatus_USB_Success; -} - -usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - uint8_t interfaceIndex = 0; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - uint8_t level = 0; - uint8_t devHubNo; - uint8_t devPortNo; -#endif - - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - if (deviceInstance->hostHandle != hostHandle) - { - return kStatus_USB_InvalidParameter; - } - - if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */ - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - devHubNo = deviceInstance->hubNumber; - devPortNo = deviceInstance->portNumber; - level = deviceInstance->level; -#endif - - deviceInstance->deviceAttachState = (uint8_t)kStatus_device_Detached; - if (deviceInstance->state >= (uint8_t)kStatus_DEV_Initial) /* device is valid */ - { - if (deviceInstance->state < - (uint8_t)kStatus_DEV_AppUsed) /* enumeration is not done or application don't use */ - { - /* detach internally */ - (void)USB_HostDetachDeviceInternal(hostHandle, deviceHandle); - } - else /* application use the device */ - { - for (interfaceIndex = 0U; interfaceIndex < deviceInstance->configuration.interfaceCount; - ++interfaceIndex) - { - if (deviceInstance->interfaceStatus[interfaceIndex] == (uint8_t)kStatus_interface_Opened) - { -#ifdef HOST_ECHO - usb_echo("error: there is class instance that is not deinited\r\n"); -#endif - break; - } - } - /* remove device instance from host */ - (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */ - } - } - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - if (level == 1U) - { - (void)USB_HostControlBus(hostHandle, (uint8_t)kUSB_HostBusReset); /* reset controller port */ - (void)USB_HostControlBus(hostHandle, (uint8_t)kUSB_HostBusRestart); /* restart controller port */ - } - else - { - (void)USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */ - } -#else - USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ - USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ -#endif /* USB_HOST_CONFIG_HUB */ - } - - return kStatus_USB_Success; -} -#endif diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c index 0024ed3585..6696f54cf6 100644 --- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c @@ -16,7 +16,9 @@ #endif #include "fsl_device_registers.h" #include "usb_host_ehci.h" +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT)) #include <usb/phy/usb_phy.h> +#endif #if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) #include "usb_host.h" #endif @@ -161,14 +163,12 @@ static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length); */ static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms); -#ifdef SOC_IMXRT1170_SERIES /*! * @brief host ehci start async schedule. * * @param ehciInstance ehci instance pointer. */ static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); -#endif /*! * @brief host ehci stop async schedule. @@ -177,14 +177,12 @@ static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); */ static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance); -#ifdef SOC_IMXRT1170_SERIES /*! * @brief host ehci start periodic schedule. * * @param ehciInstance ehci instance pointer. */ static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); -#endif /*! * @brief host ehci stop periodic schedule. @@ -505,8 +503,6 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc usb_host_ehci_pipe_t *ehciPipePointer, usb_host_transfer_t *transfer); - -#ifdef SOC_IMXRT1170_SERIES /*! * @brief control ehci bus. * @@ -516,7 +512,6 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc * @return kStatus_USB_Success or error codes. */ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); -#endif /*! * @brief ehci transaction done process function. @@ -525,7 +520,6 @@ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstanc */ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance); -#ifdef SOC_IMXRT1170_SERIES /*! * @brief ehci port change interrupt process function. * @@ -540,7 +534,6 @@ static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); * @param ehciInstance ehci instance pointer. */ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); -#endif #if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) /*! @@ -1096,11 +1089,7 @@ static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t * { usb_host_ehci_pipe_t *ehciPipePointer; uint8_t index; -#ifdef SOC_IMXRT1170_SERIES - uint32_t deviceInfo = 0; -#else - uint32_t deviceInfo; -#endif + uint32_t deviceInfo = 0U; void *temp; for (index = 0; index < 8U; ++index) @@ -1172,11 +1161,7 @@ static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t { usb_host_ehci_pipe_t *ehciPipePointer; uint16_t index; -#ifdef SOC_IMXRT1170_SERIES uint32_t deviceInfo = 0U; -#else - uint32_t deviceInfo; -#endif uint16_t frameInterval; void *temp; for (index = 0; index < 8U; ++index) @@ -1849,11 +1834,7 @@ static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms) } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8U)); /* compute the distance between sofStart and SofEnd */ } -#ifdef SOC_IMXRT1170_SERIES static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) -#else -void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) -#endif { uint32_t stateSync; @@ -1891,11 +1872,7 @@ static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance) } } -#ifdef SOC_IMXRT1170_SERIES static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) -#else -void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) -#endif { uint32_t stateSync; @@ -3127,11 +3104,9 @@ static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstan /* USB_HostEhciLock(); */ /*set next link pointer to invalid in case hardware access invalid itd structure in special case*/ itdPointer->nextLinkPointer = EHCI_HOST_T_INVALID_VALUE; -#ifdef SOC_IMXRT1170_SERIES USB_HostEhciZeroMem((uint32_t *)(void *)itdPointer + 1, ((sizeof(usb_host_ehci_itd_t) >> 2) - 4U)); -#endif - itdPointer->nextItdPointer = (usb_host_ehci_itd_t *)ehciInstance->ehciItdList; - ehciInstance->ehciItdList = itdPointer; + itdPointer->nextItdPointer = (usb_host_ehci_itd_t *)ehciInstance->ehciItdList; + ehciInstance->ehciItdList = itdPointer; ehciInstance->ehciItdNumber++; /* USB_HostEhciUnlock(); */ @@ -3449,13 +3424,10 @@ static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance) #endif #endif } -#ifdef SOC_IMXRT1170_SERIES /* no interrupt threshold */ ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; -#endif /* start the controller */ ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_RS_MASK; - /* set timer0 */ ehciInstance->ehciIpBase->GPTIMER0LD = (100U * 1000U - 1U); /* 100ms */ @@ -3547,11 +3519,8 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc return kStatus_USB_Success; } -#ifdef SOC_IMXRT1170_SERIES + static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) -#else -usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) -#endif { usb_status_t status = kStatus_USB_Success; uint32_t portScRegister; @@ -3664,11 +3633,7 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) usb_host_ehci_iso_t *isoPointer; uint32_t dataLength; -#ifdef SOC_IMXRT1170_SERIES uint32_t speed = 0U; -#else - uint32_t speed; -#endif #endif void *temp; uint32_t transferResults; @@ -3778,7 +3743,6 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) else { /* remove qtd from qh */ -#ifdef SOC_IMXRT1170_SERIES do { if (vltQtdPointer == NULL) @@ -3795,13 +3759,7 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) } vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; } while (true); -#else - while ((vltQtdPointer != NULL) && - (0U == (transferResults & EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */ - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; - } -#endif + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; vltQhPointer->transferOverlayResults[0] &= @@ -3926,11 +3884,7 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) } } -#ifdef SOC_IMXRT1170_SERIES static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) -#else -void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) -#endif { /* note: only has one port */ uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1; @@ -3998,10 +3952,12 @@ void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) ehciInstance->firstDeviceSpeed = (uint8_t)((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT); /* enable ehci phy disconnection */ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) { USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 1); } +#endif /* wait for reset */ USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY); @@ -4022,13 +3978,9 @@ void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); #endif /* disable ehci phy disconnection */ -#ifdef SOC_IMXRT1170_SERIES #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); #endif -#else - USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); -#endif /* disable async and periodic */ USB_HostEhciStopAsync(ehciInstance); USB_HostEhciStopPeriodic(ehciInstance); @@ -4037,11 +3989,7 @@ void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) } } -#ifdef SOC_IMXRT1170_SERIES static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) -#else -void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) -#endif { volatile usb_host_ehci_qh_t *vltQhPointer; usb_host_ehci_qtd_t *vltQtdPointer; @@ -4188,15 +4136,11 @@ static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) ; #endif #endif -#ifdef SOC_IMXRT1170_SERIES #if (defined(FSL_FEATURE_USBPHY_28FDSOI) && (FSL_FEATURE_USBPHY_28FDSOI > 0U)) ehciInstance->registerPhyBase->USB1_VBUS_DETECT_SET |= USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK; #endif -#endif ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; - -#ifdef SOC_IMXRT1170_SERIES #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; @@ -4205,37 +4149,20 @@ static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) __NOP(); } #endif -#else - ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; - - while (0U != (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK))) - { - __NOP(); - } -#endif - #if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; #else -#ifdef SOC_IMXRT1170_SERIES #if (defined(FSL_FEATURE_USB_ATLANTIC_EHCI_SUPPORT) && (FSL_FEATURE_USB_ATLANTIC_EHCI_SUPPORT > 0U)) #else ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; #endif -#else - ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; -#endif #endif -#ifdef #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; #endif -#else - ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; -#endif (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, kUSB_HostEventSuspended); /* call host callback function */ ehciInstance->busSuspendStatus = kBus_EhciSuspended; @@ -4306,14 +4233,9 @@ usb_status_t USB_HostEhciCreate(uint8_t controllerId, ehciInstance->busSuspendStatus = kBus_EhciIdle; #if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -#ifdef SOC_IMXRT1170_SERIES #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); #endif -#else - ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); -#endif - #if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) ehciInstance->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); #endif @@ -4539,9 +4461,6 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, usb_status_t status; uint32_t speed = 0; usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; -#if !defined(SOC_IMXRT1170_SERIES) - uint32_t val32; -#endif void *temp; /* get one pipe */ USB_HostEhciLock(); @@ -4599,16 +4518,6 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, (uint8_t)ehciPipePointer->pipeCommon.interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */ } -#if !defined(SOC_IMXRT1170_SERIES) - } - - if ((speed == USB_SPEED_HIGH) && (ehciPipePointer->pipeCommon.interval < 8U)) - { - val32 = ehciInstance->ehciIpBase->USBCMD; - val32 &= (~USBHS_USBCMD_ITC_MASK); - val32 |= USBHS_USBCMD_ITC((ehciPipePointer->pipeCommon.interval)); - ehciInstance->ehciIpBase->USBCMD = val32; -#endif } } diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h index d1831a4d00..f45ca9eb71 100644 --- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h @@ -309,13 +309,9 @@ typedef struct _usb_host_ehci_instance uint32_t taskEventHandleBuffer[(OSA_EVENT_HANDLE_SIZE + 3) / 4]; /*!< EHCI task event handle buffer*/ #if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) uint64_t matchTick; -#ifdef SOC_IMXRT1170_SERIES #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ #endif -#else - USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ -#endif #if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ #endif @@ -455,6 +451,7 @@ extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerH * @param[in] controllerHandle The controller handle. * @param[in] pipeHandle The receiving pipe handle. * @param[in] transfer The transfer information. + * @retval kStatus_USB_Success Send successfully. * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. @@ -479,46 +476,6 @@ extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandl uint32_t ioctlEvent, void *ioctlParam); -#if !defined(SOC_IMXRT1170_SERIES) -/*! - * @brief control ehci bus. - * - * @param ehciInstance ehci instance pointer. - * @param bus_control control code. - * - * @return kStatus_USB_Success or error codes. - */ -extern usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); - -/*! - * @brief ehci port change interrupt process function. - * - * @param ehciInstance ehci instance pointer. - */ -extern void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief ehci timer0 interrupt process function. - * cancel control/bulk transfer that time out. - * - * @param ehciInstance ehci instance pointer. - */ -extern void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief host ehci start async schedule. - * - * @param ehciInstance ehci instance pointer. - */ -extern void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief host ehci start periodic schedule. - * - * @param ehciInstance ehci instance pointer. - */ -extern void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); -#endif /*! @}*/ #ifdef __cplusplus diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c index a2ede69979..e7dd0e2bae 100644 --- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c @@ -267,7 +267,6 @@ usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, hos return kStatus_USB_Error; } - /* HOST instance init*/ hostInstance->controllerId = controllerId; hostInstance->deviceCallback = callbackFn; @@ -699,18 +698,10 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter } /* parse configuration descriptor */ -#ifdef SOC_IMXRT1170_SERIES temp = (void *)((usb_host_interface_t *)interfaceHandle)->interfaceExtension; -#else - temp = (void *)((usb_host_interface_t *)interfaceHandle)->interfaceDesc; -#endif unionDes = (usb_descriptor_union_t *)temp; /* interface extend descriptor start */ - endPosition = - (uint32_t)unionDes + + endPosition = (uint32_t)unionDes + ((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */ -#if !defined(SOC_IMXRT1170_SERIES) - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); -#endif /* search for the alternate setting interface descriptor */ while ((uint32_t)unionDes < endPosition) diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb.h b/bsp/imxrt/libraries/drivers/usb/include/usb.h index 0a10e0a460..be3c91f0b5 100644 --- a/bsp/imxrt/libraries/drivers/usb/include/usb.h +++ b/bsp/imxrt/libraries/drivers/usb/include/usb.h @@ -56,11 +56,15 @@ /*! @brief USB stack version definition */ #define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#ifdef SOC_IMXRT1170_SERIES /*! @brief USB stack component version definition, changed with component in yaml together */ #define USB_STACK_COMPONENT_VERSION \ MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX) -#endif + +/* + * Component ID used by tools + * + * FSL_COMPONENT_ID "middleware.usb.stack_common" + */ /*! @brief USB error code */ typedef enum _usb_status @@ -86,11 +90,9 @@ typedef enum _usb_status kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ kStatus_USB_EHCIAttached, kStatus_USB_EHCIDetached, -#ifdef SOC_IMXRT1170_SERIES kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint or the remaining buffer size. */ -#endif } usb_status_t; /*! @brief USB host handle type define */ @@ -114,33 +116,28 @@ typedef enum _usb_controller_index to be used in the future. */ kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ - kUSB_ControllerLpcIp3511Fs1 = - 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved - to be used in the future. */ + kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ - kUSB_ControllerLpcIp3511Hs1 = - 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved - to be used in the future. */ + kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved to be used in the future. */ kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ - kUSB_ControllerIp3516Hs1 = - 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved - to be used in the future. */ -#ifdef SOC_IMXRT1170_SERIES + kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, + this is reserved to be used in the future. */ kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */ kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved to be used in the future.*/ -#endif } usb_controller_index_t; /** -* @brief USB stack version fields -*/ + * @brief USB stack version fields + */ typedef struct _usb_version { uint8_t major; /*!< Major */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h b/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h index 8727a4e05c..60c8a6cce5 100644 --- a/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h @@ -22,11 +22,8 @@ * - if 0, host ehci driver is disable. * - if greater than 0, host ehci driver is enable. */ -#ifdef SOC_IMXRT1170_SERIES #define USB_HOST_CONFIG_EHCI (1U) -#else -#define USB_HOST_CONFIG_EHCI (2U) -#endif + /*! * @brief host ohci instance count, meantime it indicates ohci enable or disable. * - if 0, host ohci driver is disable. @@ -103,13 +100,10 @@ #define USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U) #endif /*! @brief if 1, enable usb compliance test codes; if 0, disable usb compliance test codes. */ -#ifdef SOC_IMXRT1170_SERIES #ifndef USB_HOST_CONFIG_COMPLIANCE_TEST #define USB_HOST_CONFIG_COMPLIANCE_TEST (0U) #endif -#else -#define USB_HOST_CONFIG_COMPLIANCE_TEST (0U) -#endif + /*! @brief if 1, class driver clear stall automatically; if 0, class driver don't clear stall. */ #define USB_HOST_CONFIG_CLASS_AUTO_CLEAR_STALL (0U) @@ -156,7 +150,7 @@ /* OHCI configuration */ #if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI)) -#ifdef SOC_IMXRT1170_SERIES + /*! * @brief ohci ED max count. */ @@ -166,17 +160,6 @@ * @brief ohci GTD max count. */ #define USB_HOST_CONFIG_OHCI_MAX_GTD (16U) -#else -/*! - * @brief ohci ED max count. - */ -#define USB_HOST_CONFIG_OHCI_MAX_ED (8U) - -/*! - * @brief ohci GTD max count. - */ -#define USB_HOST_CONFIG_OHCI_MAX_GTD (8U) -#endif /*! * @brief ohci ITD max count. diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h b/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h index d77b7d3598..7b93e1c6d7 100644 --- a/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h @@ -39,6 +39,7 @@ #define USB_SPEED_FULL (0x00U) #define USB_SPEED_LOW (0x01U) #define USB_SPEED_HIGH (0x02U) +#define USB_SPEED_SUPER (0x04U) /* Set up packet structure */ typedef struct _usb_setup_struct @@ -65,9 +66,12 @@ typedef struct _usb_setup_struct #define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) #define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) #define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT_COMPANION (0x06U) #define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) #define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) #define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_USB20_EXTENSION (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_SUPERSPEED (0x0AU) /* USB Device Capability Type Codes */ #define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) @@ -92,6 +96,8 @@ typedef struct _usb_setup_struct #define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) #define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT_COMPANION (0x30U) + /* USB standard request type */ #define USB_REQUEST_TYPE_DIR_MASK (0x80U) #define USB_REQUEST_TYPE_DIR_SHIFT (7U) @@ -191,7 +197,6 @@ typedef struct _usb_setup_struct #define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) #define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) - /* Language structure */ typedef struct _usb_language { @@ -268,29 +273,49 @@ typedef struct _usb_descriptor_endpoint uint8_t bInterval; } usb_descriptor_endpoint_t; +typedef struct _usb_descriptor_endpoint_companion +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + uint8_t wBytesPerInterval[2]; +} usb_descriptor_endpoint_companion_t; + typedef struct _usb_descriptor_binary_device_object_store { - uint8_t bLength; /* Descriptor size in bytes = 5U */ - uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ - uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ - uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ } usb_descriptor_bos_t; typedef struct _usb_descriptor_usb20_extension { uint8_t bLength; /* Descriptor size in bytes = 7U */ uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ - uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ - uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ } usb_descriptor_usb20_extension_t; - +typedef struct _usb_descriptor_super_speed_device_capability +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + uint8_t wSpeedsSupported[2]; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t wU2DevExitLat[2]; +} usb_bos_device_capability_susperspeed_desc_t; typedef union _usb_descriptor_union { - usb_descriptor_common_t common; /* Common descriptor */ - usb_descriptor_device_t device; /* Device descriptor */ - usb_descriptor_configuration_t configuration; /* Configuration descriptor */ - usb_descriptor_interface_t interface; /* Interface descriptor */ - usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ + usb_descriptor_endpoint_companion_t endpointCompanion; /* Endpoint companion descriptor */ } usb_descriptor_union_t; #endif /* __USB_SPEC_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c index c420482ad2..aa3fb98c11 100644 --- a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c +++ b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c @@ -33,7 +33,6 @@ #include <usb/phy/usb_phy.h> -#ifdef SOC_IMXRT1170_SERIES void *USB_EhciPhyGetBase(uint8_t controllerId) { void *usbPhyBase = NULL; @@ -299,210 +298,4 @@ void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable) } #endif #endif -#else -void *USB_EhciPhyGetBase(uint8_t controllerId) -{ - void *usbPhyBase = NULL; -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - uint32_t instance; - uint32_t newinstance = 0; - uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; - uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; - - if (controllerId < kUSB_ControllerEhci0) - { - return NULL; - } - - controllerId = controllerId - kUSB_ControllerEhci0; - - for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) - { - if (usbphy_base_temp[instance]) - { - usbphy_base[newinstance++] = usbphy_base_temp[instance]; - } - } - if (controllerId > newinstance) - { - return NULL; - } - - usbPhyBase = (void *)usbphy_base[controllerId]; -#endif - return usbPhyBase; -} - -/*! - * @brief ehci phy initialization. - * - * This function initialize ehci phy IP. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] freq the external input clock. - * for example: if the external input clock is 16M, the parameter freq should be 16000000. - * - * @retval kStatus_USB_Success cancel successfully. - * @retval kStatus_USB_Error the freq value is incorrect. - */ -uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return kStatus_USB_Error; - } - -#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) - ANATOP->HW_ANADIG_REG_3P0.RW = - (ANATOP->HW_ANADIG_REG_3P0.RW & - (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | - ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; - ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = - ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; -#endif - -#if (defined USB_ANALOG) - USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); -#endif - -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - - usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ - /* PWD register provides overall control of the PHY power state */ - usbPhyBase->PWD = 0U; - - /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ - usbPhyBase->TX = - ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | - (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | - USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); -#endif - - return kStatus_USB_Success; -} - -/*! - * @brief ehci phy initialization for suspend and resume. - * - * This function initialize ehci phy IP for suspend and resume. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] freq the external input clock. - * for example: if the external input clock is 16M, the parameter freq should be 16000000. - * - * @retval kStatus_USB_Success cancel successfully. - * @retval kStatus_USB_Error the freq value is incorrect. - */ -uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return kStatus_USB_Error; - } - -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ -#endif - -#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) - usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; -#else - usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ - /* PWD register provides overall control of the PHY power state */ - usbPhyBase->PWD = 0U; -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD - * pfd clock = 480MHz*18/N, where N=18~35 - * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode - */ - usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ - usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ - - usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; - usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; - while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) - { - } -#endif - /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ - usbPhyBase->TX = - ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | - (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | - USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); -#endif - - return kStatus_USB_Success; -} - -/*! - * @brief ehci phy de-initialization. - * - * This function de-initialize ehci phy IP. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - */ -void USB_EhciPhyDeinit(uint8_t controllerId) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return; - } -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ - usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ -#endif -} - -/*! - * @brief ehci phy disconnect detection enable or disable. - * - * This function enable/disable host ehci disconnect detection. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] enable - * 1U - enable; - * 0U - disable; - */ -void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return; - } - - if (enable) - { - usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; - } - else - { - usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); - } -#endif -} -#endif diff --git a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h index 278dc8fe20..8487e9f4ee 100644 --- a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h +++ b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h @@ -105,7 +105,6 @@ extern void USB_EhciPhyDeinit(uint8_t controllerId); * 0U - disable; */ extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); -#ifdef SOC_IMXRT1170_SERIES #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) #if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) /*! @@ -121,7 +120,6 @@ extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t ena extern void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable); #endif #endif -#endif #if defined(__cplusplus) } #endif |