diff options
| author | bernard.xiong <[email protected]> | 2010-03-08 23:12:08 +0000 |
|---|---|---|
| committer | bernard.xiong <[email protected]> | 2010-03-08 23:12:08 +0000 |
| commit | eb685b372dca15502d439d94997139f87bbdc023 (patch) | |
| tree | 476f19706a8f906e142bc89c64506797d814065c | |
| parent | 86f386885253fbe04a4c079a5e481b2539626f04 (diff) | |
add lpc17xx porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@466 bbd45198-f89e-11dd-88c7-29a3b14d5316
| -rw-r--r-- | libcpu/arm/lpc17xx/context_rvds.S | 173 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/cpu.c | 43 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/fault.c | 47 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/fault_rvds.S | 35 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/interrupt.c | 21 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/stack.c | 60 | ||||
| -rw-r--r-- | libcpu/arm/lpc17xx/start_rvds.S | 266 |
7 files changed, 645 insertions, 0 deletions
diff --git a/libcpu/arm/lpc17xx/context_rvds.S b/libcpu/arm/lpc17xx/context_rvds.S new file mode 100644 index 0000000000..0ffeb59c7e --- /dev/null +++ b/libcpu/arm/lpc17xx/context_rvds.S @@ -0,0 +1,173 @@ +;/*
+; * File : context_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-01-17 Bernard first version
+; * 2010-02-04 Magicoe Edit for LPC17xx Series
+; */
+
+;/**
+; * @addtogroup LPC17
+; */
+;/*@{*/
+
+NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
+NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
+NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
+NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
+
+ AREA |.text|, CODE, READONLY, ALIGN=2
+ THUMB
+ REQUIRE8
+ PRESERVE8
+
+ IMPORT rt_thread_switch_interrput_flag
+ IMPORT rt_interrupt_from_thread
+ IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable PROC
+ EXPORT rt_hw_interrupt_disable
+ MRS r0, PRIMASK
+ CPSID I
+ BX LR
+ ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable PROC
+ EXPORT rt_hw_interrupt_enable
+ MSR PRIMASK, r0
+ BX LR
+ ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+ EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch PROC
+ EXPORT rt_hw_context_switch
+
+ ; set rt_thread_switch_interrput_flag to 1
+ LDR r2, =rt_thread_switch_interrput_flag
+ LDR r3, [r2]
+ CMP r3, #1
+ BEQ _reswitch
+ MOV r3, #1
+ STR r3, [r2]
+
+ LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
+ STR r0, [r2]
+
+_reswitch
+ LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
+ STR r1, [r2]
+
+ LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
+ LDR r1, =NVIC_PENDSVSET
+ STR r1, [r0]
+ BX LR
+ ENDP
+
+; r0 --> swith from thread stack
+; r1 --> swith to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+rt_hw_pend_sv PROC
+ EXPORT rt_hw_pend_sv
+
+ ; disable interrupt to protect context switch
+ MRS r2, PRIMASK
+ CPSID I
+
+ ; get rt_thread_switch_interrupt_flag
+ LDR r0, =rt_thread_switch_interrput_flag
+ LDR r1, [r0]
+ CBZ r1, pendsv_exit ; pendsv already handled
+
+ ; clear rt_thread_switch_interrput_flag to 0
+ MOV r1, #0x00
+ STR r1, [r0]
+
+ LDR r0, =rt_interrupt_from_thread
+ LDR r1, [r0]
+ CBZ r1, swtich_to_thread ; skip register save at the first time
+
+ MRS r1, psp ; get from thread stack pointer
+ STMFD r1!, {r4 - r11} ; push r4 - r11 register
+ LDR r0, [r0]
+ STR r1, [r0] ; update from thread stack pointer
+
+swtich_to_thread
+ LDR r1, =rt_interrupt_to_thread
+ LDR r1, [r1]
+ LDR r1, [r1] ; load thread stack pointer
+
+ LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
+ MSR psp, r1 ; update stack pointer
+
+pendsv_exit
+ ; restore interrupt
+ MSR PRIMASK, r2
+
+ ORR lr, lr, #0x04
+ BX lr
+ ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to PROC
+ EXPORT rt_hw_context_switch_to
+ ; set to thread
+ LDR r1, =rt_interrupt_to_thread
+ STR r0, [r1]
+
+ ; set from thread to 0
+ LDR r1, =rt_interrupt_from_thread
+ MOV r0, #0x0
+ STR r0, [r1]
+
+ ; set interrupt flag to 1
+ LDR r1, =rt_thread_switch_interrput_flag
+ MOV r0, #1
+ STR r0, [r1]
+
+ ; set the PendSV exception priority
+ LDR r0, =NVIC_SYSPRI2
+ LDR r1, =NVIC_PENDSV_PRI
+ STR r1, [r0]
+
+ ; trigger the PendSV exception (causes context switch)
+ LDR r0, =NVIC_INT_CTRL
+ LDR r1, =NVIC_PENDSVSET
+ STR r1, [r0]
+
+ ; enable interrupts at processor level
+ CPSIE I
+
+ ; never reach here!
+ ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+ EXPORT rt_hw_interrupt_thread_switch
+ BX lr
+ NOP
+ ENDP
+
+ END
diff --git a/libcpu/arm/lpc17xx/cpu.c b/libcpu/arm/lpc17xx/cpu.c new file mode 100644 index 0000000000..5abd146e54 --- /dev/null +++ b/libcpu/arm/lpc17xx/cpu.c @@ -0,0 +1,43 @@ +/*
+ * File : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-01-05 Bernard first version
+ * 2010-02-04 Magicoe Edit for LPC17xx Series
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup LPC17xx
+ */
+/*@{*/
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+ /*NOTREACHED*/
+}
+
+/**
+ * shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+ rt_kprintf("shutdown...\n");
+
+ RT_ASSERT(0);
+}
+
+/*@}*/
diff --git a/libcpu/arm/lpc17xx/fault.c b/libcpu/arm/lpc17xx/fault.c new file mode 100644 index 0000000000..17c4a08b1f --- /dev/null +++ b/libcpu/arm/lpc17xx/fault.c @@ -0,0 +1,47 @@ +/*
+ * File : fault.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-01-05 Bernard first version
+ */
+#include <rtthread.h>
+
+struct stack_contex
+{
+ rt_uint32_t r0;
+ rt_uint32_t r1;
+ rt_uint32_t r2;
+ rt_uint32_t r3;
+ rt_uint32_t r12;
+ rt_uint32_t lr;
+ rt_uint32_t pc;
+ rt_uint32_t psr;
+};
+
+extern void rt_hw_interrupt_thread_switch(void);
+extern void list_thread(void);
+extern rt_thread_t rt_current_thread;
+void rt_hw_hard_fault_exception(struct stack_contex* contex)
+{
+ rt_kprintf("psr: 0x%08x\n", contex->psr);
+ rt_kprintf(" pc: 0x%08x\n", contex->pc);
+ rt_kprintf(" lr: 0x%08x\n", contex->lr);
+ rt_kprintf("r12: 0x%08x\n", contex->r12);
+ rt_kprintf("r03: 0x%08x\n", contex->r3);
+ rt_kprintf("r02: 0x%08x\n", contex->r2);
+ rt_kprintf("r01: 0x%08x\n", contex->r1);
+ rt_kprintf("r00: 0x%08x\n", contex->r0);
+
+ rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
+#ifdef RT_USING_FINSH
+ list_thread();
+#endif
+ while (1);
+}
diff --git a/libcpu/arm/lpc17xx/fault_rvds.S b/libcpu/arm/lpc17xx/fault_rvds.S new file mode 100644 index 0000000000..9a422e16b9 --- /dev/null +++ b/libcpu/arm/lpc17xx/fault_rvds.S @@ -0,0 +1,35 @@ +;/*
+; * File : fault_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-01-17 Bernard first version
+; */
+
+ AREA |.text|, CODE, READONLY, ALIGN=2
+ THUMB
+ REQUIRE8
+ PRESERVE8
+
+ IMPORT rt_hw_hard_fault_exception
+
+rt_hw_hard_fault PROC
+ EXPORT rt_hw_hard_fault
+
+ ; get current context
+ MRS r0, psp ; get fault thread stack pointer
+ PUSH {lr}
+ BL rt_hw_hard_fault_exception
+ POP {lr}
+
+ ORR lr, lr, #0x04
+ BX lr
+ ENDP
+
+ END
diff --git a/libcpu/arm/lpc17xx/interrupt.c b/libcpu/arm/lpc17xx/interrupt.c new file mode 100644 index 0000000000..8cf81a620f --- /dev/null +++ b/libcpu/arm/lpc17xx/interrupt.c @@ -0,0 +1,21 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include <rtthread.h> + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; + +/*@}*/ diff --git a/libcpu/arm/lpc17xx/stack.c b/libcpu/arm/lpc17xx/stack.c new file mode 100644 index 0000000000..68f6850e54 --- /dev/null +++ b/libcpu/arm/lpc17xx/stack.c @@ -0,0 +1,60 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard the first version + * 2010-02-04 Magicoe Edit for LPC17xx Series + */ +#include <rtthread.h> + +/** + * @addtogroup LPC17xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = 0x01000000L; /* PSR */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ + + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/arm/lpc17xx/start_rvds.S b/libcpu/arm/lpc17xx/start_rvds.S new file mode 100644 index 0000000000..6023780083 --- /dev/null +++ b/libcpu/arm/lpc17xx/start_rvds.S @@ -0,0 +1,266 @@ +; /*
+; * File : start_rvds.s
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-09-23 Bernard first implementation
+; * 2010-02-04 Magicoe Edit for LPC17xx Series
+; */
+
+;* <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+; not use external SRAM as data memory
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+ IMPORT rt_hw_hard_fault
+ IMPORT rt_hw_pend_sv
+ IMPORT rt_hw_timer_handler
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD rt_hw_hard_fault ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD rt_hw_pend_sv ; PendSV Handler in RT-Thread
+ DCD rt_hw_timer_handler ; SysTick Handler in RT-Thread
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+
+ LDR R1, = __initial_sp ; restore original stack pointer
+ MSR MSP, R1
+
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+RIT_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* COPYLEFT 2010 Magicoe *****END OF FILE*****
+
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