summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBernard Xiong <[email protected]>2014-07-12 10:23:41 +0800
committerBernard Xiong <[email protected]>2014-07-12 10:23:41 +0800
commitf8d2f880c31fad452e0416cd40ef22e075d59ee1 (patch)
treec155ee370402b2d033e32409b3643d362db1c90d
parent5c5928f8226698113cf0111346b01b56dedcaa72 (diff)
[bsp] Remove NUC140 porting
Diffstat
-rw-r--r--bsp/nuc140/CMSIS/CM0/NUC1xx.h2029
-rw-r--r--bsp/nuc140/CMSIS/CM0/core_cm0.c470
-rw-r--r--bsp/nuc140/CMSIS/CM0/core_cm0.h801
-rw-r--r--bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s381
-rw-r--r--bsp/nuc140/CMSIS/CM0/system_NUC1xx.c37
-rw-r--r--bsp/nuc140/CMSIS/CM0/system_NUC1xx.h39
-rw-r--r--bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm1204
-rw-r--r--bsp/nuc140/application.c26
-rw-r--r--bsp/nuc140/board.c65
-rw-r--r--bsp/nuc140/board.h20
-rw-r--r--bsp/nuc140/project.uvopt2096
-rw-r--r--bsp/nuc140/project.uvproj609
-rw-r--r--bsp/nuc140/rtconfig.h74
-rw-r--r--bsp/nuc140/startup.c111
-rw-r--r--bsp/nuc140/uart.c226
-rw-r--r--bsp/nuc140/uart.h6
16 files changed, 0 insertions, 8194 deletions
diff --git a/bsp/nuc140/CMSIS/CM0/NUC1xx.h b/bsp/nuc140/CMSIS/CM0/NUC1xx.h
deleted file mode 100644
index 18996d9250..0000000000
--- a/bsp/nuc140/CMSIS/CM0/NUC1xx.h
+++ /dev/null
@@ -1,2029 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------*/
-/* */
-/* Copyright (c) Nuvoton Technology Corp. All rights reserved. */
-/* */
-/*---------------------------------------------------------------------------------------------------------*/
-
-#ifndef __NUC1xx_H__
-#define __NUC1xx_H__
-
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-
-/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
- BOD_IRQn = 0,
- WDT_IRQn = 1,
- EINT0_IRQn = 2,
- EINT1_IRQn = 3,
- GPAB_IRQn = 4,
- GPCDE_IRQn = 5,
- PWMA_IRQn = 6,
- PWMB_IRQn = 7,
- TMR0_IRQn = 8,
- TMR1_IRQn = 9,
- TMR2_IRQn = 10,
- TMR3_IRQn = 11,
- UART0_IRQn = 12,
- UART1_IRQn = 13,
- SPI0_IRQn = 14,
- SPI1_IRQn = 15,
- SPI2_IRQn = 16,
- SPI3_IRQn = 17,
- I2C0_IRQn = 18,
- I2C1_IRQn = 19,
- CAN0_IRQn = 20,
- CAN1_IRQn = 21,
- SD_IRQn = 22,
- USBD_IRQn = 23,
- PS2_IRQn = 24,
- ACMP_IRQn = 25,
- PDMA_IRQn = 26,
- I2S_IRQn = 27,
- PWRWU_IRQn = 28,
- ADC_IRQn = 29,
- DAC_IRQn = 30,
- RTC_IRQn = 31
-
- /*!< maximum of 32 Interrupts are possible */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0 Processor and Core Peripherals */
-#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-
-#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
-#include "system_NUC1xx.h" /* NUC1xx System */
-// #include "System\SysInfra.h"
-
-
-/**
- * Initialize the system clock
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system
- * Initialize the PLL and update the SystemFrequency variable
- */
-extern void SystemInit (void);
-
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-
-/*--------------------- General Purpose Input and Ouptut ---------------------*/
-typedef struct
-{
- __IO uint32_t PMD0:2;
- __IO uint32_t PMD1:2;
- __IO uint32_t PMD2:2;
- __IO uint32_t PMD3:2;
- __IO uint32_t PMD4:2;
- __IO uint32_t PMD5:2;
- __IO uint32_t PMD6:2;
- __IO uint32_t PMD7:2;
- __IO uint32_t PMD8:2;
- __IO uint32_t PMD9:2;
- __IO uint32_t PMD10:2;
- __IO uint32_t PMD11:2;
- __IO uint32_t PMD12:2;
- __IO uint32_t PMD13:2;
- __IO uint32_t PMD14:2;
- __IO uint32_t PMD15:2;
-} GPIO_PMD_T;
-
-typedef __IO uint32_t GPIO_SCH_T;
-
-typedef __IO uint32_t GPIO_DOUT_T;
-
-typedef __IO uint32_t GPIO_DMASK_T;
-
-typedef __IO uint32_t GPIO_PIN_T;
-
-typedef __IO uint32_t GPIO_DBEN_T;
-
-typedef __IO uint32_t GPIO_IMD_T;
-
-typedef __IO uint32_t GPIO_IEN_T;
-
-typedef __IO uint32_t GPIO_ISRC_T;
-
-typedef struct
-{
- __IO uint32_t DBCLKSEL:4;
- __IO uint32_t DBCLKSRC:1;
- __IO uint32_t ICLK_ON:1;
- __I uint32_t RESERVE:26;
-} GPIO_DBNCECON_T;
-
-typedef struct
-{
- GPIO_PMD_T PMD;
- GPIO_SCH_T SCH;
- GPIO_DOUT_T DOUT;
- GPIO_DMASK_T DMASK;
- GPIO_PIN_T PIN;
- GPIO_DBEN_T DBEN;
- GPIO_IMD_T IMD;
- GPIO_IEN_T IEN;
- GPIO_ISRC_T ISRC;
-
-} GPIO_T;
-
-
-/*------------------------- UART Interface Controller ------------------------*/
-
-typedef __IO uint32_t UART_DATA_T;
-
-
-typedef struct
-{
- __IO uint32_t RDA_IEN:1;
- __IO uint32_t THRE_IEN:1;
- __IO uint32_t RLS_IEN:1;
- __IO uint32_t MS_IEN:1;
- __IO uint32_t RTO_IEN:1;
- __IO uint32_t BUF_ERR_IEN:1;
- __IO uint32_t WAKE_IEN:1;
- __I uint32_t RESERVE0:4;
- __IO uint32_t TOC_EN:1; /* Time-out counter enable */
- __IO uint32_t AUTO_RTS_EN:1;
- __IO uint32_t AUTO_CTS_EN:1;
- __IO uint32_t DMA_TX_EN:1;
- __IO uint32_t DMA_RX_EN:1;
- __I uint32_t RESERVE1:15;
- __IO uint32_t nDEBUGACK_EN:1;
-} UART_IER_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:1;
- __IO uint32_t RFR:1;
- __IO uint32_t TFR:1;
- __I uint32_t RESERVE1:1;
- __IO uint32_t RFITL:4; /* Rx FIFO Interrupt Trigger Level */
- __I uint32_t RESERVE2:8;
- __IO uint32_t RTS_TRIG_LEVEL:4;
- __I uint32_t RESERVE3:12;
-} UART_FCR_T;
-
-typedef struct
-{
- __IO uint32_t WLS:2; /* Word length select */
- __IO uint32_t NSB:1; /* Number of STOP bit */
- __IO uint32_t PBE:1; /* Parity bit enable */
- __IO uint32_t EPE:1; /* Even parity enable */
- __IO uint32_t SPE:1; /* Stick parity enable*/
- __IO uint32_t BCB:1; /* Break control bit */
- __I uint32_t RESERVE:25;
-} UART_LCR_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:1;
- __IO uint32_t RTS_INV:1;
- __I uint32_t RESERVE1:2;
- __IO uint32_t LBME:1;
- __I uint32_t RESERVE2:4;
- __IO uint32_t RTS_ACT_LEVEL:1;
- __I uint32_t RESERVE3:3;
- __I uint32_t RTS:1; /* RTS status */
- __I uint32_t RESERVE4:18;
-} UART_MCR_T;
-
-typedef struct
-{
- __IO uint32_t DCTS:1;
- __I uint32_t RESERVE0:3;
- __I uint32_t CTS:1; /* CTS status */
- __I uint32_t RESERVE1:3;
- __IO uint32_t CTS_ACT_LEVEL:1;
- __I uint32_t RESERVE2:23;
-} UART_MSR_T;
-
-typedef struct
-{
- __IO uint32_t RX_OVERFLOW:1;
- __I uint32_t RESERVE0:3;
- __IO uint32_t PEI:1;
- __IO uint32_t FEI:1;
- __IO uint32_t BII:1;
- __I uint32_t RESERVE1:1;
- __I uint32_t RX_POINTER:6;
- __I uint32_t RX_EMPTY:1;
- __I uint32_t RX_FULL:1;
- __I uint32_t TX_POINTER:6;
- __I uint32_t TX_EMPTY:1;
- __I uint32_t TX_FULL:1;
- __IO uint32_t TX_OVERFLOW:1;
- __I uint32_t RESERVE2:3;
- __I uint32_t TE:1; /* Transmitter empty flag */
- __I uint32_t RESERVE3:3;
-} UART_FSR_T;
-
-typedef struct
-{
- __IO uint32_t RDA_IF:1;
- __IO uint32_t THRE_IF:1;
- __IO uint32_t RLS_IF:1;
- __IO uint32_t MODEM_IF:1;
- __IO uint32_t TOUT_IF:1;
- __IO uint32_t BUF_ERR_IF:1;
- __IO uint32_t WAKE_IF:1;
- __IO uint32_t SW_TX:1;
- __IO uint32_t RDA_INT:1;
- __IO uint32_t THRE_INT:1;
- __IO uint32_t RLS_INT:1;
- __IO uint32_t MODEM_INT:1;
- __IO uint32_t TOUT_INT:1;
- __IO uint32_t BUF_ERR_INT:1;
- __IO uint32_t WAKE_INT:1;
- __IO uint32_t SW_RX:1;
- __I uint32_t RESERVE0:2;
- __IO uint32_t HW_RLS_IF:1;
- __IO uint32_t HW_MODEM_IF:1;
- __IO uint32_t HW_TOUT_IF:1;
- __IO uint32_t HW_BUF_ERR_IF:1;
- __IO uint32_t HW_WAKE_IF:1;
- __IO uint32_t EDMA_TX:1;
- __I uint32_t RESERVE1:2;
- __IO uint32_t HW_RLS_INT:1;
- __IO uint32_t HW_MODEM_INT:1;
- __IO uint32_t HW_TOUT_INT:1;
- __IO uint32_t HW_BUF_ERR_INT:1;
- __IO uint32_t HW_WAKE_INT:1;
- __IO uint32_t EDMA_RX:1;
-} UART_ISR_T;
-
-typedef __IO uint32_t UART_TOR_T;
-
-typedef struct
-{
- __IO uint32_t DIV:16;
- __I uint32_t RESERVE0:8;
- __IO uint32_t DIVX:4;
- __IO uint32_t DIVX1:1;
- __IO uint32_t DIVX_EN:1;
- __I uint32_t RESERVE1:2;
-} UART_BAUD_T;
-
-typedef struct
-{
- __IO uint32_t IrDA_EN:1;
- __I uint32_t RESERVE0:2;
- __IO uint32_t RX_EN:1;
- __IO uint32_t TX_EN:1;
- __IO uint32_t TX_INV_EN:1;
- __IO uint32_t RX_INV_EN:1;
- __I uint32_t RESERVE1:25;
-} UART_IRCR_T;
-
-typedef struct
-{
- __IO uint32_t LINBCNT:4;
- __I uint32_t RESERVE0:2;
- __IO uint32_t LINRX_EN:1;
- __IO uint32_t LINTX_EN:1;
- __I uint32_t RESERVE1:24;
-} UART_LINCON_T;
-
-
-
-typedef struct
-{
- __IO uint32_t LIN_EN:2;
- __IO uint32_t IrDA_EN:2;
- __I uint32_t RESERVE0:32;
-
-} UART_FUNSEL_T;
-
-
-typedef struct
-{
- UART_DATA_T DATA;
- UART_IER_T IER;
- UART_FCR_T FCR;
- UART_LCR_T LCR;
- UART_MCR_T MCR;
- UART_MSR_T MSR;
- UART_FSR_T FSR;
- UART_ISR_T ISR;
- UART_TOR_T TOR;
- UART_BAUD_T BAUD;
- UART_IRCR_T IRCR;
- UART_LINCON_T LINCON;
- UART_FUNSEL_T FUNSEL;
-} UART_T;
-
-/*----------------------------- Timer Controller -----------------------------*/
-typedef struct
-{
- __IO uint32_t PRESCALE:8;
- __I uint32_t RESERVE0:8;
- __IO uint32_t TDR_EN:1;
- __I uint32_t RESERVE1:8;
- __IO uint32_t CACT:1;
- __IO uint32_t CRST:1;
- __IO uint32_t MODE:2;
- __IO uint32_t IE:1;
- __IO uint32_t CEN:1;
- __IO uint32_t nDBGACK_EN:1;
-} TIMER_TCSR_T;
-
-typedef __IO uint32_t TIMER_TICR_T;
-
-typedef __IO uint32_t TIMER_TDR_T;
-
-typedef struct
-{
- __IO uint32_t TIF:1;
- __I uint32_t RESERVE:31;
-} TIMER_TISR_T;
-
-typedef struct
-{
- TIMER_TCSR_T TCSR;
- TIMER_TICR_T TICR;
- TIMER_TISR_T TISR;
- TIMER_TDR_T TDR;
- } TIMER_T;
-
-
-/*----------------------------- WDT Controller -----------------------------*/
-typedef struct
-{
- __IO uint32_t WTR:1;
- __IO uint32_t WTRE:1;
- __IO uint32_t WTRF:1;
- __IO uint32_t WTIF:1;
- __I uint32_t RESERVE:2;
- __IO uint32_t WTIE:1;
- __IO uint32_t WTE:1;
- __IO uint32_t WTIS:3;
- __I uint32_t RESERVE1:21;
-} WDT_WTCR_T;
-
-typedef struct
-{
- WDT_WTCR_T WTCR;
-
- } WDT_T;
-
-/*------------------------- SPI Interface Controller -------------------------*/
-typedef struct
-{
- __IO uint32_t GO_BUSY:1;
- __IO uint32_t RX_NEG:1;
- __IO uint32_t TX_NEG:1;
- __IO uint32_t TX_BIT_LEN:5;
- __IO uint32_t TX_NUM:2;
- __IO uint32_t LSB:1;
- __IO uint32_t CLKP:1;
- __IO uint32_t SLEEP:4;
- __IO uint32_t IF:1;
- __IO uint32_t IE:1;
- __IO uint32_t SLAVE:1;
- __IO uint32_t BYTE_SLEEP:1;
- __IO uint32_t BYTE_ENDIAN:1;
- __IO uint32_t FOURB:1;
- __IO uint32_t TWOB:1;
- __IO uint32_t VARCLK_EN:1;
- __I uint32_t RESERVE:8;
-} SPI_CNTRL_T;
-
-typedef struct
-{
- __IO uint32_t DIVIDER:16;
- __IO uint32_t DIVIDER2:16;
-} SPI_DIVIDER_T;
-
-typedef struct
-{
- __IO uint32_t SSR:2;
- __IO uint32_t SS_LVL:1;
- __IO uint32_t ASS:1;
- __IO uint32_t SS_LTRIG:1;
- __IO uint32_t LTRIG_FLAG:1;
- __I uint32_t RESERVE:26;
-} SPI_SSR_T;
-
-
-typedef __I uint32_t SPI_RX_T;
-typedef __O uint32_t SPI_TX_T;
-
-typedef struct
-{
- __IO uint32_t JS:1;
- __I uint32_t RESERVE0:3;
- __IO uint32_t JS_RW:1;
- __IO uint32_t CS_ACT:1;
- __IO uint32_t DATA_RDY:1;
- __IO uint32_t CS_DEACT:1;
- __IO uint32_t READYB:1;
- __I uint32_t RESERVE1:23;
-} SPI_JS_T;
-
-typedef __IO uint32_t SPI_VARCLK_T;
-
-typedef struct
-{
- __IO uint32_t TX_DMA_GO:1;
- __IO uint32_t RX_DMA_GO:1;
- __I uint32_t RESERVE:30;
-} SPI_DMA_T;
-
-typedef struct
-{
- SPI_CNTRL_T CNTRL;
- SPI_DIVIDER_T DIVIDER;
- SPI_SSR_T SSR;
- uint32_t RESERVE0;
- SPI_RX_T RX[2];
- uint32_t RESERVE1;
- uint32_t RESERVE2;
- SPI_TX_T TX[2];
- uint32_t RESERVE3;
- uint32_t RESERVE4;
- SPI_JS_T JS;
- SPI_VARCLK_T VARCLK;
- SPI_DMA_T DMA;
-} SPI_T;
-
-/*------------------------------ I2C Controller ------------------------------*/
-typedef struct
-{
- __I uint32_t RESERVE0:2;
- __IO uint32_t AA:1;
- __IO uint32_t SI:1;
- __IO uint32_t STO:1;
- __IO uint32_t STA:1;
- __IO uint32_t ENSI:1;
- __IO uint32_t EI:1;
- __I uint32_t RESERVE1:24;
-} I2C_CON_T;
-
-typedef struct
-{
- __IO uint32_t GC:1;
- __IO uint32_t ADDR:7;
- __I uint32_t RESERVE:24;
-} I2C_ADDR_T;
-
-typedef __IO uint32_t I2C_DATA_T;
-
-typedef __I uint32_t I2C_STATUS_T;
-
-typedef __IO uint32_t I2C_CLK_T;
-
-typedef struct
-{
- __IO uint32_t TIF:1;
- __IO uint32_t DIV4:1;
- __IO uint32_t ENTI:1;
- __I uint32_t RESERVE:29;
-} I2C_TOC_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:1;
- __IO uint32_t ADM:7;
- __I uint32_t RESERVE1:24;
-} I2C_ADRM_T;
-
-typedef struct
-{
- I2C_CON_T CON;
- I2C_ADDR_T ADDR0;
- I2C_DATA_T DATA;
- I2C_STATUS_T STATUS;
- I2C_CLK_T CLK;
- I2C_TOC_T TOC;
- I2C_ADDR_T ADDR1;
- I2C_ADDR_T ADDR2;
- I2C_ADDR_T ADDR3;
- I2C_ADRM_T ADRM0;
- I2C_ADRM_T ADRM1;
- I2C_ADRM_T ADRM2;
- I2C_ADRM_T ADRM3;
-} I2C_T;
-
-
-/*----------------------------- RTC Controller -------------------------------*/
-
-typedef __IO uint32_t RTC_INIR_T;
-
-typedef struct
-{
- __IO uint32_t AER:16;
- __I uint32_t ENF:1;
- __I uint32_t RESERVE1:15;
-} RTC_AER_T;
-
-typedef struct
-{
- __IO uint32_t FRACTION:6;
- __I uint32_t RESERVE0:2;
- __IO uint32_t INTEGER:4;
- __I uint32_t RESERVE1:20;
-} RTC_FCR_T;
-
-typedef struct
-{
- __IO uint32_t SEC1:4;
- __IO uint32_t SEC10:3;
- __I uint32_t RESERVE0:1;
- __IO uint32_t MIN1:4;
- __IO uint32_t MIN10:3;
- __I uint32_t RESERVE1:1;
- __IO uint32_t HR1:4;
- __IO uint32_t HR10:2;
- __I uint32_t RESERVE2:10;
-} RTC_TLR_T;
-
-typedef struct
-{
- __IO uint32_t DAY1:4;
- __IO uint32_t DAY10:2;
- __I uint32_t RESERVE0:2;
- __IO uint32_t MON1:4;
- __IO uint32_t MON10:1;
- __I uint32_t RESERVE1:3;
- __IO uint32_t YEAR1:4;
- __IO uint32_t YEAR10:4;
- __I uint32_t RESERVE2:8;
-} RTC_CLR_T;
-
-typedef struct
-{
- __IO uint32_t HR24:1;
- __I uint32_t RESERVE:31;
-} RTC_TSSR_T;
-
-typedef struct
-{
- __IO uint32_t DWR:3;
- __I uint32_t RESERVE:29;
-} RTC_DWR_T;
-
-typedef RTC_TLR_T RTC_TAR_T;
-typedef RTC_CLR_T RTC_CAR_T;
-
-typedef struct
-{
- __IO uint32_t LIR:1;
- __I uint32_t RESERVE:31;
-} RTC_LIR_T;
-
-typedef struct
-{
- __IO uint32_t AIER:1;
- __IO uint32_t TIER:1;
- __I uint32_t RESERVE:30;
-} RTC_RIER_T;
-
-
-//typedef __IO uint32_t RTC_RIIR_T;
-
-typedef struct
-{
- __IO uint32_t AI:1;
- __IO uint32_t TI:1;
- __I uint32_t RESERVE:30;
-} RTC_RIIR_T;
-
-typedef struct
-{
- __IO uint32_t TTR:3;
- __I uint32_t RESERVE:30;
-} RTC_TTR_T;
-
-typedef struct
-{
- __IO uint32_t PTOUT:16;
- __I uint32_t RESERVE0:7;
- __IO uint32_t PWROFF:1;
- __I uint32_t RESERVE1:8;
-} RTC_PWRCON_T;
-
-typedef struct
-{
- RTC_INIR_T INIR;
- RTC_AER_T AER;
- RTC_FCR_T FCR;
- RTC_TLR_T TLR;
- RTC_CLR_T CLR;
- RTC_TSSR_T TSSR;
- RTC_DWR_T DWR;
- RTC_TAR_T TAR;
- RTC_CAR_T CAR;
- RTC_LIR_T LIR;
- RTC_RIER_T RIER;
- RTC_RIIR_T RIIR;
- RTC_TTR_T TTR;
- RTC_PWRCON_T PWRCON;
-} RTC_T;
-
-
-/*----------------------------- ADC Controller -------------------------------*/
-typedef struct
-{
- __IO uint32_t RSLT:16;
- __IO uint32_t OVERRUN:1;
- __IO uint32_t VALID:1;
- __I uint32_t RESERVE1:14;
-} ADC_ADDR_T;
-
-typedef struct
-{
- __IO uint32_t ADEN:1;
- __IO uint32_t ADIE:1;
- __IO uint32_t ADMD:2;
- __IO uint32_t TRGS:2;
- __IO uint32_t TRGCOND:2;
- __IO uint32_t TRGEN:1;
- __IO uint32_t PTEN:1;
- __IO uint32_t DIFF:1;
- __IO uint32_t ADST:1;
- __I uint32_t RESERVE0:4;
- __IO uint32_t ADCLKDIV:7;
- __I uint32_t RESERVE1:9;
-} ADC_ADCR_T;
-
-
-
-typedef struct
-{
- __IO uint32_t CHEN:8;
- __IO uint32_t PRESEL:2;
- __I uint32_t RESERVE:22;
-} ADC_ADCHER_T;
-
-
-typedef struct
-{
- __IO uint32_t CMPEN:1;
- __IO uint32_t CMPIE:1;
- __IO uint32_t CMPCOND:1;
- __IO uint32_t CMPCH:3;
- __I uint32_t RESERVE0:2;
- __IO uint32_t CMPMATCNT:4;
- __I uint32_t RESERVE1:4;
- __IO uint32_t CMPD:12;
- __I uint32_t RESERVE2:4;
-} ADC_ADCMPR_T;
-
-typedef struct
-{
- __IO uint32_t ADF:1;
- __IO uint32_t CMPF0:1;
- __IO uint32_t CMPF1:1;
- __IO uint32_t BUSY:1;
- __IO uint32_t CHANNEL:3;
- __I uint32_t RESERVE0:1;
- __IO uint32_t VALID:8;
- __IO uint32_t OVERRUN:8;
- __I uint32_t RESERVE1:8;
-} ADC_ADSR_T;
-
-typedef struct
-{
- __IO uint32_t CALEN:1;
- __IO uint32_t CALDONE:1;
- __I uint32_t RESERVE:30;
-} ADC_ADCALR_T;
-
-typedef struct
-{
- ADC_ADDR_T ADDR[8];
- ADC_ADCR_T ADCR;
- ADC_ADCHER_T ADCHER;
- ADC_ADCMPR_T ADCMPR[2];
- ADC_ADSR_T ADSR;
- ADC_ADCALR_T ADCALR;
-
-} ADC_T;
-
-/*---------------------- Analog Comparator Controller -------------------------*/
-typedef struct
-{
- __IO uint32_t CMPEN:1;
- __IO uint32_t CMPIE:1;
- __IO uint32_t CMP_HYSEN:1;
- __IO uint32_t CP:1;
- __IO uint32_t CN:1;
- __IO uint32_t COE:1;
- __I uint32_t RESERVE:26;
-} ACMP_CMPCR_T;
-
-typedef struct
-{
- __IO uint32_t CMPF1:1;
- __IO uint32_t CMPF2:1;
- __IO uint32_t CO1:1;
- __IO uint32_t CO2:1;
- __I uint32_t RESERVE:28;
-} ACMP_CMPSR_T;
-
-typedef struct
-{
- ACMP_CMPCR_T CMPCR[2];
- ACMP_CMPSR_T CMPSR;
-} ACMP_T;
-
-/*---------------------------- Clock Controller ------------------------------*/
-typedef struct
-{
- __IO uint32_t XTL12M_EN:1;
- __IO uint32_t XTL32K_EN:1;
- __IO uint32_t OSC22M_EN:1;
- __IO uint32_t OSC10K_EN:1;
- __IO uint32_t WU_DLY:1;
- __IO uint32_t WINT_EN:1;
- __IO uint32_t PD_WU_STS:1;
- __IO uint32_t PWR_DOWN:1;
- __IO uint32_t PD_WAIT_CPU:1;
- __I uint32_t RESERVE:23;
-} SYSCLK_PWRCON_T;
-
-typedef struct
-{
- __IO uint32_t CPU_EN:1;
- __IO uint32_t PDMA_EN:1;
- __IO uint32_t ISP_EN:1;
- __I uint32_t RESERVE:29;
-} SYSCLK_AHBCLK_T;
-
-typedef struct
-{
- __IO uint32_t WDG_EN:1;
- __IO uint32_t RTC_EN:1;
- __IO uint32_t TMR0_EN:1;
- __IO uint32_t TMR1_EN:1;
- __IO uint32_t TMR2_EN:1;
- __IO uint32_t TMR3_EN:1;
- __I uint32_t RESERVE0:2;
- __IO uint32_t I2C0_EN:1;
- __IO uint32_t I2C1_EN:1;
- __I uint32_t RESERVE1:2;
- __IO uint32_t SPI0_EN:1;
- __IO uint32_t SPI1_EN:1;
- __IO uint32_t SPI2_EN:1;
- __IO uint32_t SPI3_EN:1;
- __IO uint32_t UART0_EN:1;
- __IO uint32_t UART1_EN:1;
- __I uint32_t RESERVE2:2;
- __IO uint32_t PWM01_EN:1;
- __IO uint32_t PWM23_EN:1;
- __I uint32_t RESERVE3:2;
- __IO uint32_t CAN0_EN:1;
- __IO uint32_t CAN1_EN:1;
- __I uint32_t RESERVE4:1;
- __IO uint32_t USBD_EN:1;
- __IO uint32_t ADC_EN:1;
- __I uint32_t RESERVE5:1;
- __IO uint32_t ACMP_EN:1;
- __IO uint32_t PS2_EN:1;
-} SYSCLK_APBCLK_T;
-
-typedef struct
-{
- __IO uint32_t HCLK_S:3;
- __IO uint32_t STCLK_S:3;
- __I uint32_t RESERVE:26;
-} SYSCLK_CLKSEL0_T;
-
-
-typedef struct
-{
- __IO uint32_t WDG_S:2;
- __IO uint32_t ADC_S:2;
- __I uint32_t RESERVE1:4;
- __IO uint32_t TMR0_S:3;
- __I uint32_t RESERVE2:1;
- __IO uint32_t TMR1_S:3;
- __I uint32_t RESERVE3:1;
- __IO uint32_t TMR2_S:3;
- __I uint32_t RESERVE4:1;
- __IO uint32_t TMR3_S:3;
- __I uint32_t RESERVE5:1;
- __IO uint32_t UART_S:2;
- __IO uint32_t CAN_S:2;
- __IO uint32_t PWM10_S:2;
- __IO uint32_t PWM32_S:2;
-} SYSCLK_CLKSEL1_T;
-
-typedef struct
-{
- __IO uint32_t HCLK_N:4;
- __IO uint32_t USB_N:4;
- __IO uint32_t UART_N:4;
- __IO uint32_t CAN_N:4;
- __IO uint32_t ADC_N:8;
- __I uint32_t RESERVE:8;
-} SYSCLK_CLKDIV_T;
-
-typedef struct
-{
- __IO uint32_t FB_DV:9;
- __IO uint32_t IN_DV:5;
- __IO uint32_t OUT_DV:2;
- __IO uint32_t PD:1;
- __IO uint32_t BP:1;
- __IO uint32_t OE:1;
- __IO uint32_t PLL_SRC:1;
- __I uint32_t RESERVE:12;
-} SYSCLK_PLLCON_T;
-
-typedef struct
-{
- __IO uint32_t TEST_SEL:8;
- __I uint32_t RESERVE:24;
-} SYSCLK_TREG_T;
-
-typedef struct
-{
- SYSCLK_PWRCON_T PWRCON;
- SYSCLK_AHBCLK_T AHBCLK;
- SYSCLK_APBCLK_T APBCLK;
- uint32_t RESERVED0;
- SYSCLK_CLKSEL0_T CLKSEL0;
- SYSCLK_CLKSEL1_T CLKSEL1;
- SYSCLK_CLKDIV_T CLKDIV;
- uint32_t RESERVED1;
- SYSCLK_PLLCON_T PLLCON;
-
-} SYSCLK_T;
-
-/*---------------------------- Global Controller -----------------------------*/
-typedef __I uint32_t GCR_PDID_T;
-
-typedef struct
-{
- __IO uint32_t RSTS_POR:1;
- __IO uint32_t RSTS_PAD:1;
- __IO uint32_t RSTS_WDG:1;
- __IO uint32_t RSTS_LVR:1;
- __IO uint32_t RSTS_BOD:1;
- __IO uint32_t RSTS_MCU:1;
- __IO uint32_t RSTS_PMU:1;
- __I uint32_t RESERVE:25;
-} GCR_RSTSRC_T;
-
-
-typedef struct
-{
- __IO uint32_t CHIP_RST:1;
- __IO uint32_t CPU_RST:1;
- __IO uint32_t PDMA_RST:1;
- __I uint32_t RESERVE:29;
-} GCR_IPRSTC1_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:1;
- __IO uint32_t GPIO_RST:1;
- __IO uint32_t TMR0_RST:1;
- __IO uint32_t TMR1_RST:1;
- __IO uint32_t TMR2_RST:1;
- __IO uint32_t TMR3_RST:1;
- __I uint32_t RESERVE1:2;
- __IO uint32_t I2C0_RST:1;
- __IO uint32_t I2C1_RST:1;
- __I uint32_t RESERVE2:2;
- __IO uint32_t SPI0_RST:1;
- __IO uint32_t SPI1_RST:1;
- __IO uint32_t SPI2_RST:1;
- __IO uint32_t SPI3_RST:1;
- __IO uint32_t UART0_RST:1;
- __IO uint32_t UART1_RST:1;
- __I uint32_t RESERVE3:2;
- __IO uint32_t PWM_RST:1;
- __I uint32_t RESERVE4:1;
- __IO uint32_t ACMP_RST:1;
- __IO uint32_t PS2_RST:1;
- __IO uint32_t CAN0_RST:1;
- __IO uint32_t CAN1_RST:1;
- __I uint32_t RESERVE5:1;
- __IO uint32_t USBD_RST:1;
- __IO uint32_t ADC_RST:1;
- __I uint32_t RESERVE6:3;
-} GCR_IPRSTC2_T;
-
-typedef __IO uint32_t GCR_MISCR_T;
-
-
-typedef struct
-{
- __IO uint32_t BOD_EN:1;
- __IO uint32_t BOD_VL:2;
- __IO uint32_t BOD_RSTEN:1;
- __IO uint32_t BOD_BYP_EN:1;
- __IO uint32_t BOD_LPM:1;
- __IO uint32_t BOD_OUT:1;
- __IO uint32_t LVR_EN:1;
- __IO uint32_t VTEMP_EN:1;
- __IO uint32_t LDO_BYP:1;
- __I uint32_t RESERVE1:22;
-} GCR_BODCR_T;
-
-typedef __IO uint32_t GCR_PORCR_T;
-
-
-typedef struct
-{
- __IO uint32_t ADC0:1;
- __IO uint32_t ADC1:1;
- __IO uint32_t ADC2:1;
- __IO uint32_t ADC3:1;
- __IO uint32_t ADC4:1;
- __IO uint32_t ADC5:1;
- __IO uint32_t ADC6:1;
- __IO uint32_t ADC7:1;
- __IO uint32_t I2C0_SDA:1;
- __IO uint32_t I2C0_SCL:1;
- __IO uint32_t I2C1_SDA:1;
- __IO uint32_t I2C1_SCL:1;
- __IO uint32_t PWM0:1;
- __IO uint32_t PWM1:1;
- __IO uint32_t PWM2:1;
- __IO uint32_t PWM3:1;
- __IO uint32_t SCHMITT:16;
-} GCR_GPAMFP_T;
-
-typedef struct
-{
- __IO uint32_t UART0_RX:1;
- __IO uint32_t UART0_TX:1;
- __IO uint32_t UART0_nRTS:1;
- __IO uint32_t UART0_nCTS:1;
- __IO uint32_t UART1_RX:1;
- __IO uint32_t UART1_TX:1;
- __IO uint32_t UART1_nRTS:1;
- __IO uint32_t UART1_nCTS:1;
- __IO uint32_t TM0:1;
- __IO uint32_t TM1:1;
- __IO uint32_t TM2:1;
- __IO uint32_t TM3:1;
- __IO uint32_t CPO0:1;
- __IO uint32_t CPO1:1;
- __IO uint32_t INT0:1;
- __IO uint32_t INT1:1;
- __IO uint32_t SCHMITT:16;
-} GCR_GPBMFP_T;
-
-typedef struct
-{
- __IO uint32_t SPI0_SS0:1;
- __IO uint32_t SPI0_CLK:1;
- __IO uint32_t SPI0_MISO0:1;
- __IO uint32_t SPI0_MOSI0:1;
- __IO uint32_t SPI0_MISO1:1;
- __IO uint32_t SPI0_MOSI1:1;
- __IO uint32_t CPP0:1;
- __IO uint32_t CPN0:1;
- __IO uint32_t SPI1_SS0:1;
- __IO uint32_t SPI1_CLK:1;
- __IO uint32_t SPI1_MISO0:1;
- __IO uint32_t SPI1_MOSI0:1;
- __IO uint32_t SPI1_MISO1:1;
- __IO uint32_t SPI1_MOSI1:1;
- __IO uint32_t CPP1:1;
- __IO uint32_t CPN1:1;
- __IO uint32_t SCHMITT:16;
-} GCR_GPCMFP_T;
-
-typedef struct
-{
- __IO uint32_t SPI2_SS0:1;
- __IO uint32_t SPI2_CLK:1;
- __IO uint32_t SPI2_MISO0:1;
- __IO uint32_t SPI2_MOSI0:1;
- __IO uint32_t SPI2_MISO1:1;
- __IO uint32_t SPI2_MOSI1:1;
- __IO uint32_t CAN0_RX:1;
- __IO uint32_t CAN0_TX:1;
- __IO uint32_t SPI3_SS0:1;
- __IO uint32_t SPI3_CLK:1;
- __IO uint32_t SPI3_MISO0:1;
- __IO uint32_t SPI3_MOSI0:1;
- __IO uint32_t SPI3_MISO1:1;
- __IO uint32_t SPI3_MOSI1:1;
- __IO uint32_t CAN1_RX:1;
- __IO uint32_t CAN1_TX:1;
- __IO uint32_t SCHMITT:16;
-} GCR_GPDMFP_T;
-
-
-typedef struct
-{
- __I uint32_t RESERVE:16;
- __IO uint32_t SCHMITT:16;
-} GCR_GPEMFP_T;
-
-typedef struct
-{
- __IO uint32_t SPI0_SS1:1; /* GPB10 */
- __IO uint32_t SPI1_SS1:1; /* GPB9 */
- __IO uint32_t SPI2_SS1:1; /* GPA7 */
- __IO uint32_t SPI3_SS1:1; /* GPB14 */
- __I uint32_t RESERVE:28;
-
-} GCR_USPIMFP_T;
-
-typedef __IO uint32_t GCR_REGLOCK_T;
-typedef __IO uint32_t GCR_RCADJ_T;
-
-
-typedef struct
-{
- __IO uint32_t INTSRC:3;
- __I uint32_t RESERVE:29;
-} GCR_INTSRC_T;
-
-typedef struct
-{
- __IO uint32_t NMISEL:5;
- __I uint32_t RESERVE0:2;
- __IO uint32_t INT_TEST:1;
- __I uint32_t RESERVE1:24;
-} GCR_NMISEL_T;
-
-
-typedef __IO uint32_t GCR_MCUIRQ_T;
-
-typedef struct
-{
- GCR_PDID_T PDID;
- GCR_RSTSRC_T RSTSRC;
- GCR_IPRSTC1_T IPRSTC1;
- GCR_IPRSTC2_T IPRSTC2;
- uint32_t RESERVE0;
- GCR_MISCR_T MISCR;
- GCR_BODCR_T BODCR;
- GCR_PORCR_T PORCR;
- uint32_t RESERVE1[4];
- GCR_GPAMFP_T GPAMFP;
- GCR_GPBMFP_T GPBMFP;
- GCR_GPCMFP_T GPCMFP;
- GCR_GPDMFP_T GPDMFP;
- GCR_GPEMFP_T GPEMFP;
- uint32_t RESERVE2[3];
- GCR_USPIMFP_T USPIMFP;
- uint32_t RESERVE3[43];
- GCR_REGLOCK_T REGLOCK;
- uint32_t RESERVE4[3];
- GCR_RCADJ_T RCADJ;
-} GCR_T;
-
-
-
-typedef struct
-{
- GCR_INTSRC_T INTSRC;
- GCR_NMISEL_T NMISEL;
- GCR_MCUIRQ_T MCUIRQ;
-} GCR_INT_T;
-
-/*-------------------------- FLASH Memory Controller -------------------------*/
-typedef struct
-{
- __IO uint32_t ISPEN:1;
- __IO uint32_t BS:1;
- __I uint32_t RESERVE0:3;
- __IO uint32_t LDUEN:1;
- __IO uint32_t ISPFF:1;
- __IO uint32_t SWRST:1;
- __IO uint32_t PT:3;
- __I uint32_t RESERVE1:1;
- __IO uint32_t ET:3;
- __I uint32_t RESERVE2:17;
-
-} FMC_ISPCON_T;
-
-typedef __IO uint32_t FMC_ISPADR_T;
-typedef __IO uint32_t FMC_ISPDAT_T;
-
-typedef struct
-{
- __IO uint32_t FCTRL:4;
- __IO uint32_t FCEN:1;
- __IO uint32_t FOEN:1;
- __I uint32_t RESERVE:26;
-} FMC_ISPCMD_T;
-
-typedef struct
-{
- __IO uint32_t ISPGO:1;
- __I uint32_t RESERVE:31;
-} FMC_ISPTRG_T;
-
-typedef __I uint32_t FMC_DFBADR_T;
-
-typedef struct
-{
- __IO uint32_t FPSEN:1;
- __IO uint32_t FATS:3;
- __I uint32_t RESERVE:28;
-} FMC_FATCON_T;
-
-typedef struct
-{
- FMC_ISPCON_T ISPCON;
- FMC_ISPADR_T ISPADR;
- FMC_ISPDAT_T ISPDAT;
- FMC_ISPCMD_T ISPCMD;
- FMC_ISPTRG_T ISPTRG;
- FMC_DFBADR_T DFBADR;
- FMC_FATCON_T FATCON;
-} FMC_T;
-
-
-/*------------------------ PS2 Device Interface Controller -------------------*/
-typedef struct
-{
- __IO uint32_t PS2EN:1;
- __IO uint32_t TXINTEN:1;
- __IO uint32_t RXINTEN:1;
- __IO uint32_t TXFIFO_DEPTH:4;
- __IO uint32_t ACK:1;
- __IO uint32_t CLRFIFO:1;
- __IO uint32_t OVERRIDE:1;
- __IO uint32_t FPS2CLK:1;
- __IO uint32_t FPS2DAT:1;
- __I uint32_t RESERVE:20;
-} PS2_CON_T;
-
-typedef __IO uint32_t PS2_DATA_T;
-
-typedef struct
-{
- __IO uint32_t PS2CLK:1;
- __IO uint32_t PS2DATA:1;
- __IO uint32_t FRAMERR:1;
- __IO uint32_t RXPARTY:1;
- __IO uint32_t RXBUSY:1;
- __IO uint32_t TXBUSY:1;
- __IO uint32_t RXOVF:1;
- __IO uint32_t TXEMPTY:1;
- __IO uint32_t BYTEIDX:4;
- __I uint32_t RESERVE:20;
-} PS2_STATUS_T;
-
-typedef __IO uint32_t PS2_INTID_T;
-
-typedef struct
-{
- PS2_CON_T PS2CON;
- PS2_DATA_T TXDATA[4];
- PS2_DATA_T RXDATA;
- PS2_STATUS_T STATUS;
- PS2_INTID_T INTID;
-} PS2_T;
-
-/*---------------------------- CAN Bus Controller ----------------------------*/
-typedef struct
-{
- __IO uint32_t RSTM:1;
- __IO uint32_t LOM:1;
- __I uint32_t RESERVE:30;
-
-} CAN_OPMODE_T;
-
-typedef struct
-{
- __IO uint32_t TR:1;
- __IO uint32_t ABRT:1;
- __I uint32_t RESERVE2:3;
- __IO uint32_t OVERFLOAD_EN:1;
- __IO uint32_t WAKEUP_EN:1;
- __IO uint32_t CAN_EN:1;
- __I uint32_t RESERVE:24;
-} CAN_CMD_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:3;
- __IO uint32_t TCS:1;
- __IO uint32_t RS:1;
- __IO uint32_t TS:1;
- __IO uint32_t BS:1;
- __IO uint32_t BS2:1;
- __IO uint32_t EAS:1;
- __IO uint32_t EPS:1;
- __I uint32_t RESERVE1:22;
-} CAN_BSR_T;
-
-typedef struct
-{
- __IO uint32_t RI:1;
- __IO uint32_t TI:1;
- __I uint32_t RESERVE0:2;
- __IO uint32_t WUI:1;
- __I uint32_t RESERVE1:1;
- __IO uint32_t ALI:1;
- __IO uint32_t BEI:1;
- __I uint32_t RESERVE2:24;
-} CAN_INTR_T;
-
-typedef struct
-{
- __IO uint32_t RIE:1;
- __IO uint32_t TIE:1;
- __I uint32_t RESERVE0:2;
- __IO uint32_t WUIE:1;
- __I uint32_t RESERVE1:1;
- __IO uint32_t ALIE:1;
- __IO uint32_t BEIE:1;
- __I uint32_t RESERVE2:24;
-} CAN_INTEN_T;
-
-typedef struct
-{
- __IO uint32_t BRP:4;
- __IO uint32_t SJW:2;
- __IO uint32_t TSEG1:5;
- __IO uint32_t TSEG2:4;
- __IO uint32_t SAMP:1;
- __I uint32_t RESERVE2:16;
-} CAN_BTIMR_T;
-
-typedef struct
-{
- __IO uint32_t BIT_ERR:4;
- __IO uint32_t ACK_ERR:2;
- __IO uint32_t CRC_ERR:5;
- __IO uint32_t FORM_ERR:4;
- __IO uint32_t STUFF_ERR:1;
- __I uint32_t RESERVE:16;
-} CAN_ERRCR_T;
-
-typedef struct
-{
- __IO uint32_t RECNT:8;
- __I uint32_t RESERVE:24;
-} CAN_RECNTR_T;
-
-typedef struct
-{
- __IO uint32_t TECNT:8;
- __I uint32_t RESERVE:24;
-} CAN_TECNTR_T;
-
-typedef struct
-{
- __IO uint32_t TXDLC:6;
- __IO uint32_t TXRTR:1;
- __IO uint32_t TXFF:1;
- __I uint32_t RESERVE:24;
-} CAN_TXFINFO_T;
-
-typedef struct
-{
- __I uint32_t RESERVE:3;
- __IO uint32_t TXID:29;
-} CAN_TXID_T;
-
-typedef __IO uint32_t CAN_TXDATA_T;
-
-typedef struct
-{
- __IO uint32_t RXDLC:4;
- __I uint32_t RESERVE0:2;
- __IO uint32_t RXRTR:1;
- __IO uint32_t RXIDE:1;
- __I uint32_t RESERVE1:24;
-} CAN_RXFINFO_T;
-
-typedef struct
-{
- __I uint32_t RESERVE:3;
- __IO uint32_t RXID:29;
-} CAN_RXID_T;
-
-typedef __IO uint32_t CAN_RXDATA_T;
-
-typedef struct
-{
- __I uint32_t RESERVE:3;
- __IO uint32_t ACR:29;
-} CAN_ACR_T;
-
-typedef struct
-{
- __I uint32_t RESERVE:3;
- __IO uint32_t AMR:29;
-} CAN_AMR_T;
-
-
-typedef struct
-{
- __I uint32_t RESERVE:32;
-} CAN_RESERVE_T;
-
-typedef struct
-{
- CAN_OPMODE_T OPMODE;
- CAN_CMD_T CMD;
- CAN_BSR_T BSR;
- CAN_INTR_T INTR;
-
- CAN_INTEN_T INTEN;
- CAN_BTIMR_T BTIMR;
- CAN_RESERVE_T PROTECT[2];
-
- CAN_ERRCR_T ERRCR;
- CAN_RESERVE_T PROTECT1;
- CAN_RECNTR_T RECNTR;
- CAN_TECNTR_T TECNTR;
-
- CAN_TXFINFO_T TXFINFO;
- CAN_TXID_T TXID;
- CAN_TXDATA_T TXDATA[2];
-
- CAN_RXFINFO_T RXFINFO;
- CAN_RXID_T RXID;
- CAN_RXDATA_T RX_DATA[2];
- CAN_ACR_T ACR;
- CAN_AMR_T AMR;
-} CAN_T;
-
-
-/*--------------------------- USB Device Controller --------------------------*/
-typedef struct
-{
- __IO uint32_t BUS:1;
- __IO uint32_t USB:1;
- __IO uint32_t FLD:1;
- __IO uint32_t WAKEUP:1;
- __I uint32_t RESERVE0:4;
- __IO uint32_t WAKEUP_EN:1;
- __I uint32_t RESERVE1:6;
- __IO uint32_t INNAK_EN:1;
- __I uint32_t RESERVE2:16;
-} USBD_IEF_T;
-
-typedef struct
-{
- __IO uint32_t BUS:1;
- __IO uint32_t USB:1;
- __IO uint32_t FLD:1;
- __IO uint32_t WAKEUP:1;
- __I uint32_t RESERVE0:12;
- __IO uint32_t EPTF:6;
- __I uint32_t RESERVE1:9;
- __IO uint32_t SETUP:1;
-} USBD_EVF_T;
-
-typedef struct
-{
- __IO uint32_t FADDR:7;
- __I uint32_t RESERVE:25;
-} USBD_FADDR_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:7;
- __IO uint32_t OVERRUN:1;
- __IO uint32_t STS0:3;
- __IO uint32_t STS1:3;
- __IO uint32_t STS2:3;
- __IO uint32_t STS3:3;
- __IO uint32_t STS4:3;
- __IO uint32_t STS5:3;
- __I uint32_t RESERVE1:6;
-} USBD_STS_T;
-
-
-
-typedef struct
-{
- __IO uint32_t USBRST:1;
- __IO uint32_t SUSPEND:1;
- __IO uint32_t RESUME:1;
- __IO uint32_t TIMEOUT:1;
- __IO uint32_t PHY_EN:1;
- __IO uint32_t RWAKEUP:1;
- __I uint32_t RESERVE0:1;
- __IO uint32_t USB_EN:1;
- __IO uint32_t DPPU_EN:1;
- __IO uint32_t PDB:1;
- __I uint32_t RESERVE1:22;
-} USBD_ATTR_T;
-
-
-
-typedef struct
-{
- __IO uint32_t FLODET:1;
- __I uint32_t RESERVE:31;
-} USBD_FLODET_T;
-
-typedef struct
-{
- __I uint32_t RESERVE0:3;
- __IO uint32_t BUFSEG:6;
- __I uint32_t RESERVE:23;
-} USBD_BUFSEG_T;
-
-typedef struct
-{
- __IO uint32_t MXPLD:9;
- __I uint32_t RESERVE:23;
-} USBD_MXPLD_T;
-
-typedef struct
-{
- __IO uint32_t EPT:4;
- __IO uint32_t ISOCH:1;
- __IO uint32_t STATE:2;
- __IO uint32_t DSQ:1;
- __I uint32_t RESERVE0:1;
- __IO uint32_t STALL_CTL:1;
- __I uint32_t RESERVE1:22;
-} USBD_CFG_T;
-
-typedef struct
-{
- __IO uint32_t CFGP:1;
- __IO uint32_t STALL:1;
- __I uint32_t RESERVE:30;
-} USBD_CFGP_T;
-
-typedef struct
-{
- __IO uint32_t DRVSE0:1;
- __I uint32_t RESERVE:31;
-} USBD_DRVSE0_T;
-
-typedef struct
-{
- __IO uint32_t BISTEN:1;
- __IO uint32_t FINISH:1;
- __IO uint32_t BISTFAIL:1;
- __I uint32_t RESERVE:29;
-} USBD_BIST_T;
-
-typedef struct
-{
- __IO uint32_t PDMA_RW:1;
- __IO uint32_t PDMA_EN:1;
- __I uint32_t RESERVE:30;
-} USBD_PDMA_T;
-
-
-typedef struct
-{
- USBD_BUFSEG_T BUFSEG;
- USBD_MXPLD_T MXPLD;
- USBD_CFG_T CFG;
- USBD_CFGP_T CFGP;
-} USBD_EP_T;
-
-typedef struct
-{
- USBD_IEF_T IEF;
- USBD_EVF_T EVF;
- USBD_FADDR_T FADDR;
- USBD_STS_T STS;
- USBD_ATTR_T ATTR;
- USBD_FLODET_T FLODET;
- USBD_BUFSEG_T BUFSEG;
- uint32_t RESERVE0;
- USBD_EP_T EP[6];
- uint32_t RESERVE1[4];
- USBD_DRVSE0_T DRVSE0;
- uint32_t RESERVE2[3];
- USBD_BIST_T BIST;
- USBD_PDMA_T PDMA;
-} USBD_T;
-
-
-/*------------------------------ PDMA Controller -----------------------------*/
-typedef struct
-{
- __IO uint32_t PDMACEN:1;
- __IO uint32_t SW_RST:1;
- __IO uint32_t MODE_SEL:2;
- __IO uint32_t SAD_SEL:2;
- __IO uint32_t DAD_SEL:2;
- __I uint32_t RESERVE0:4;
- __IO uint32_t WAR_BCR_SEL:4;
- __I uint32_t RESERVE1:3;
- __IO uint32_t APB_TWS:2;
- __I uint32_t RESERVE2:2;
- __IO uint32_t TRIG_EN:1;
- __I uint32_t RESERVE3:8;
-} PDMA_CSR_T;
-
-typedef __IO uint32_t PDMA_SAR_T;
-typedef __IO uint32_t PDMA_DAR_T;
-
-typedef __IO uint32_t PDMA_BCR_T;
-
-typedef __IO uint32_t PDMA_CSAR_T;
-typedef __IO uint32_t PDMA_CDAR_T;
-
-typedef struct
-{
- __IO uint32_t CBCR:24;
- __I uint32_t RESERVE:8;
-} PDMA_CBCR_T;
-
-typedef struct
-{
- __IO uint32_t TABORT_IE:1;
- __IO uint32_t BLKD_IE:1;
- __IO uint32_t WAR_IE:1;
- __I uint32_t RESERVE:29;
-} PDMA_IER_T;
-
-//typedef __IO uint32_t PDMA_ISR_T;
-
-typedef struct
-{
- __IO uint32_t TABORT_IF:1;
- __IO uint32_t BLKD_IF:1;
- __I uint32_t RESERVE:6;
- __IO uint32_t WAR_IF:4;
- __I uint32_t RESERVE1:3;
- __IO uint32_t BUSY:1;
- __I uint32_t RESERVE2:15;
- __IO uint32_t INTR:1;
-} PDMA_ISR_T;
-
-typedef __IO uint32_t PDMA_SBUF_T;
-
-typedef struct
-{
- __IO uint32_t PDMA_RST:1;
- __I uint32_t RESERVE0:7;
- __IO uint32_t HCLK0_EN:1;
- __IO uint32_t HCLK1_EN:1;
- __IO uint32_t HCLK2_EN:1;
- __IO uint32_t HCLK3_EN:1;
- __IO uint32_t HCLK4_EN:1;
- __IO uint32_t HCLK5_EN:1;
- __IO uint32_t HCLK6_EN:1;
- __IO uint32_t HCLK7_EN:1;
- __IO uint32_t HCLK8_EN:1;
- __IO uint32_t HCLK9_EN:1;
- __IO uint32_t HCLK10_EN:1;
- __IO uint32_t HCLK11_EN:1;
- __I uint32_t RESERVE1:12;
-} PDMA_GCRCSR_T;
-
-typedef struct
-{
- __IO uint32_t UART0_RXSEL:4;
- __IO uint32_t UART0_TXSEL:4;
- __IO uint32_t UART1_RXSEL:4;
- __IO uint32_t UART1_TXSEL:4;
- __IO uint32_t USBD_RXSEL:4;
- __IO uint32_t USBD_TXSEL:4;
- __IO uint32_t ADC_RXSEL:4;
- __IO uint32_t ADC_TXSEL:4;
-} PDMA_PDSSR1_T;
-
-
-typedef struct
-{
- __IO uint32_t SPI0_RXSEL:4;
- __IO uint32_t SPI0_TXSEL:4;
- __IO uint32_t SPI1_RXSEL:4;
- __IO uint32_t SPI1_TXSEL:4;
- __IO uint32_t SPI2_RXSEL:4;
- __IO uint32_t SPI2_TXSEL:4;
- __IO uint32_t SPI3_RXSEL:4;
- __IO uint32_t SPI3_TXSEL:4;
-} PDMA_PDSSR0_T;
-
-typedef __IO uint32_t PDMA_GCRISR_T;
-
-typedef struct
-{
- PDMA_GCRCSR_T GCRCSR;
- PDMA_PDSSR0_T PDSSR0;
- PDMA_PDSSR1_T PDSSR1;
- PDMA_GCRISR_T GCRISR;
-} PDMA_GCR_T;
-
-typedef struct
-{
- PDMA_CSR_T CSR;
- PDMA_SAR_T SAR;
- PDMA_DAR_T DAR;
- PDMA_BCR_T BCR;
- uint32_t POINT;
- PDMA_CSAR_T CSAR;
- PDMA_CDAR_T CDAR;
- PDMA_CBCR_T CBCR;
- PDMA_IER_T IER;
- PDMA_ISR_T ISR;
- PDMA_SBUF_T SBUF[4];
-} PDMA_T;
-
-/*----------------------------- PWM Controller -------------------------------*/
-typedef struct
-{
- __IO uint32_t CP0:8;
- __IO uint32_t CP1:8;
- __IO uint32_t DZI0:8;
- __IO uint32_t DZI1:8;
-} PWM_PPR_T;
-
-typedef struct
-{
- __IO uint32_t CSR0:3;
- __I uint32_t RESERVE0:1;
- __IO uint32_t CSR1:3;
- __I uint32_t RESERVE1:1;
- __IO uint32_t CSR2:3;
- __I uint32_t RESERVE2:1;
- __IO uint32_t CSR3:3;
- __I uint32_t RESERVE:17;
-} PWM_CSR_T;
-
-typedef struct
-{
- __IO uint32_t CH0EN:1;
- __I uint32_t RESERVE0:1;
- __IO uint32_t CH0INV:1;
- __IO uint32_t CH0MOD:1;
- __IO uint32_t DZEN0:1;
- __IO uint32_t DZEN1:1;
- __I uint32_t RESERVE1:2;
- __IO uint32_t CH1EN:1;
- __I uint32_t RESERVE2:1;
- __IO uint32_t CH1INV:1;
- __IO uint32_t CH1MOD:1;
- __I uint32_t RESERVE3:4;
- __IO uint32_t CH2EN:1;
- __I uint32_t RESERVE4:1;
- __IO uint32_t CH2INV:1;
- __IO uint32_t CH2MOD:1;
- __I uint32_t RESERVE5:4;
- __IO uint32_t CH3EN:1;
- __I uint32_t RESERVE6:1;
- __IO uint32_t CH3INV:1;
- __IO uint32_t CH3MOD:1;
- __I uint32_t RESERVE7:4;
-} PWM_PCR_T;
-
-typedef __IO uint32_t PWM_CNR_T;
-
-typedef __IO uint32_t PWM_CMR_T;
-
-typedef __IO uint32_t PWM_PDR_T;
-
-typedef struct
-{
- __IO uint32_t PWMIE0:1;
- __IO uint32_t PWMIE1:1;
- __IO uint32_t PWMIE2:1;
- __IO uint32_t PWMIE3:1;
- __I uint32_t RESERVE:28;
-} PWM_PIER_T;
-
-
-typedef struct
-{
- __IO uint32_t PWMIF0:1;
- __IO uint32_t PWMIF1:1;
- __IO uint32_t PWMIF2:1;
- __IO uint32_t PWMIF3:1;
- __I uint32_t RESERVE:28;
-} PWM_PIIR_T;
-
-
-typedef struct
-{
- __IO uint32_t INV0:1;
- __IO uint32_t CRL_IE0:1;
- __IO uint32_t CFL_IE0:1;
- __IO uint32_t CAPCH0EN:1;
- __IO uint32_t CAPIF0:1;
- __I uint32_t RESERVE0:1;
- __IO uint32_t CRLRI0:1;
- __IO uint32_t CFLRI0:1;
- __I uint32_t RESERVE1:8;
- __IO uint32_t INV1:1;
- __IO uint32_t CRL_IE1:1;
- __IO uint32_t CFL_IE1:1;
- __IO uint32_t CAPCH1EN:1;
- __IO uint32_t CAPIF1:1;
- __I uint32_t RESERVE2:1;
- __IO uint32_t CRLRI1:1;
- __IO uint32_t CFLRI1:1;
- __I uint32_t RESERVE3:8;
-} PWM_CCR0_T;
-
-
-typedef struct
-{
- __IO uint32_t INV2:1;
- __IO uint32_t CRL_IE2:1;
- __IO uint32_t CFL_IE2:1;
- __IO uint32_t CAPCH2EN:1;
- __IO uint32_t CAPIF2:1;
- __I uint32_t RESERVE0:1;
- __IO uint32_t CRLRI2:1;
- __IO uint32_t CFLRI2:1;
- __I uint32_t RESERVE1:8;
- __IO uint32_t INV3:1;
- __IO uint32_t CRL_IE3:1;
- __IO uint32_t CFL_IE3:1;
- __IO uint32_t CAPCH3EN:1;
- __IO uint32_t CAPIF3:1;
- __I uint32_t RESERVE2:1;
- __IO uint32_t CRLRI3:1;
- __IO uint32_t CFLRI3:1;
- __I uint32_t RESERVE3:8;
-} PWM_CCR1_T;
-
-
-typedef __IO uint32_t PWM_CRLR_T;
-
-typedef __IO uint32_t PWM_CFLR_T;
-
-typedef __IO uint32_t PWM_CAPENR_T;
-
-typedef struct
-{
- __IO uint32_t PWM0:1;
- __IO uint32_t PWM1:1;
- __IO uint32_t PWM2:1;
- __IO uint32_t PWM3:1;
- __I uint32_t RESERVE:28;
-} PWM_POE_T;
-
-
-typedef struct
-{
- PWM_PPR_T PPR;
- PWM_CSR_T CSR;
- PWM_PCR_T PCR;
- PWM_CNR_T CNR0;
- PWM_CMR_T CMR0;
- PWM_PDR_T PDR0;
- PWM_CNR_T CNR1;
- PWM_CMR_T CMR1;
- PWM_PDR_T PDR1;
- PWM_CNR_T CNR2;
- PWM_CMR_T CMR2;
- PWM_PDR_T PDR2;
- PWM_CNR_T CNR3;
- PWM_CMR_T CMR3;
- PWM_PDR_T PDR3;
- __I uint32_t RESERVE0;
- PWM_PIER_T PIER;
- PWM_PIIR_T PIIR;
- __I uint32_t RESERVE1[2];
- PWM_CCR0_T CCR0;
- PWM_CCR1_T CCR1;
- PWM_CRLR_T CRLR0;
- PWM_CFLR_T CFLR0;
- PWM_CRLR_T CRLR1;
- PWM_CFLR_T CFLR1;
- PWM_CRLR_T CRLR2;
- PWM_CFLR_T CFLR2;
- PWM_CRLR_T CRLR3;
- PWM_CFLR_T CFLR3;
- PWM_CAPENR_T CAPENR;
- PWM_POE_T POE;
-
-
-} PWM_T;
-
-
-
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Peripheral and SRAM base address */
-#define FLASH_BASE (( uint32_t)0x00000000)
-#define SRAM_BASE (( uint32_t)0x20000000)
-#define AHB_BASE (( uint32_t)0x50000000)
-#define APB1_BASE (( uint32_t)0x40000000)
-#define APB2_BASE (( uint32_t)0x40100000)
-
-/* Peripheral memory map */
-#define GPIO_BASE (AHB_BASE + 0x4000)
-
-#define GPIOA_BASE (GPIO_BASE )
-#define GPIOB_BASE (GPIO_BASE + 0x0040)
-#define GPIOC_BASE (GPIO_BASE + 0x0080)
-#define GPIOD_BASE (GPIO_BASE + 0x00C0)
-#define GPIOE_BASE (GPIO_BASE + 0x0100)
-#define GPIO_DBNCECON_BASE (GPIO_BASE + 0x0180)
-
-#define UART0_BASE (APB1_BASE + 0x50000)
-#define UART1_BASE (APB2_BASE + 0x50000)
-
-#define TIMER0_BASE (APB1_BASE + 0x10000)
-#define TIMER1_BASE (APB1_BASE + 0x10020)
-#define TIMER2_BASE (APB2_BASE + 0x10000)
-#define TIMER3_BASE (APB2_BASE + 0x10020)
-
-#define WDT_BASE (APB1_BASE + 0x4000)
-
-#define SPI0_BASE (APB1_BASE + 0x30000)
-#define SPI1_BASE (APB1_BASE + 0x34000)
-#define SPI2_BASE (APB2_BASE + 0x30000)
-#define SPI3_BASE (APB2_BASE + 0x34000)
-
-#define I2C0_BASE (APB1_BASE + 0x20000)
-#define I2C1_BASE (APB2_BASE + 0x20000)
-
-#define RTC_BASE (APB1_BASE + 0x08000)
-
-#define ADC_BASE (APB1_BASE + 0xE0000)
-#define ADC_ADSR (ADC_BASE + 0x30)
-
-#define ACMP_BASE (APB1_BASE + 0xD0000)
-
-#define SYSCLK_BASE (AHB_BASE + 0x00200)
-
-#define GCR_BASE (AHB_BASE + 0x00000)
-
-#define INT_BASE (AHB_BASE + 0x00300)
-
-#define FMC_BASE (AHB_BASE + 0x0C000)
-
-#define PS2_BASE (APB2_BASE + 0x00000)
-
-#define CAN0_BASE (APB2_BASE + 0x80000)
-#define CAN1_BASE (APB2_BASE + 0x84000)
-
-#define USBD_BASE (APB1_BASE + 0x60000)
-
-#define PDMA0_BASE (AHB_BASE + 0x08000)
-#define PDMA1_BASE (AHB_BASE + 0x08100)
-#define PDMA2_BASE (AHB_BASE + 0x08200)
-#define PDMA3_BASE (AHB_BASE + 0x08300)
-#define PDMA4_BASE (AHB_BASE + 0x08400)
-#define PDMA5_BASE (AHB_BASE + 0x08500)
-#define PDMA6_BASE (AHB_BASE + 0x08600)
-#define PDMA7_BASE (AHB_BASE + 0x08700)
-#define PDMA8_BASE (AHB_BASE + 0x08800)
-#define PDMA9_BASE (AHB_BASE + 0x08900)
-#define PDMA10_BASE (AHB_BASE + 0x08A00)
-#define PDMA11_BASE (AHB_BASE + 0x08B00)
-#define PDMA_GCR_BASE (AHB_BASE + 0x08F00)
-
-#define PWM_BASE (APB1_BASE + 0x40000)
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define GPIOA ((GPIO_T *) GPIOA_BASE)
-#define GPIOB ((GPIO_T *) GPIOB_BASE)
-#define GPIOC ((GPIO_T *) GPIOC_BASE)
-#define GPIOD ((GPIO_T *) GPIOD_BASE)
-#define GPIOE ((GPIO_T *) GPIOE_BASE)
-#define GPIO_DBNCECON ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
-
-#define UART0 ((UART_T *) UART0_BASE)
-#define UART1 ((UART_T *) UART1_BASE)
-
-#define TIMER0 ((TIMER_T *) TIMER0_BASE)
-#define TIMER1 ((TIMER_T *) TIMER1_BASE)
-#define TIMER2 ((TIMER_T *) TIMER2_BASE)
-#define TIMER3 ((TIMER_T *) TIMER3_BASE)
-
-#define WDT ((WDT_T *) WDT_BASE)
-
-#define SPI0 ((SPI_T *) SPI0_BASE)
-#define SPI1 ((SPI_T *) SPI1_BASE)
-#define SPI2 ((SPI_T *) SPI2_BASE)
-#define SPI3 ((SPI_T *) SPI3_BASE)
-
-#define I2C0 ((I2C_T *) I2C0_BASE)
-#define I2C1 ((I2C_T *) I2C1_BASE)
-
-#define RTC ((RTC_T *) RTC_BASE)
-
-#define ADC ((ADC_T *) ADC_BASE)
-
-#define ACMP ((ACMP_T *) ACMP_BASE)
-
-#define SYSCLK ((SYSCLK_T *) SYSCLK_BASE)
-
-#define SYS ((GCR_T *) GCR_BASE)
-
-#define SYSINT ((GCR_INT_T *) INT_BASE)
-
-#define FMC ((FMC_T *) FMC_BASE)
-
-#define PS2 ((PS2_T *) PS2_BASE)
-
-#define CAN0 ((CAN_T *) CAN0_BASE)
-#define CAN1 ((CAN_T *) CAN1_BASE)
-
-#define USBD ((USBD_T *) USBD_BASE)
-
-#define PDMA0 ((PDMA_T *) PDMA0_BASE)
-#define PDMA1 ((PDMA_T *) PDMA1_BASE)
-#define PDMA2 ((PDMA_T *) PDMA2_BASE)
-#define PDMA3 ((PDMA_T *) PDMA3_BASE)
-#define PDMA4 ((PDMA_T *) PDMA4_BASE)
-#define PDMA5 ((PDMA_T *) PDMA5_BASE)
-#define PDMA6 ((PDMA_T *) PDMA6_BASE)
-#define PDMA7 ((PDMA_T *) PDMA7_BASE)
-#define PDMA8 ((PDMA_T *) PDMA8_BASE)
-#define PDMA9 ((PDMA_T *) PDMA9_BASE)
-#define PDMA10 ((PDMA_T *) PDMA10_BASE)
-#define PDMA11 ((PDMA_T *) PDMA11_BASE)
-#define PDMA_GCR ((PDMA_GCR_T *) PDMA_GCR_BASE)
-
-#define PWM ((PWM_T *) PWM_BASE)
-
-#define UNLOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88
-#define LOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00;
-
-#define REGCOPY(dest, src) *((uint32_t *)&(dest)) = *((uint32_t *)&(src))
-#define CLEAR(dest) *((uint32_t *)&(dest)) = 0
-
-//=============================================================================
-typedef volatile unsigned char vu8;
-typedef volatile unsigned long vu32;
-typedef volatile unsigned short vu16;
-#define M8(adr) (*((vu8 *) (adr)))
-#define M16(adr) (*((vu16 *) (adr)))
-#define M32(adr) (*((vu32 *) (adr)))
-
-#define outpw(port,value) *((volatile unsigned int *)(port))=value
-#define inpw(port) (*((volatile unsigned int *)(port)))
-#define outpb(port,value) *((volatile unsigned char *)(port))=value
-#define inpb(port) (*((volatile unsigned char *)(port)))
-#define outps(port,value) *((volatile unsigned short *)(port))=value
-#define inps(port) (*((volatile unsigned short *)(port)))
-
-#define E_SUCCESS 0
-#define NULL 0
-
-#define TRUE 1
-#define FALSE 0
-
-#define ENABLE 1
-#define DISABLE 0
-
-// Define one bit mask
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-#endif
-
diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.c b/bsp/nuc140/CMSIS/CM0/core_cm0.c
deleted file mode 100644
index cbac38562a..0000000000
--- a/bsp/nuc140/CMSIS/CM0/core_cm0.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/******************************************************************************
- * @file: core_cm0.c
- * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version: V1.10
- * @date: 24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-#include <stdint.h>
-
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for armcc */
- #define __INLINE __inline /*!< inline keyword for armcc */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for iarcc */
- #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
- #define __nop __no_operation /*!< no operation intrinsic in iarcc */
-
-#elif defined ( __GNUC__ )
- #define __ASM asm /*!< asm keyword for gcc */
- #define __INLINE inline /*!< inline keyword for gcc */
-#endif
-
-
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-
-#pragma diag_default=Pe940
-
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
-}
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int32_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.h b/bsp/nuc140/CMSIS/CM0/core_cm0.h
deleted file mode 100644
index f4aee39cd9..0000000000
--- a/bsp/nuc140/CMSIS/CM0/core_cm0.h
+++ /dev/null
@@ -1,801 +0,0 @@
-/******************************************************************************
- * @file: core_cm0.h
- * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version: V1.10
- * @date: 24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-
-#ifndef __CM0_CORE_H__
-#define __CM0_CORE_H__
-
-
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex core */
-
-
-
-#include <stdint.h> /* Include standard types */
-
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#define __I volatile const /*!< defines 'read only' permissions */
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-
-
-/* System Reset */
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
-
-
-
-
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Interrupt Priority Register */
-} NVIC_Type;
-
-
-/* memory mapping struct for System Control Block */
-typedef struct
-{
- __I uint32_t CPUID; /*!< CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< System Control Register */
- __IO uint32_t CCR; /*!< Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
- uint32_t RESERVED2[2];
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */
-} SCB_Type;
-
-
-/* memory mapping struct for SysTick */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< SysTick Current Value Register */
- __I uint32_t CALIB; /*!< SysTick Calibration Register */
-} SysTick_Type;
-
-
-
-/* Core Debug Register */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
- #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-
-#elif defined ( __GNUC__ )
- #define __ASM asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-
-
- /* intrinsic void __enable_irq(); */
- /* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-
-//static __INLINE void __ISB(arg) { __ASM ("isb"); }
-//static __INLINE void __DSB(arg) { __ASM ("dsb"); }
-//static __INLINE void __DMB(arg) { __ASM ("dmb"); }
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-
-
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB(arg) { __ASM volatile ("isb"); }
-static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); }
-static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * @brief Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#endif
-
-
-
-/* ########################## NVIC functions #################################### */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param uint32_t priority_grouping is priority grouping field
- * @return
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
-{
- uint32_t reg_value=0;
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn_Type IRQn specifies the interrupt number
- * @return none
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn_Type IRQn is the positive number of the external interrupt
- * @return none
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn_Type IRQn is the number of the device specifc interrupt
- * @return IRQn_Type Number of pending interrupt or zero
- *
- * Read the pending register in NVIC and return the number of the
- * specified interrupt if its status is pending, otherwise it returns
- * zero. The interrupt number cannot be a negative value.
- */
-static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @param priority is the priority for the interrupt
- * @return none
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt. \n
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return priority is the priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/* SysTick constants */
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param uint32_t ticks is the number of ticks between two interrupts
- * @return none
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * @param none
- * @return none
- *
- * Initialize a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
-}
-
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s b/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s
deleted file mode 100644
index d420492899..0000000000
--- a/bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s
+++ /dev/null
@@ -1,381 +0,0 @@
-;/*---------------------------------------------------------------------------------------------------------*/
-;/* */
-;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
-;/* */
-;/*---------------------------------------------------------------------------------------------------------*/
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-CLK_BA_base EQU 0x50000200
-PWRCON EQU 0x00
-AHBCLK EQU 0x04
-APBCLK EQU 0x08
-CLKSEL0 EQU 0x10
-CLKSEL1 EQU 0x14
-CLKDIV EQU 0x18
-PLLCON EQU 0x20
-TEST_S EQU 0x30
-
-CLK_BA_APBCLK EQU 0x50000208
-
-;// Define clock enable registers
-
-ADC_COMP_CLK EQU 0x50000208
-ADC_enable EQU 0x10000000
-COMP_enable EQU 0x40000000
-
-PDMA_CLK EQU 0x50000204
-PDMA_enable EQU 0x00000003
-
-;; bit 0 CPU_EN
-;; bit 1 PDMA_EN
-
-
-
-
-;// Define COMP registers base
-COMP_base EQU 0x400D0000
-CMP1CR EQU 0x00
-CMP2CR EQU 0x04
-CMPSR EQU 0x08
-
-;// Define ADC registers base
-ADC_base EQU 0x400E0000
-ADDR0 EQU 0x00
-ADDR1 EQU 0x04
-ADDR2 EQU 0x08
-ADDR3 EQU 0x0c
-ADDR4 EQU 0x10
-ADDR5 EQU 0x14
-ADDR6 EQU 0x18
-ADDR7 EQU 0x1c
-ADCR EQU 0x20
-ADCHER EQU 0x24
-ADCMPR0 EQU 0x28
-ADCMPR1 EQU 0x2c
-ADSR EQU 0x30
-ADCALR EQU 0x34
-ADCFCR EQU 0x38
-ADCALD EQU 0x3c
-
-;// Pattern Table
-pattern_55555555 EQU 0x55555555
-pattern_aaaaaaaa EQU 0xaaaaaaaa
-pattern_00005555 EQU 0x00005555
-pattern_0000aaaa EQU 0x0000aaaa
-pattern_05550515 EQU 0x05550515
-pattern_0aaa0a2a EQU 0x0aaa0a2a
-
-;// Define PDMA regsiter base
-PDMA_BA_ch0_base EQU 0x50008000
-PDMA_BA_ch1_base EQU 0x50008100
-PDMA_BA_ch2_base EQU 0x50008200
-PDMA_BA_ch3_base EQU 0x50008300
-PDMA_BA_ch4_base EQU 0x50008400
-PDMA_BA_ch5_base EQU 0x50008500
-PDMA_BA_ch6_base EQU 0x50008600
-PDMA_BA_ch7_base EQU 0x50008700
-
-PDMA_BA_GCR EQU 0x50008F00
-PDMA_BA_GCR_base EQU 0x50008F00
-
-PDMA_GCRCSR EQU 0X00
-PDMA_PDSSR2 EQU 0X04
-PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000
-PDMA_GCRISR EQU 0X0C
-
-PDMA_GLOBAL_enable EQU 0x0000FF00
-
-
-PDMA_CSR EQU 0X00
-PDMA_SAR EQU 0X04
-PDMA_DAR EQU 0X08
-PDMA_BCR EQU 0X0C
-PDMA_CSAR EQU 0X14
-PDMA_CDAR EQU 0X18
-PDMA_CBSR EQU 0X1C
-PDMA_IER EQU 0X20
-PDMA_ISR EQU 0X24
-PDMA_CTCSR EQU 0X28
-PDMA_SASOCR EQU 0X2C
-PDMA_DASOCR EQU 0X30
-PDMA_SBUF0 EQU 0X80
-PDMA_SBUF1 EQU 0X84
-PDMA_SBUF2 EQU 0X88
-PDMA_SBUF3 EQU 0X8C
-
-
-;// Define VIC control register
-VIC_base EQU 0xFFFF0000
-VIC_SCR15 EQU 0x003c
-VIC_SVR15 EQU 0x00bc
-VIC_SCR16 EQU 0x0040
-VIC_SVR16 EQU 0x00c0
-VIC_SCR30 EQU 0x0078
-VIC_SVR30 EQU 0x00f8
-VIC_MECR EQU 0x0318
-VIC_MDCR EQU 0x031c
-VIC_EOSCR EQU 0x0130
-
-;//==================================
-INT_BA_base EQU 0x50000300
-
-
-;// Parameter table
-ADC_PDMA_CFG EQU 0x00002980
-ADC_PDMA_DST EQU 0xC0000000
-ADC_PDMA_SRC EQU 0xE0024200
-ADC_PDMA_TCBL EQU 0x00030008
-
-;//==================================
-
-
-GPIO_base EQU 0x50004000
-GPIOB_PMD EQU 0x0040
-GPIOB_OFFD EQU 0x0044
-GPIOB_DOUT EQU 0x0048
-GPIOB_DMASK EQU 0x004C
-GPIOB_PIN EQU 0x0050
-GPIOB_DBEN EQU 0x0054
-GPIOB_IMD EQU 0x0058
-GPIOB_IEN EQU 0x005C
-GPIOB_ISRC EQU 0x0060
-
-;//==================================
-
-
-GCR_base EQU 0x50000000
-GPB_MFP EQU 0x0034
-
-
-
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
-
-
-
-
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- ; maximum of 32 External Interrupts are possible
- DCD BOD_IRQHandler
- DCD WDT_IRQHandler
- DCD EINT0_IRQHandler
- DCD EINT1_IRQHandler
- DCD GPAB_IRQHandler
- DCD GPCDE_IRQHandler
- DCD PWMA_IRQHandler
- DCD PWMB_IRQHandler
- DCD TMR0_IRQHandler
- DCD TMR1_IRQHandler
- DCD TMR2_IRQHandler
- DCD TMR3_IRQHandler
- DCD UART0_IRQHandler
- DCD UART1_IRQHandler
- DCD SPI0_IRQHandler
- DCD SPI1_IRQHandler
- DCD SPI2_IRQHandler
- DCD SPI3_IRQHandler
- DCD I2C0_IRQHandler
- DCD I2C1_IRQHandler
- DCD CAN0_IRQHandler
- DCD CAN1_IRQHandler
- DCD Default_Handler
- DCD USBD_IRQHandler
- DCD PS2_IRQHandler
- DCD ACMP_IRQHandler
- DCD PDMA_IRQHandler
- DCD Default_Handler
- DCD PWRWU_IRQHandler
- DCD ADC_IRQHandler
- DCD Default_Handler
- DCD RTC_IRQHandler
-
-
-
-
-
-
-
- AREA |.text|, CODE, READONLY
-
-
-
-; Reset Handler
-
- ENTRY
-
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
-
- LDR R0, =__main
- BX R0
- ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT BOD_IRQHandler [WEAK]
- EXPORT WDT_IRQHandler [WEAK]
- EXPORT EINT0_IRQHandler [WEAK]
- EXPORT EINT1_IRQHandler [WEAK]
- EXPORT GPAB_IRQHandler [WEAK]
- EXPORT GPCDE_IRQHandler [WEAK]
- EXPORT PWMA_IRQHandler [WEAK]
- EXPORT PWMB_IRQHandler [WEAK]
- EXPORT TMR0_IRQHandler [WEAK]
- EXPORT TMR1_IRQHandler [WEAK]
- EXPORT TMR2_IRQHandler [WEAK]
- EXPORT TMR3_IRQHandler [WEAK]
- EXPORT UART0_IRQHandler [WEAK]
- EXPORT UART1_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT I2C0_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT CAN0_IRQHandler [WEAK]
- EXPORT CAN1_IRQHandler [WEAK]
- EXPORT USBD_IRQHandler [WEAK]
- EXPORT PS2_IRQHandler [WEAK]
- EXPORT ACMP_IRQHandler [WEAK]
- EXPORT PDMA_IRQHandler [WEAK]
- EXPORT PWRWU_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
-
-BOD_IRQHandler
-WDT_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-GPAB_IRQHandler
-GPCDE_IRQHandler
-PWMA_IRQHandler
-PWMB_IRQHandler
-TMR0_IRQHandler
-TMR1_IRQHandler
-TMR2_IRQHandler
-TMR3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-SPI3_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-CAN0_IRQHandler
-CAN1_IRQHandler
-USBD_IRQHandler
-PS2_IRQHandler
-ACMP_IRQHandler
-PDMA_IRQHandler
-PWRWU_IRQHandler
-ADC_IRQHandler
-RTC_IRQHandler
- B .
- ENDP
-
-
- ALIGN
-
-
-; User Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, = (Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
-
- END
diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c
deleted file mode 100644
index c4e73afd63..0000000000
--- a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*---------------------------------------------------------------------------------------------------------*/
-/* */
-/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
-/* */
-/*---------------------------------------------------------------------------------------------------------*/
-#include <stdint.h>
-#include "NUC1xx.h"
-
-/*----------------------------------------------------------------------------
- Define SYSCLK
- *----------------------------------------------------------------------------*/
-#define __HSI (50000000UL)
-
-/*----------------------------------------------------------------------------
- Clock Definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemFrequency = __HSI; /*!< System Clock Frequency (Core Clock) */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Function: SystemInit */
-/* */
-/* Parameters: */
-/* None */
-/* */
-/* Returns: */
-/* None */
-/* */
-/* Description: */
-/* The necessary initializaiton of systerm. */
-/* */
-/*---------------------------------------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-}
-
diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h
deleted file mode 100644
index f29860fabc..0000000000
--- a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/******************************************************************************
- * @file: system_armikmcu.h
- * @purpose: CMSIS ARM Cortex-M0 Device Peripheral Access Layer Header File
- * @version: V0.01
- * @date: 17. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_ARMCM0_H
-#define __SYSTEM_ARMCM0_H
-
-extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system
- * Initialise GPIO directions and values
- */
-extern void SystemInit (void);
-#endif
diff --git a/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm b/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm
deleted file mode 100644
index 4743909ce4..0000000000
--- a/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm
+++ /dev/null
@@ -1,1204 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head>
-
- <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
- <meta name="ProgId" content="FrontPage.Editor.Document">
- <style>
-<!--
-/*-----------------------------------------------------------Keil Software CHM Style Sheet
------------------------------------------------------------*/
-body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: Verdana, Arial, 'Sans Serif' }
-a:link { color: #0000FF; text-decoration: underline }
-a:visited { color: #0000FF; text-decoration: underline }
-a:active { color: #FF0000; text-decoration: underline }
-a:hover { color: #FF0000; text-decoration: underline }
-h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; text-align: Center; margin-right: 3 }
-h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; margin-left: 24; margin-right: 24 }
-ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
-ol { margin-top: 6pt; margin-bottom: 0 }
-li { clear: both; margin-bottom: 6pt }
-table { font-size: 100%; border-width: 0; padding: 0 }
-th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: bottom; padding-right: 6pt }
-tr { text-align: left; vertical-align: top }
-td { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT { font-size: 8pt; color: #808080 }
-.TinyT { font-size: 8pt; text-align: Center }
-code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------Notes
------------------------------------------------------------*/
-p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand { text-decoration: none; margin-bottom: 3pt }
-img.expand { border-style: none; border-width: medium }
-div.expand { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------Where List Tags
------------------------------------------------------------*/
-p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh { width: 100% }
-td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 6pt }
-td.whDesc { padding-bottom: 6pt }
-/*-----------------------------------------------------------Keil Table Tags
------------------------------------------------------------*/
-table.kt { width: 100%; border: 1pt solid #000000 }
-th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
-tr.kt { }
-td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; padding-bottom: 2pt }
-/*----------------------------------------------------------------------------------------------------------------------*/
- .style1 {
- background-color: #E0E0E0;
-}
-.O
- {color:#1D315B;
- font-size:149%;}
- -->
- </style></head>
-<body>
-<h1>Cortex Microcontroller Software Interface Standard</h1>
-
-<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
-<p align="center">Version: 1.10 - 24. Feb. 2009</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
- Copyright � ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
- <li>Version 1.00: initial release. </li>
- <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
- <li>Version 1.02: added Cortex-M0. </li>
- <li>Version 1.10: second review. </li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
- <li class="LI2"><a href="#1">About</a></li>
- <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
- <li class="LI2"><a href="#3">CMSIS Files</a></li>
- <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
- <li class="LI2"><a href="#5">CMSIS Example</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
- The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
- that are faced when software components are deployed to physical microcontroller devices based on a
- Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
- processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation
- with various silicon and software vendors and provides a common approach to interface to peripherals,
- real-time operating systems, and middleware components.
-</p>
-
-<p>ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:</p>
-<ul>
- <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
- address definitions and helper functions to
- access core registers and peripherals. It defines also an device
- independent interface for RTOS Kernels that includes debug channel
- definitions.</li>
- <li><strong>Middleware Access Layer:</strong> provides common methods to
- access peripherals for the software industry. The Middleware Access Layer
- is adapted by the Silicon Vendor for the device specific peripherals used
- by middleware components. The middleware access layer is currently in
- development and not yet part of this documentation</li>
-</ul>
-
-<p>These software layers are expanded by Silicon partners with:</p>
-<ul>
- <li><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals</li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals</li>
-</ul>
-
-<p>CMSIS defines for a Cortex-Mx Microcontroller System:</p>
-<ul>
- <li style="text-align: left;">A common way to access peripheral registers
- and a common way to define exception vectors.</li>
- <li style="text-align: left;">The register names of the <strong>Core
- Peripherals</strong> and<strong> </strong>the names of the <strong>Core
- Exception Vectors</strong>.</li>
- <li>An device independent interface for RTOS Kernels including a debug
- channel.</li>
- <li style="text-align: left;">Interfaces for middleware components (TCP/IP
- Stack, Flash File System).</li>
-</ul>
-
-<p>
- By using CMSIS compliant software components, the user can easier re-use template code.
- CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-</p>
-
-<h2><a name="2"></a>Coding Rules and Conventions</h2>
-
-<p>
- The following section describes the coding rules and conventions used in the CMSIS
- implementation. It contains also information about data types and version number information.
-</p>
-
-<h3>Essentials</h3>
-<ul>
- <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
- there are disable and enable sequences for PC-LINT inserted.</li>
- <li>ANSI standard data types defined in the ANSI C header file
- <strong>&lt;stdint.h&gt;</strong> are used.</li>
- <li>#define constants that include expressions must be enclosed by
- parenthesis.</li>
- <li>Variables and parameters have a complete data type.</li>
- <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
- re-entrant.</li>
- <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
- (which means that wait/query loops are done at other software layers such as
- the <strong>Middleware Access Layer</strong>).</li>
- <li>For each exception/interrupt there is definition for:
- <ul>
- <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
- (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
- <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
- <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
- </ul></li>
-</ul>
-
-<h3>Recommendations</h3>
-
-<p>The CMSIS recommends the following conventions for identifiers.</p>
-<ul>
- <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
- <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
- <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
- <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
-</ul>
-
-<b>Comments</b>
-
-<ul>
- <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
- (<em>// comment</em>). It is assumed that the programming tools support today
- consistently the C++ comment style.</li>
- <li><strong>Function Comments</strong> provide for each function the following information:
- <ul>
- <li>one-line brief function overview.</li>
- <li>detailed parameter explanation.</li>
- <li>detailed information about return values.</li>
- <li>detailed description of the actual function.</li>
- </ul>
- <p><b>Doxygen Example:</b></p>
- <pre>
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- * @param IRQn interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */</pre>
- </li>
-</ul>
-
-<h3>Data Types and IO Type Qualifiers</h3>
-
-<p>
- The <strong>Cortex-Mx HAL</strong> uses the standard types from the standard ANSI C header file
- <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
- to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
- debug information of peripheral registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
- <th class="kt">#define</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__I</td>
- <td class="kt">volatile const</td>
- <td class="kt">Read access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__O</td>
- <td class="kt">volatile</td>
- <td class="kt">Write access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__IO</td>
- <td class="kt">volatile</td>
- <td class="kt">Read and write access</td>
- </tr>
- </tbody>
-</table>
-
-<h3>CMSIS Version Number</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM3_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
-#define __CM3_CMSIS_VERSION_SUB (0x03) /* [15:0] sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM0_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
-#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>
-
-
-<h3>CMSIS Cortex Core</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x03)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x00)</pre>
-
-
-<h2><a name="3"></a>CMSIS Files</h2>
-<p>
- This section describes the Files provided in context with the CMSIS to access the Cortex-Mx
- hardware and peripherals.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt">Provider</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap"><i>device.h</i></td>
- <td class="kt">Device specific (provided by silicon partner)</td>
- <td class="kt">Defines the peripherals for the actual device. The file may use
- several other include files to define the peripherals of the actual device.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm3.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
- <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
- <td class="kt">Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">system<i>_device</i></td>
- <td class="kt">ARM (adapted by silicon partner)</td>
- <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
- typically the oscillator (PLL) that is part of the microcontroller device</td>
- </tr>
- </tbody>
-</table>
-
-<h3><em>device.h</em></h3>
-
-<p>
- The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
- <u><strong>central include file</strong></u> that the application programmer is using in
- the C source code. This file contains:
-</p>
-<ul>
- <li>
- <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
- (IRQn) for all core and device specific exceptions and interrupts.</p>
- </li>
- <li>
- <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
- actual configuration of the Cortex-Mx processor that is part of the actual
- device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
- implements access to processor registers and core peripherals. </p>
- </li>
- <li>
- <p><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals. It contains all data structures and the address
- mapping for the device specific peripherals. </p>
- </li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals that are useful for programming
- of these peripherals. Access Functions may be provided as inline functions
- or can be extern references to a device specific library provided by the
- silicon vendor.</li>
-</ul>
-
-
-<h4><strong>Interrupt Number Definition</strong></h4>
-
-<p>To access the device specific interrupts the device.h file defines IRQn
-numbers for the complete device using a enum typedef as shown below:</p>
-<pre>
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
- NonMaskableInt_IRQn = -14, /*!&lt; 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!&lt; 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!&lt; 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!&lt; 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!&lt; 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!&lt; 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!&lt; 15 Cortex-M3 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers ****************************************************************/
- WWDG_STM_IRQn = 0, /*!&lt; Window WatchDog Interrupt */
- PVD_STM_IRQn = 1, /*!&lt; PVD through EXTI Line detection Interrupt */
- :
- :
- } IRQn_Type;</pre>
-
-
-<h4>Configuration for core_cm0.h / core_cm3.h</h4>
-<p>
- The Cortex-Mx core configuration options which are defined for each device implementation. Some
- configuration options are reflected in the CMSIS layer using the #define settings described below.
-</p>
-<p>
- To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
- Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
- defined before <strong>#include &lt;core_cm0.h&gt;</strong> / <strong>#include &lt;core_cm3.h&gt;</strong>
- preprocessor command.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">#define</th>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt" nowrap="nowrap">Value</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm0.h</td>
- <td class="kt" nowrap="nowrap">(2)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(2 ... 8)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(0, 1)</td>
- <td class="kt">Defines if an MPU is present or not</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(1)</td>
- <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
- in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
- file must contain a vendor specific implementation of this function.</td>
- </tr>
- </tbody>
-</table>
-
-
-<h4>Device Peripheral Access Layer</h4>
-<p>
- Each peripheral uses a <strong>PERIPHERAL_</strong> prefix to identify peripheral registers
- and functions that access this specific peripheral. If more than one peripheral of the same
- type exists, identifiers have a postfix (digit or letter). For example:
-</p>
-<ul>
- <li>UART_Type: defines the generic register layout for all UART channels in a device.</li>
- <li>UART1: is a pointer to a register structure that refers to a specific UART.
- For example UART1-&gt;DR is the data register of UART1.</li>
- <li>UART_SendChar(UART1, c): is a generic function that works with all UART's in the device.
- To communicate the UART that it accesses the first parameter is a pointer to the actual
- UART register structure.</li>
- <li>UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).</li>
-</ul>
-
-<h5>Minimal Requiements</h5>
-<p>
- To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
- and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
-</p>
-<ul>
- <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
- Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
- the peripheral registers. For example:
- <pre>
-typedef struct {
- __IO uint32_t CTRL; /* SysTick Control and Status Register */
- __IO uint32_t LOAD; /* SysTick Reload Value Register */
- __IO uint32_t VAL; /* SysTick Current Value Register */
- __I uint32_t CALIB; /* SysTick Calibration Register */
- } SysTick_Type;</pre>
- </li>
-
- <li><strong>Base Address</strong> for each peripheral (in case of multiple peripherals
- that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
- <pre>
-#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
- </li>
-
- <li><strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
- the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. UART0,
- UART1). For Example:
- <pre>
-#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
- </li>
-</ul>
-
-<p>
- These definitions allow to access the peripheral registers from user code with simple assignments like:
-</p>
-<pre>SysTick-&gt;CTRL = 0;</pre>
-
-<h5>Optional Features</h5>
-<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
-<ul>
- <li>#define constants that simplify access to the peripheral registers.
- These constant define bit-positions or other specific patterns are that
- required for the programming of the peripheral registers. The identifiers
- used start with the name of the <strong>PERIPERHAL_</strong>. It is
- recommended to use CAPITAL letters for such #define constants.</li>
- <li>Functions that perform more complex functions with the peripheral (i.e.
- status query before a sending register is accessed). Again these function
- start with the name of the <strong>PERIPHERAL_</strong>. </li>
-</ul>
-
-<h3>core_cm0.h and core_cm0.c</h3>
-<p>
- File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm0.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
-
-<h3>core_cm3.h and core_cm3.c</h3>
-<p>
- File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm3.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
-
-<h3>startup_<em>device</em></h3>
-<p>
- A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
- compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
- interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
- to an dummy handler. Therefore the interrupt handler can be directly used in application software
- without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
-</p>
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M3:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- In the following examples for device specific interrupts are shown:
-</p>
-<pre>
-; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper</pre>
-
-<p>
- Device specific interrupts must have a dummy function that can be overwritten in user code.
- Below is an example for this dummy function.
-</p>
-<pre>
-Default_Handler PROC
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- :
- :
- WWDG_IRQHandler
- PVD_IRQHandler
- TAMPER_IRQHandler
- :
- :
- B .
- ENDP</pre>
-
-<p>
- The user application may simply define an interrupt handler function by using the handler name
- as shown below.
-</p>
-<pre>
-void WWDG_IRQHandler(void)
-{
- :
- :
-}</pre>
-
-
-<h3><a name="4"></a>system_<em>device</em>.c</h3>
-<p>
- A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
- the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
- this file must provide a device specific system configuration function and a global variable
- that contains the system frequency. It configures the device and initializes typically the
- oscillator (PLL) that is part of the microcontroller device.
-</p>
-<p>
- The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
- as a minimum requirement the SystemInit function as shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
- <td class="kt">Setup the microcontroller system. Typically this function configures the
- oscillator (PLL) that is part of the microcontroller device. For systems
- with variable clock speed it also updates the variable SystemFrequency.</td>
- </tr>
- </tbody>
-</table>
-
-<p>
- Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
- is the variable <strong>SystemFrequency</strong> which contains the current CPU clock speed shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Variable Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t SystemFrequency</td>
- <td class="kt">Contains the system frequency (which is the system clock frequency supplied
- to the SysTick timer and the processor core clock). This variable can be
- used by the user application after the call to the function SystemInit()
- to setup the SysTick timer or configure other parameters. It may also be
- used by debugger to query the frequency of the debug timer or configure
- the trace clock speed.<br><br>
- This variable may also be defined in the <strong>const</strong> space.
- The compiler must be configured to avoid the removal of this variable in
- case that the application program is not using it. It is important for
- debug systems that the variable is physically present in memory so that
- it can be examined to configure the debugger.</td>
- </tr>
- </tbody>
-</table>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>The above definitions are the minimum requirements for the file <strong>
- system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
- file may export more functions or variables that provide a more flexible
- configuration of the microcontroller system.</p>
- </li>
-</ul>
-
-
-<h2>Core Peripheral Access Layer</h2>
-
-<h3>Cortex-Mx Core Register Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
- and provide access to Cortex-Mx core registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Core</th>
- <th class="kt">Core Register</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 0</td>
- <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
- i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 1</td>
- <td class="kt">Global Interrupt disable (using the instruction <strong>
- CPSID i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = value</td>
- <td class="kt">Assign value to Priority Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PRIMASK</td>
- <td class="kt">Return Priority Mask Register (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 0</td>
- <td class="kt">Global Fault exception and Interrupt enable (using the
- instruction <strong>CPSIE
- f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 1</td>
- <td class="kt">Global Fault exception and Interrupt disable (using the
- instruction <strong>CPSID f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = value</td>
- <td class="kt">Assign value to Fault Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return FAULTMASK</td>
- <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">BASEPRI = value</td>
- <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return BASEPRI</td>
- <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">CONTROL = value</td>
- <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return CONTROL</td>
- <td class="kt">Return Control Register Value (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PSP = TopOfProcStack</td>
- <td class="kt">Set Process Stack Pointer value (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PSP</td>
- <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">MSP = TopOfMainStack</td>
- <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return MSP</td>
- <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- </tbody>
-</table>
-
-<h3>Cortex-Mx Instruction Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
- generate specific Cortex-Mx instructions. The functions are implemented in the file
- <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Generated CPU Instruction</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFI (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFI</td>
- <td class="kt">Wait for Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFE (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFE</td>
- <td class="kt">Wait for Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __SEV (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">SEV</td>
- <td class="kt">Set Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __ISB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">ISB</td>
- <td class="kt">Instruction Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DSB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DSB</td>
- <td class="kt">Data Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DMB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DMB</td>
- <td class="kt">Data Memory Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV</td>
- <td class="kt">Reverse byte order in integer value.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV16</td>
- <td class="kt">Reverse byte order in unsigned short value. </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REVSH</td>
- <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">RBIT</td>
- <td class="kt">Reverse bit order of value</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXB</td>
- <td class="kt">Load exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXH</td>
- <td class="kt">Load exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXW</td>
- <td class="kt">Load exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXB</td>
- <td class="kt">Store exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXH</td>
- <td class="kt">Store exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXW</td>
- <td class="kt">Store exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
- <td class="kt">M3</td>
- <td class="kt">CLREX</td>
- <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>NVIC Access Functions</h3>
-<p>
- The CMSIS provides access to the NVIC via the register interface structure and several helper
- functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
- identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
- IRQn values are used for processor core exceptions.
-</p>
-<p>
- For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
- the following enum names.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
- <th class="kt">Core</th>
- <th class="kt">IRQn</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-14</td>
- <td class="kt">Cortex-Mx Non Maskable Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-12</td>
- <td class="kt">Cortex-Mx Memory Management Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-11</td>
- <td class="kt">Cortex-Mx Bus Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-10</td>
- <td class="kt">Cortex-Mx Usage Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-5</td>
- <td class="kt">Cortex-Mx SV Call Interrupt </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-4</td>
- <td class="kt">Cortex-Mx Debug Monitor Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-2</td>
- <td class="kt">Cortex-Mx Pend SV Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-1</td>
- <td class="kt">Cortex-Mx System Tick Interrupt</td>
- </tr>
- </tbody>
-</table>
-
-<p>The following functions simplify the setup of the NVIC.
-The functions are defined as <strong>static inline</strong>.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping(uint32_t priority_grouping)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">Priority Grouping Value</td>
- <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ(IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Enable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ(IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Disable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return true (IRQ-Number) if IRQn is pending</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Set IRQn Pending</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Clear IRQn Pending Status</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return the IRQn of the active interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number, Priority</td>
- <td class="kt">Set Priority for IRQn<br>
- (not threadsafe for Cortex-M0)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Get Priority for IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">(void)</td>
- <td class="kt">Resets the System</td>
- </tr>
- </tbody>
-</table>
-<p class="Note">Note</p>
-<ul>
- <li><p>The processor exceptions have negative enum values. Device specific interrupts
- have positive enum values and start with 0. The values are defined in
- <b><em>device.h</em></b> file.</p>
- </li>
-</ul>
-
-
-<h3>SysTick Configuration Function</h3>
-
-<p>The following function is used to configure the SysTick timer and start the
-SysTick interrupt.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
- (uint32_t ticks)</span></td>
- <td class="kt">ticks is SysTick counter reload value</td>
- <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
- call the SysTick timer creates interrupts with the specified time
- interval. <br>
- <br>
- Return: 0 when successful, 1 on failure.<br>
- </td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>Cortex-M3 ITM Debug Access</h3>
-
-<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
-provides together with the Serial Viewer Output trace capabilities for the
-microcontroller system. The ITM has 32 communication channels; two ITM
-communication channels are used by CMSIS to output the following information:</p>
-<ul>
- <li>ITM Channel 0: implements the <strong>ITM_putchar</strong> function
- which can be used for printf-style output via the debug interface.</li>
- <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
- kernel awareness debugging.</li>
-</ul>
-<p class="Note">Note</p>
-<ul>
- <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
- may use the Privileged level for program execution. ITM
- channels have 4 groups with 8 channels each, whereby each group can be
- configured for access rights in the Unprivileged level. The ITM channel 0
- may be therefore enabled for the user task whereas ITM channel 31 may be
- accessible only in Privileged level from the RTOS kernel itself.</p>
- </li>
-</ul>
-
-<p>The prototype of the <strong>ITM_putchar</strong> routine is shown in the
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void uint32_t ITM_putchar(uint32_t chr)</td>
- <td class="kt">character to output</td>
- <td class="kt">The function outputs a character via the ITM channel 0. The
- function returns when no debugger is connected that has booked the
- output. It is blocking when a debugger is connected, but the
- previous character send is not transmitted. <br><br>
- Return: the input character 'chr'.</td>
- </tr>
- </tbody>
-</table>
-
-
-<p>
- Example for the usage of the ITM Channel 31 for RTOS Kernels:
-</p>
-<pre>
- // check if debugger connected and ITM channel enabled for tracing
- if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;
- (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;
- (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {
- // transmit trace data
- while (ITM-&gt;PORT31_U32 == 0);
- ITM-&gt;PORT[31].u8 = task_id; // id of next task
- while (ITM-&gt;PORT[31].u32 == 0);
- ITM-&gt;PORT[31].u32 = task_status; // status information
- }</pre>
-
-
-<h2><a name="5"></a>CMSIS Example</h2>
-<p>
- The following section shows a typical example for using the CMSIS layer in user applications.
-</p>
-<pre>
-#include &lt;device.h&gt; // file name depends on the device used.
-
-void SysTick_Handler (void) { // SysTick Interrupt Handler
- ;
-}
-
-void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
- ;
-}
-
-void timer1_init(int frequency) {
- // set up Timer (device specific)
- NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
- NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
-}
-
-void main (void) {
- SystemInit ();
-
- if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
- : // Handle Error
- :
- while (1);
- }
-
- timer1_init (); // device specific timer
-
- while (1);
-}</pre>
-
-
-</body></html> \ No newline at end of file
diff --git a/bsp/nuc140/application.c b/bsp/nuc140/application.c
deleted file mode 100644
index 40f1fd4234..0000000000
--- a/bsp/nuc140/application.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * File : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-01-25 Bernard first version
- */
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-#include <rtthread.h>
-
-int rt_application_init()
-{
- return 0;
-}
-
-/*@}*/
diff --git a/bsp/nuc140/board.c b/bsp/nuc140/board.c
deleted file mode 100644
index bb74ead8e9..0000000000
--- a/bsp/nuc140/board.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-01-25 Bernard first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "board.h"
-#include "uart.h"
-
-#include "CMSIS/CM0/NUC1xx.h"
-#include "CMSIS/CM0/core_cm0.h"
-
-/**
- * @addtogroup NUC100
- */
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler()
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- rt_tick_increase();
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-
-/**
- * This function will initial sam7s64 board.
- */
-void rt_hw_board_init()
-{
- SystemInit();
-
- /* init systick */
- SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1);
-
- /* set pend exception priority */
- NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
-
-#ifdef RT_USING_UART
- /* init hardware UART device */
- rt_hw_uart_init();
-#endif
-#ifdef RT_USING_CONSOLE
- /* set console device */
- rt_console_set_device("uart1");
-#endif
-}
-/*@}*/
diff --git a/bsp/nuc140/board.h b/bsp/nuc140/board.h
deleted file mode 100644
index a8f6dd9f87..0000000000
--- a/bsp/nuc140/board.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-01-25 Bernard first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/nuc140/project.uvopt b/bsp/nuc140/project.uvopt
deleted file mode 100644
index ad6dbf0745..0000000000
--- a/bsp/nuc140/project.uvopt
+++ /dev/null
@@ -1,2096 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
- <SchemaVersion>1.0</SchemaVersion>
-
- <Header>### uVision Project, (C) Keil Software</Header>
-
- <Extensions>
- <cExt>*.c</cExt>
- <aExt>*.s*; *.src; *.a*</aExt>
- <oExt>*.obj</oExt>
- <lExt>*.lib</lExt>
- <tExt>*.txt; *.h; *.inc</tExt>
- <pExt>*.plm</pExt>
- <CppX>*.cpp</CppX>
- </Extensions>
-
- <DaveTm>
- <dwLowDateTime>0</dwLowDateTime>
- <dwHighDateTime>0</dwHighDateTime>
- </DaveTm>
-
- <Target>
- <TargetName>RT-Thread NUC100</TargetName>
- <ToolsetNumber>0x4</ToolsetNumber>
- <ToolsetName>ARM-ADS</ToolsetName>
- <TargetOption>
- <CLKADS>12000000</CLKADS>
- <OPTTT>
- <gFlags>1</gFlags>
- <BeepAtEnd>1</BeepAtEnd>
- <RunSim>1</RunSim>
- <RunTarget>0</RunTarget>
- </OPTTT>
- <OPTHX>
- <HexSelection>1</HexSelection>
- <FlashByte>65535</FlashByte>
- <HexRangeLowAddress>0</HexRangeLowAddress>
- <HexRangeHighAddress>0</HexRangeHighAddress>
- <HexOffset>0</HexOffset>
- </OPTHX>
- <OPTLEX>
- <PageWidth>79</PageWidth>
- <PageLength>66</PageLength>
- <TabStop>8</TabStop>
- <ListingPath>.\</ListingPath>
- </OPTLEX>
- <ListingPage>
- <CreateCListing>1</CreateCListing>
- <CreateAListing>1</CreateAListing>
- <CreateLListing>1</CreateLListing>
- <CreateIListing>0</CreateIListing>
- <AsmCond>1</AsmCond>
- <AsmSymb>1</AsmSymb>
- <AsmXref>0</AsmXref>
- <CCond>1</CCond>
- <CCode>0</CCode>
- <CListInc>0</CListInc>
- <CSymb>0</CSymb>
- <LinkerCodeListing>0</LinkerCodeListing>
- </ListingPage>
- <OPTXL>
- <LMap>1</LMap>
- <LComments>1</LComments>
- <LGenerateSymbols>1</LGenerateSymbols>
- <LLibSym>1</LLibSym>
- <LLines>1</LLines>
- <LLocSym>1</LLocSym>
- <LPubSym>1</LPubSym>
- <LXref>0</LXref>
- <LExpSel>0</LExpSel>
- </OPTXL>
- <OPTFL>
- <tvExp>1</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <IsCurrentTarget>1</IsCurrentTarget>
- </OPTFL>
- <CpuCode>255</CpuCode>
- <DllOpt>
- <SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments></SimDllArguments>
- <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
- <SimDlgDllArguments></SimDlgDllArguments>
- <TargetDllName>SARMCM3.DLL</TargetDllName>
- <TargetDllArguments></TargetDllArguments>
- <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
- <TargetDlgDllArguments></TargetDlgDllArguments>
- </DllOpt>
- <DebugOpt>
- <uSim>0</uSim>
- <uTrg>1</uTrg>
- <sLdApp>1</sLdApp>
- <sGomain>1</sGomain>
- <sRbreak>1</sRbreak>
- <sRwatch>1</sRwatch>
- <sRmem>1</sRmem>
- <sRfunc>1</sRfunc>
- <sRbox>1</sRbox>
- <tLdApp>1</tLdApp>
- <tGomain>0</tGomain>
- <tRbreak>1</tRbreak>
- <tRwatch>1</tRwatch>
- <tRmem>1</tRmem>
- <tRfunc>0</tRfunc>
- <tRbox>1</tRbox>
- <sRunDeb>0</sRunDeb>
- <sLrtime>0</sLrtime>
- <nTsel>1</nTsel>
- <sDll></sDll>
- <sDllPa></sDllPa>
- <sDlgDll></sDlgDll>
- <sDlgPa></sDlgPa>
- <sIfile></sIfile>
- <tDll></tDll>
- <tDllPa></tDllPa>
- <tDlgDll></tDlgDll>
- <tDlgPa></tDlgPa>
- <tIfile></tIfile>
- <pMon>BIN\UL2CM3.DLL</pMon>
- </DebugOpt>
- <TargetDriverDllRegistry>
- <SetRegEntry>
- <Number>0</Number>
- <Key>DLGDARM</Key>
- <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
- </SetRegEntry>
- <SetRegEntry>
- <Number>0</Number>
- <Key>DLGTARM</Key>
- <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
- </SetRegEntry>
- <SetRegEntry>
- <Number>0</Number>
- <Key>ARMDBGFLAGS</Key>
- <Name>-T0</Name>
- </SetRegEntry>
- <SetRegEntry>
- <Number>0</Number>
- <Key>DLGUARM</Key>
- <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
- </SetRegEntry>
- <SetRegEntry>
- <Number>0</Number>
- <Key>UL2CM3</Key>
- <Name>-UV0704M0Z -O78 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0NUC1xx_128 -FS00 -FL020000</Name>
- </SetRegEntry>
- </TargetDriverDllRegistry>
- <DebugFlag>
- <trace>0</trace>
- <periodic>1</periodic>
- <aLwin>0</aLwin>
- <aCover>0</aCover>
- <aSer1>0</aSer1>
- <aSer2>0</aSer2>
- <aPa>0</aPa>
- <viewmode>1</viewmode>
- <vrSel>0</vrSel>
- <aSym>0</aSym>
- <aTbox>0</aTbox>
- <AscS1>0</AscS1>
- <AscS2>0</AscS2>
- <AscS3>0</AscS3>
- <aSer3>0</aSer3>
- <eProf>0</eProf>
- <aLa>0</aLa>
- <aPa1>0</aPa1>
- <AscS4>0</AscS4>
- <aSer4>0</aSer4>
- <StkLoc>1</StkLoc>
- <TrcWin>0</TrcWin>
- <newCpu>0</newCpu>
- <uProt>0</uProt>
- </DebugFlag>
- <LintExecutable></LintExecutable>
- <LintConfigFile></LintConfigFile>
- </TargetOption>
- </Target>
-
- <Group>
- <GroupName>Startup</GroupName>
- <tvExp>1</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <cbSel>0</cbSel>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>1</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\board.c</PathWithFileName>
- <FilenameWithoutPath>board.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>2</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>7</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\startup.c</PathWithFileName>
- <FilenameWithoutPath>startup.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>3</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>15</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\uart.c</PathWithFileName>
- <FilenameWithoutPath>uart.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>4</FileNumber>
- <FileType>5</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\rtconfig.h</PathWithFileName>
- <FilenameWithoutPath>rtconfig.h</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>5</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>6</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>5</TopLine>
- <CurrentLine>26</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\application.c</PathWithFileName>
- <FilenameWithoutPath>application.c</FilenameWithoutPath>
- </File>
- </Group>
-
- <Group>
- <GroupName>NUC100</GroupName>
- <tvExp>0</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <cbSel>0</cbSel>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>6</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\fault.c</PathWithFileName>
- <FilenameWithoutPath>fault.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>7</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\interrupt.c</PathWithFileName>
- <FilenameWithoutPath>interrupt.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>8</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\stack.c</PathWithFileName>
- <FilenameWithoutPath>stack.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>9</FileNumber>
- <FileType>2</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\context_rvds.S</PathWithFileName>
- <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>10</FileNumber>
- <FileType>2</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\fault_rvds.S</PathWithFileName>
- <FilenameWithoutPath>fault_rvds.S</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>2</GroupNumber>
- <FileNumber>11</FileNumber>
- <FileType>2</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\libcpu\arm\nuc1xx\start_rvds.S</PathWithFileName>
- <FilenameWithoutPath>start_rvds.S</FilenameWithoutPath>
- </File>
- </Group>
-
- <Group>
- <GroupName>CMSIS</GroupName>
- <tvExp>0</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <cbSel>0</cbSel>
- <File>
- <GroupNumber>3</GroupNumber>
- <FileNumber>12</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\CMSIS\CM0\system_NUC1xx.c</PathWithFileName>
- <FilenameWithoutPath>system_NUC1xx.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>3</GroupNumber>
- <FileNumber>13</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\CMSIS\CM0\core_cm0.c</PathWithFileName>
- <FilenameWithoutPath>core_cm0.c</FilenameWithoutPath>
- </File>
- </Group>
-
- <Group>
- <GroupName>Kernel</GroupName>
- <tvExp>0</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <cbSel>0</cbSel>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>14</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\timer.c</PathWithFileName>
- <FilenameWithoutPath>timer.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>15</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\clock.c</PathWithFileName>
- <FilenameWithoutPath>clock.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>16</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\device.c</PathWithFileName>
- <FilenameWithoutPath>device.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>17</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\idle.c</PathWithFileName>
- <FilenameWithoutPath>idle.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>18</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
- <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>19</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\irq.c</PathWithFileName>
- <FilenameWithoutPath>irq.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>20</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\kservice.c</PathWithFileName>
- <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>21</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\mem.c</PathWithFileName>
- <FilenameWithoutPath>mem.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>22</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\mempool.c</PathWithFileName>
- <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>23</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\object.c</PathWithFileName>
- <FilenameWithoutPath>object.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>24</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
- <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>25</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\slab.c</PathWithFileName>
- <FilenameWithoutPath>slab.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>4</GroupNumber>
- <FileNumber>26</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\src\thread.c</PathWithFileName>
- <FilenameWithoutPath>thread.c</FilenameWithoutPath>
- </File>
- </Group>
-
- <Group>
- <GroupName>finsh</GroupName>
- <tvExp>1</tvExp>
- <tvExpOptDlg>0</tvExpOptDlg>
- <cbSel>0</cbSel>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>27</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\symbol.c</PathWithFileName>
- <FilenameWithoutPath>symbol.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>28</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\cmd.c</PathWithFileName>
- <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>29</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_compiler.c</PathWithFileName>
- <FilenameWithoutPath>finsh_compiler.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>30</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>47</TopLine>
- <CurrentLine>60</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_error.c</PathWithFileName>
- <FilenameWithoutPath>finsh_error.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>31</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_heap.c</PathWithFileName>
- <FilenameWithoutPath>finsh_heap.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>32</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_init.c</PathWithFileName>
- <FilenameWithoutPath>finsh_init.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>33</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_node.c</PathWithFileName>
- <FilenameWithoutPath>finsh_node.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>34</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_ops.c</PathWithFileName>
- <FilenameWithoutPath>finsh_ops.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>35</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_parser.c</PathWithFileName>
- <FilenameWithoutPath>finsh_parser.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>36</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_token.c</PathWithFileName>
- <FilenameWithoutPath>finsh_token.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>37</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_var.c</PathWithFileName>
- <FilenameWithoutPath>finsh_var.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>38</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\finsh_vm.c</PathWithFileName>
- <FilenameWithoutPath>finsh_vm.c</FilenameWithoutPath>
- </File>
- <File>
- <GroupNumber>5</GroupNumber>
- <FileNumber>39</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>..\..\components\finsh\shell.c</PathWithFileName>
- <FilenameWithoutPath>shell.c</FilenameWithoutPath>
- </File>
- </Group>
-
- <WinLayout>
- <sActiveDebugView>Default</sActiveDebugView>
- <iActiveDebugViewLocation>1</iActiveDebugViewLocation>
- <sActiveBuildView>Build</sActiveBuildView>
- <iActiveBuildViewLocation>0</iActiveBuildViewLocation>
- <View>
- <ViewName>Default</ViewName>
- <ViewType>1</ViewType>
- <Window>
- <WinId>35824</WinId>
- <ItemNo>1</ItemNo>
- <Name>Logic Analyzer</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>6</DockType>
- <DockLocation>0</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>600</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>1</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>59392</WinId>
- <ItemNo>2</ItemNo>
- <Name>File</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>3</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>24</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>50</DockedRect_bottom>
- <DockedRect_right>893</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>0</FloatingRect_bottom>
- <FloatingRect_right>0</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>59398</WinId>
- <ItemNo>3</ItemNo>
- <Name>Build</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>3</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>50</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>76</DockedRect_bottom>
- <DockedRect_right>384</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>0</FloatingRect_bottom>
- <FloatingRect_right>0</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>59399</WinId>
- <ItemNo>4</ItemNo>
- <Name>Debug</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>3</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>50</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>76</DockedRect_bottom>
- <DockedRect_right>626</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>0</FloatingRect_bottom>
- <FloatingRect_right>0</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>197</WinId>
- <ItemNo>5</ItemNo>
- <Name>Build Output</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>4</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>198</WinId>
- <ItemNo>6</ItemNo>
- <Name>Command</Name>
- <AnchorWinID>197</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>199</WinId>
- <ItemNo>7</ItemNo>
- <Name>Find in Files</Name>
- <AnchorWinID>198</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>38007</WinId>
- <ItemNo>8</ItemNo>
- <Name>Browse</Name>
- <AnchorWinID>199</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1939</WinId>
- <ItemNo>9</ItemNo>
- <Name>UART #1</Name>
- <AnchorWinID>38007</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1940</WinId>
- <ItemNo>10</ItemNo>
- <Name>UART #2</Name>
- <AnchorWinID>1939</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1941</WinId>
- <ItemNo>11</ItemNo>
- <Name>UART #3</Name>
- <AnchorWinID>1940</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1942</WinId>
- <ItemNo>12</ItemNo>
- <Name>UART #4</Name>
- <AnchorWinID>1941</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1944</WinId>
- <ItemNo>13</ItemNo>
- <Name>Call Stack</Name>
- <AnchorWinID>197</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1507</WinId>
- <ItemNo>14</ItemNo>
- <Name>Call Stack</Name>
- <AnchorWinID>1944</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>1</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1935</WinId>
- <ItemNo>15</ItemNo>
- <Name>Locals</Name>
- <AnchorWinID>1507</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1936</WinId>
- <ItemNo>16</ItemNo>
- <Name>Watch 1</Name>
- <AnchorWinID>1935</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1937</WinId>
- <ItemNo>17</ItemNo>
- <Name>Watch 2</Name>
- <AnchorWinID>1936</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1465</WinId>
- <ItemNo>18</ItemNo>
- <Name>Memory 1</Name>
- <AnchorWinID>1937</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1466</WinId>
- <ItemNo>19</ItemNo>
- <Name>Memory 2</Name>
- <AnchorWinID>1465</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1467</WinId>
- <ItemNo>20</ItemNo>
- <Name>Memory 3</Name>
- <AnchorWinID>1466</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1468</WinId>
- <ItemNo>21</ItemNo>
- <Name>Memory 4</Name>
- <AnchorWinID>1467</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1506</WinId>
- <ItemNo>22</ItemNo>
- <Name>Symbols</Name>
- <AnchorWinID>1468</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>197</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>465</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>659</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>0</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1005</WinId>
- <ItemNo>23</ItemNo>
- <Name>Project</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>1</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>210</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>1</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>109</WinId>
- <ItemNo>24</ItemNo>
- <Name>Books</Name>
- <AnchorWinID>1005</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>210</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>195</WinId>
- <ItemNo>25</ItemNo>
- <Name>Functions</Name>
- <AnchorWinID>109</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>210</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>196</WinId>
- <ItemNo>26</ItemNo>
- <Name>Templates</Name>
- <AnchorWinID>195</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>210</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>38003</WinId>
- <ItemNo>27</ItemNo>
- <Name>Registers</Name>
- <AnchorWinID>196</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>210</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>1</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35885</WinId>
- <ItemNo>28</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35886</WinId>
- <ItemNo>29</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35885</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35887</WinId>
- <ItemNo>30</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35886</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35888</WinId>
- <ItemNo>31</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35887</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35889</WinId>
- <ItemNo>32</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35888</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35890</WinId>
- <ItemNo>33</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35889</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35891</WinId>
- <ItemNo>34</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35890</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35892</WinId>
- <ItemNo>35</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35891</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35893</WinId>
- <ItemNo>36</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35892</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35894</WinId>
- <ItemNo>37</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35893</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35895</WinId>
- <ItemNo>38</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35894</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35896</WinId>
- <ItemNo>39</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35895</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35897</WinId>
- <ItemNo>40</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35896</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35898</WinId>
- <ItemNo>41</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35897</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35899</WinId>
- <ItemNo>42</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35898</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35900</WinId>
- <ItemNo>43</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35899</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35901</WinId>
- <ItemNo>44</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35900</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35902</WinId>
- <ItemNo>45</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35901</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35903</WinId>
- <ItemNo>46</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35902</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35904</WinId>
- <ItemNo>47</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35903</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>35905</WinId>
- <ItemNo>48</ItemNo>
- <Name>not set</Name>
- <AnchorWinID>35904</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>76</DockedRect_top>
- <DockedRect_left>814</DockedRect_left>
- <DockedRect_bottom>461</DockedRect_bottom>
- <DockedRect_right>1024</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>600</FloatingRect_bottom>
- <FloatingRect_right>250</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>203</WinId>
- <ItemNo>49</ItemNo>
- <Name>Disassembly</Name>
- <AnchorWinID>0</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>2</DockType>
- <DockLocation>3</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>810</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>1913</WinId>
- <ItemNo>50</ItemNo>
- <Name>Instruction Trace</Name>
- <AnchorWinID>203</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>810</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>343</WinId>
- <ItemNo>51</ItemNo>
- <Name>Performance Analyzer</Name>
- <AnchorWinID>1913</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>810</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>204</WinId>
- <ItemNo>52</ItemNo>
- <Name>Performance Analyzer</Name>
- <AnchorWinID>343</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>810</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- <Window>
- <WinId>346</WinId>
- <ItemNo>53</ItemNo>
- <Name>Code Coverage</Name>
- <AnchorWinID>204</AnchorWinID>
- <AnchorWinName></AnchorWinName>
- <OtherWinID>0</OtherWinID>
- <OtherWinName></OtherWinName>
- <WinType>1</WinType>
- <DockType>4</DockType>
- <DockLocation>2</DockLocation>
- <Pinned>0</Pinned>
- <DockedRect_top>0</DockedRect_top>
- <DockedRect_left>0</DockedRect_left>
- <DockedRect_bottom>210</DockedRect_bottom>
- <DockedRect_right>810</DockedRect_right>
- <FloatingRect_top>0</FloatingRect_top>
- <FloatingRect_left>0</FloatingRect_left>
- <FloatingRect_bottom>250</FloatingRect_bottom>
- <FloatingRect_right>600</FloatingRect_right>
- <ContainerPercent>100</ContainerPercent>
- <ActiveTab>0</ActiveTab>
- <Visible>0</Visible>
- <Dynamic>0</Dynamic>
- </Window>
- </View>
- </WinLayout>
-
-</ProjectOpt>
diff --git a/bsp/nuc140/project.uvproj b/bsp/nuc140/project.uvproj
deleted file mode 100644
index 362158e600..0000000000
--- a/bsp/nuc140/project.uvproj
+++ /dev/null
@@ -1,609 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
- <SchemaVersion>1.0</SchemaVersion>
-
- <Header>### uVision Project, (C) Keil Software</Header>
-
- <Targets>
- <Target>
- <TargetName>RT-Thread NUC100</TargetName>
- <ToolsetNumber>0x4</ToolsetNumber>
- <ToolsetName>ARM-ADS</ToolsetName>
- <TargetOption>
- <TargetCommonOption>
- <Device>Cortex-M0</Device>
- <Vendor>ARM</Vendor>
- <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
- <FlashUtilSpec></FlashUtilSpec>
- <StartupFile></StartupFile>
- <FlashDriverDll></FlashDriverDll>
- <DeviceId>4803</DeviceId>
- <RegisterFile></RegisterFile>
- <MemoryEnv></MemoryEnv>
- <Cmp></Cmp>
- <Asm></Asm>
- <Linker></Linker>
- <OHString></OHString>
- <InfinionOptionDll></InfinionOptionDll>
- <SLE66CMisc></SLE66CMisc>
- <SLE66AMisc></SLE66AMisc>
- <SLE66LinkerMisc></SLE66LinkerMisc>
- <UseEnv>0</UseEnv>
- <BinPath></BinPath>
- <IncludePath></IncludePath>
- <LibPath></LibPath>
- <RegisterFilePath></RegisterFilePath>
- <DBRegisterFilePath></DBRegisterFilePath>
- <TargetStatus>
- <Error>0</Error>
- <ExitCodeStop>0</ExitCodeStop>
- <ButtonStop>0</ButtonStop>
- <NotGenerated>0</NotGenerated>
- <InvalidFlash>1</InvalidFlash>
- </TargetStatus>
- <OutputDirectory>.\objs\</OutputDirectory>
- <OutputName>rtthread-nuc140</OutputName>
- <CreateExecutable>1</CreateExecutable>
- <CreateLib>0</CreateLib>
- <CreateHexFile>0</CreateHexFile>
- <DebugInformation>1</DebugInformation>
- <BrowseInformation>1</BrowseInformation>
- <ListingPath>.\</ListingPath>
- <HexFormatSelection>1</HexFormatSelection>
- <Merge32K>0</Merge32K>
- <CreateBatchFile>0</CreateBatchFile>
- <BeforeCompile>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- </BeforeCompile>
- <BeforeMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- </BeforeMake>
- <AfterMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- </AfterMake>
- <SelectedForBatchBuild>0</SelectedForBatchBuild>
- <SVCSIdString></SVCSIdString>
- </TargetCommonOption>
- <CommonProperty>
- <UseCPPCompiler>0</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>1</IncludeInBuild>
- <AlwaysBuild>0</AlwaysBuild>
- <GenerateAssemblyFile>0</GenerateAssemblyFile>
- <AssembleAssemblyFile>0</AssembleAssemblyFile>
- <PublicsOnly>0</PublicsOnly>
- <StopOnExitCode>3</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <DllOption>
- <SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments></SimDllArguments>
- <SimDlgDll>DARMCM1.DLL</SimDlgDll>
- <SimDlgDllArguments></SimDlgDllArguments>
- <TargetDllName>SARMCM3.DLL</TargetDllName>
- <TargetDllArguments></TargetDllArguments>
- <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
- <TargetDlgDllArguments></TargetDlgDllArguments>
- </DllOption>
- <DebugOption>
- <OPTHX>
- <HexSelection>1</HexSelection>
- <HexRangeLowAddress>0</HexRangeLowAddress>
- <HexRangeHighAddress>0</HexRangeHighAddress>
- <HexOffset>0</HexOffset>
- <Oh166RecLen>16</Oh166RecLen>
- </OPTHX>
- <Simulator>
- <UseSimulator>0</UseSimulator>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>1</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>1</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
- </Simulator>
- <Target>
- <UseTarget>1</UseTarget>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>0</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>0</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- </Target>
- <RunDebugAfterBuild>0</RunDebugAfterBuild>
- <TargetSelection>1</TargetSelection>
- <SimDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- </SimDlls>
- <TargetDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- <Driver>BIN\UL2CM3.DLL</Driver>
- </TargetDlls>
- </DebugOption>
- <Utilities>
- <Flash1>
- <UseTargetDll>1</UseTargetDll>
- <UseExternalTool>0</UseExternalTool>
- <RunIndependent>0</RunIndependent>
- <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
- <Capability>1</Capability>
- <DriverSelection>4097</DriverSelection>
- </Flash1>
- <Flash2>BIN\UL2CM3.DLL</Flash2>
- <Flash3>"" ()</Flash3>
- <Flash4></Flash4>
- </Utilities>
- <TargetArmAds>
- <ArmAdsMisc>
- <GenerateListings>0</GenerateListings>
- <asHll>1</asHll>
- <asAsm>1</asAsm>
- <asMacX>1</asMacX>
- <asSyms>1</asSyms>
- <asFals>1</asFals>
- <asDbgD>1</asDbgD>
- <asForm>1</asForm>
- <ldLst>0</ldLst>
- <ldmm>1</ldmm>
- <ldXref>1</ldXref>
- <BigEnd>0</BigEnd>
- <AdsALst>1</AdsALst>
- <AdsACrf>1</AdsACrf>
- <AdsANop>0</AdsANop>
- <AdsANot>0</AdsANot>
- <AdsLLst>1</AdsLLst>
- <AdsLmap>1</AdsLmap>
- <AdsLcgr>1</AdsLcgr>
- <AdsLsym>1</AdsLsym>
- <AdsLszi>1</AdsLszi>
- <AdsLtoi>1</AdsLtoi>
- <AdsLsun>1</AdsLsun>
- <AdsLven>1</AdsLven>
- <AdsLsxf>1</AdsLsxf>
- <RvctClst>0</RvctClst>
- <GenPPlst>0</GenPPlst>
- <AdsCpuType>"Cortex-M0"</AdsCpuType>
- <RvctDeviceName></RvctDeviceName>
- <mOS>0</mOS>
- <uocRom>0</uocRom>
- <uocRam>0</uocRam>
- <hadIROM>0</hadIROM>
- <hadIRAM>0</hadIRAM>
- <hadXRAM>0</hadXRAM>
- <uocXRam>0</uocXRam>
- <RvdsVP>0</RvdsVP>
- <hadIRAM2>0</hadIRAM2>
- <hadIROM2>0</hadIROM2>
- <StupSel>8</StupSel>
- <useUlib>1</useUlib>
- <EndSel>0</EndSel>
- <uLtcg>0</uLtcg>
- <RoSelD>3</RoSelD>
- <RwSelD>5</RwSelD>
- <CodeSel>0</CodeSel>
- <OptFeed>1</OptFeed>
- <NoZi1>0</NoZi1>
- <NoZi2>0</NoZi2>
- <NoZi3>0</NoZi3>
- <NoZi4>0</NoZi4>
- <NoZi5>0</NoZi5>
- <Ro1Chk>0</Ro1Chk>
- <Ro2Chk>0</Ro2Chk>
- <Ro3Chk>0</Ro3Chk>
- <Ir1Chk>1</Ir1Chk>
- <Ir2Chk>0</Ir2Chk>
- <Ra1Chk>0</Ra1Chk>
- <Ra2Chk>0</Ra2Chk>
- <Ra3Chk>0</Ra3Chk>
- <Im1Chk>1</Im1Chk>
- <Im2Chk>0</Im2Chk>
- <OnChipMemories>
- <Ocm1>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm1>
- <Ocm2>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm2>
- <Ocm3>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm3>
- <Ocm4>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm4>
- <Ocm5>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm5>
- <Ocm6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm6>
- <IRAM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </IRAM>
- <IROM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </IROM>
- <XRAM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </XRAM>
- <OCR_RVCT1>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT1>
- <OCR_RVCT2>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT2>
- <OCR_RVCT3>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT3>
- <OCR_RVCT4>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x20000</Size>
- </OCR_RVCT4>
- <OCR_RVCT5>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT5>
- <OCR_RVCT6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT6>
- <OCR_RVCT7>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT7>
- <OCR_RVCT8>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT8>
- <OCR_RVCT9>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x4000</Size>
- </OCR_RVCT9>
- <OCR_RVCT10>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT10>
- </OnChipMemories>
- <RvctStartVector></RvctStartVector>
- </ArmAdsMisc>
- <Cads>
- <interw>1</interw>
- <Optim>3</Optim>
- <oTime>0</oTime>
- <SplitLS>0</SplitLS>
- <OneElfS>1</OneElfS>
- <Strict>0</Strict>
- <EnumInt>0</EnumInt>
- <PlainCh>0</PlainCh>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>0</uThumb>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath>.;..\..\include;..\..\components\finsh</IncludePath>
- </VariousControls>
- </Cads>
- <Aads>
- <interw>1</interw>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <thumb>1</thumb>
- <SplitLS>0</SplitLS>
- <SwStkChk>0</SwStkChk>
- <NoWarn>0</NoWarn>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Aads>
- <LDads>
- <umfTarg>1</umfTarg>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <noStLib>0</noStLib>
- <RepFail>1</RepFail>
- <useFile>0</useFile>
- <TextAddressRange>0x00000000</TextAddressRange>
- <DataAddressRange>0x20000000</DataAddressRange>
- <ScatterFile></ScatterFile>
- <IncludeLibs></IncludeLibs>
- <IncludeLibsPath></IncludeLibsPath>
- <Misc>--entry Reset_Handler --keep __fsym_* --keep __vsym_*</Misc>
- <LinkerInputFile></LinkerInputFile>
- <DisabledWarnings></DisabledWarnings>
- </LDads>
- </TargetArmAds>
- </TargetOption>
- <Groups>
- <Group>
- <GroupName>Startup</GroupName>
- <Files>
- <File>
- <FileName>board.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\board.c</FilePath>
- </File>
- <File>
- <FileName>startup.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\startup.c</FilePath>
- </File>
- <File>
- <FileName>uart.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\uart.c</FilePath>
- </File>
- <File>
- <FileName>rtconfig.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\rtconfig.h</FilePath>
- </File>
- <File>
- <FileName>application.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\application.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>NUC100</GroupName>
- <Files>
- <File>
- <FileName>fault.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\fault.c</FilePath>
- </File>
- <File>
- <FileName>interrupt.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\interrupt.c</FilePath>
- </File>
- <File>
- <FileName>stack.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\stack.c</FilePath>
- </File>
- <File>
- <FileName>context_rvds.S</FileName>
- <FileType>2</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\context_rvds.S</FilePath>
- </File>
- <File>
- <FileName>fault_rvds.S</FileName>
- <FileType>2</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\fault_rvds.S</FilePath>
- </File>
- <File>
- <FileName>start_rvds.S</FileName>
- <FileType>2</FileType>
- <FilePath>..\..\libcpu\arm\nuc1xx\start_rvds.S</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>CMSIS</GroupName>
- <Files>
- <File>
- <FileName>system_NUC1xx.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\CMSIS\CM0\system_NUC1xx.c</FilePath>
- </File>
- <File>
- <FileName>core_cm0.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\CMSIS\CM0\core_cm0.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>Kernel</GroupName>
- <Files>
- <File>
- <FileName>timer.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\timer.c</FilePath>
- </File>
- <File>
- <FileName>clock.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\clock.c</FilePath>
- </File>
- <File>
- <FileName>device.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\device.c</FilePath>
- </File>
- <File>
- <FileName>idle.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\idle.c</FilePath>
- </File>
- <File>
- <FileName>ipc.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\ipc.c</FilePath>
- </File>
- <File>
- <FileName>irq.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\irq.c</FilePath>
- </File>
- <File>
- <FileName>kservice.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\kservice.c</FilePath>
- </File>
- <File>
- <FileName>mem.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\mem.c</FilePath>
- </File>
- <File>
- <FileName>mempool.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\mempool.c</FilePath>
- </File>
- <File>
- <FileName>object.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\object.c</FilePath>
- </File>
- <File>
- <FileName>scheduler.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\scheduler.c</FilePath>
- </File>
- <File>
- <FileName>slab.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\slab.c</FilePath>
- </File>
- <File>
- <FileName>thread.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\src\thread.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>finsh</GroupName>
- <Files>
- <File>
- <FileName>symbol.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\symbol.c</FilePath>
- </File>
- <File>
- <FileName>cmd.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\cmd.c</FilePath>
- </File>
- <File>
- <FileName>finsh_compiler.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
- </File>
- <File>
- <FileName>finsh_error.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
- </File>
- <File>
- <FileName>finsh_heap.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
- </File>
- <File>
- <FileName>finsh_init.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
- </File>
- <File>
- <FileName>finsh_node.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
- </File>
- <File>
- <FileName>finsh_ops.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
- </File>
- <File>
- <FileName>finsh_parser.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
- </File>
- <File>
- <FileName>finsh_token.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
- </File>
- <File>
- <FileName>finsh_var.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
- </File>
- <File>
- <FileName>finsh_vm.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
- </File>
- <File>
- <FileName>shell.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\components\finsh\shell.c</FilePath>
- </File>
- </Files>
- </Group>
- </Groups>
- </Target>
- </Targets>
-
-</Project>
diff --git a/bsp/nuc140/rtconfig.h b/bsp/nuc140/rtconfig.h
deleted file mode 100644
index 6caa08a7d7..0000000000
--- a/bsp/nuc140/rtconfig.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX 4
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE 4
-
-/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX 8
-
-/* Tick per Second*/
-#define RT_TICK_PER_SECOND 100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug*/
-/* #define RT_THREAD_DEBUG */
-
-/* Using Hook*/
-/* #define RT_USING_HOOK */
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex*/
-/* #define RT_USING_MUTEX */
-
-/* Using Event*/
-/* #define RT_USING_EVENT */
-
-/* Using MailBox*/
-#define RT_USING_MAILBOX
-
-/* Using Message Queue*/
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
-
-/* Using Dynamic Heap Management*/
-#define RT_USING_HEAP
-
-/* Using Small MM*/
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-
-/* buffer size for UART reception */
-#define RT_UART_RX_BUFFER_SIZE 64
-
-/* Using UART */
-#define RT_USING_UART
-
-/* SECTION: Console options */
-/* use console for rt_kprintf */
-#define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE 80
-
-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
-/* #define RT_USING_FINSH */
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-#endif
diff --git a/bsp/nuc140/startup.c b/bsp/nuc140/startup.c
deleted file mode 100644
index 0e3c695df3..0000000000
--- a/bsp/nuc140/startup.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * File : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-01-25 Bernard first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#ifdef RT_USING_FINSH
-#include "finsh.h"
-extern void finsh_system_init(void);
-#endif
-
-/**
- * @addtogroup NUC100
- */
-
-/*@{*/
-#if defined(__CC_ARM)
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#elif defined(__GNUC__)
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-#endif
-
-extern int rt_application_init(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
- /* init kernel object */
- rt_system_object_init();
-
- /* init board */
- rt_hw_board_init();
- rt_show_version();
-
- /* init tick */
- rt_system_tick_init();
-
- /* init timer system */
- rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-#ifdef __CC_ARM
- rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20004000);
-#elif __ICCARM__
- rt_system_heap_init(__segment_end("HEAP"), (void*)0x20004000);
-#else
- rt_system_heap_init((void*)&__bss_end, (void*)0x20004000);
-#endif
-#endif
-
- /* init scheduler system */
- rt_system_scheduler_init();
-
-#ifdef RT_USING_HOOK /* if the hook is used */
- /* set idle thread hook */
- rt_thread_idle_sethook(rt_hw_led_flash);
-#endif
-
-#ifdef RT_USING_DEVICE
- /* init all device */
- rt_device_init_all();
-#endif
-
- /* init application */
- rt_application_init();
-
-#ifdef RT_USING_FINSH
- /* init finsh */
- finsh_system_init();
- finsh_set_device("uart1");
-#endif
-
- /* init idle thread */
- rt_thread_idle_init();
-
- /* start scheduler */
- rt_system_scheduler_start();
-
- /* never reach here */
- return ;
-}
-
-int main (void)
-{
- rt_uint32_t UNUSED level;
-
- /* disable interrupt first */
- level = rt_hw_interrupt_disable();
-
- /* invoke rtthread_startup */
- rtthread_startup();
-
- return 0;
-}
-
-/*@}*/
diff --git a/bsp/nuc140/uart.c b/bsp/nuc140/uart.c
deleted file mode 100644
index a7625b457e..0000000000
--- a/bsp/nuc140/uart.c
+++ /dev/null
@@ -1,226 +0,0 @@
-#include <rthw.h>
-#include <rtthread.h>
-#include "CMSIS/CM0/NUC1xx.h"
-
-/**
- * @addtogroup NUC1xx
- */
-
-/*@{*/
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
-
-#define UART_BAUDRATE 115200
-struct rt_uart_nuc
-{
- struct rt_device parent;
-
- /* buffer for reception */
- rt_uint8_t read_index, save_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-void UART0_IRQHandler(void)
-{
- rt_ubase_t level;
- struct rt_uart_nuc* uart = &uart_device;
-
- if (UART0->ISR.RDA_INT == 1) /* Receive Data Available */
- {
- while (UART0->ISR.RDA_IF == 1)
- {
- /* Receive Data Available */
- uart->rx_buffer[uart->save_index] = UART0->DATA;
-
- level = rt_hw_interrupt_disable();
- uart->save_index ++;
- if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
- uart->save_index = 0;
- rt_hw_interrupt_enable(level);
- }
-
- /* invoke callback */
- if(uart->parent.rx_indicate != RT_NULL)
- {
- rt_size_t length;
- if (uart->read_index > uart->save_index)
- length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
- else
- length = uart->save_index - uart->read_index;
-
- uart->parent.rx_indicate(&uart->parent, length);
- }
- }
-
- return;
-}
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
- /* Multi-Function Pin: Enable UART0:Tx Rx */
- SYS->GPBMFP.UART0_RX = 1;
- SYS->GPBMFP.UART0_TX = 1;
-
- /* Configure GCR to reset UART0 */
- SYS->IPRSTC2.UART0_RST = 1;
- SYS->IPRSTC2.UART0_RST = 0;
-
- /* Enable UART clock */
- SYSCLK->APBCLK.UART0_EN = 1;
-
- /* Select UART clock source */
- SYSCLK->CLKSEL1.UART_S = 0;
-
- /* Data format */
- UART0->LCR.WLS = 3;
-
- /* Configure the baud rate */
- *((__IO uint32_t *)&UART0->BAUD) = 0x3F000066; /* This setting is for 115200bsp with 12Mhz clock source */
-
- return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
- RT_ASSERT(dev != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* open receive data available interrupt */
- UART0->IER.RDA_IEN = 1;
-
- /* Enable the UART Interrupt */
- NVIC_EnableIRQ(UART0_IRQn);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
- RT_ASSERT(dev != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Disable the UART Interrupt */
- NVIC_DisableIRQ(UART0_IRQn);
- }
-
- return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- struct rt_uart_nuc *uart = (struct rt_uart_nuc*)dev;
- RT_ASSERT(uart != RT_NULL);
-
- /* point to buffer */
- ptr = (rt_uint8_t*) buffer;
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (uart->read_index != uart->save_index)
- {
- *ptr = uart->rx_buffer[uart->read_index];
-
- uart->read_index ++;
- if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
- uart->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- ptr ++;
- size --;
- }
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
-
- return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- char *ptr;
- ptr = (char*)buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- /* check whether UART is empty */
- while (UART0->FSR.TX_EMPTY !=1);
- /* write data */
- UART0->DATA = '\r';
- }
-
- /* check whether UART is empty */
- while (UART0->FSR.TX_EMPTY !=1);
- /* write data */
- UART0->DATA = *ptr;
-
- ptr ++;
- size --;
- }
- }
- else
- {
- while ( size != 0 )
- {
- /* check whether UART is empty */
- while (UART0->FSR.TX_EMPTY !=1);
- /* write data */
- UART0->DATA = *ptr;
-
- ptr++;
- size--;
- }
- }
-
- return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
- struct rt_uart_nuc* uart;
-
- /* get uart device */
- uart = &uart_device;
-
- /* device initialization */
- uart->parent.type = RT_Device_Class_Char;
- rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
- uart->read_index = uart->save_index = 0;
-
- /* device interface */
- uart->parent.init = rt_uart_init;
- uart->parent.open = rt_uart_open;
- uart->parent.close = rt_uart_close;
- uart->parent.read = rt_uart_read;
- uart->parent.write = rt_uart_write;
- uart->parent.control = RT_NULL;
- uart->parent.user_data = RT_NULL;
-
- rt_device_register(&uart->parent,
- "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/nuc140/uart.h b/bsp/nuc140/uart.h
deleted file mode 100644
index c5ca6c70c4..0000000000
--- a/bsp/nuc140/uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UART_H__
-#define __UART_H__
-
-void rt_hw_uart_init(void);
-
-#endif
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 15:41:53 +0000