[bsp][cvitek]: 将adc wdt驱动的局部函数移至源文件

4 files changed, 112 insertions, 113 deletions

diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c
index e3ca317b58..86cde2aabb 100644
--- a/bsp/cvitek/drivers/drv_adc.c
+++ b/bsp/cvitek/drivers/drv_adc.c
@@ -16,6 +16,49 @@
 #include <rtdbg.h>
 #define LOG_TAG "DRV.ADC"
 
+rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
+{
+    value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
+    mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
+}
+
+rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
+{
+    value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value;
+    mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
+}
+
+rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base)
+{
+    return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET));
+}
+
+rt_inline void cvi_set_cyc(unsigned long reg_base)
+{
+    rt_uint32_t value;
+
+    value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET);
+
+    value &= ~SARADC_CYC_CLKDIV_DIV_16;
+    mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
+
+    value |= SARADC_CYC_CLKDIV_DIV_16;                                                               //set saradc clock cycle=840ns
+    mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
+}
+
+rt_inline void cvi_do_calibration(unsigned long reg_base)
+{
+    rt_uint32_t val;
+
+    val = mmio_read_32(reg_base + SARADC_TEST_OFFSET);
+    val |= 1 << SARADC_TEST_VREFSEL_BIT;
+    mmio_write_32(reg_base + SARADC_TEST_OFFSET, val);
+
+    val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET);
+    val |= 0x4;
+    mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val);
+}
+
 struct cvi_adc_dev
 {
     struct rt_adc_device device;
diff --git a/bsp/cvitek/drivers/drv_adc.h b/bsp/cvitek/drivers/drv_adc.h
index 3ef86a2ecb..8cbec51b48 100644
--- a/bsp/cvitek/drivers/drv_adc.h
+++ b/bsp/cvitek/drivers/drv_adc.h
@@ -53,49 +53,6 @@
 
 #define SARADC_TRIM_OFFSET                  0x034
 
-rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
-{
-    value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
-    mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
-}
-
-rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
-{
-    value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value;
-    mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
-}
-
-rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base)
-{
-    return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET));
-}
-
-rt_inline void cvi_set_cyc(unsigned long reg_base)
-{
-    rt_uint32_t value;
-
-    value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET);
-
-    value &= ~SARADC_CYC_CLKDIV_DIV_16;
-    mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
-
-    value |= SARADC_CYC_CLKDIV_DIV_16;                                                               //set saradc clock cycle=840ns
-    mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
-}
-
-rt_inline void cvi_do_calibration(unsigned long reg_base)
-{
-    rt_uint32_t val;
-
-    val = mmio_read_32(reg_base + SARADC_TEST_OFFSET);
-    val |= 1 << SARADC_TEST_VREFSEL_BIT;
-    mmio_write_32(reg_base + SARADC_TEST_OFFSET, val);
-
-    val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET);
-    val |= 0x4;
-    mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val);
-}
-
 int rt_hw_adc_init(void);
 
 #endif /* __DRV_ADC_H__ */
diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c
index 1fb1ad8430..80d5203440 100644
--- a/bsp/cvitek/drivers/drv_wdt.c
+++ b/bsp/cvitek/drivers/drv_wdt.c
@@ -18,6 +18,75 @@
 #define WDT_FREQ_DEFAULT 25000000UL
 #define CVI_WDT_MAX_TOP     15
 
+rt_inline void cvi_wdt_top_setting()
+{
+    uint32_t val;
+
+    mmio_write_32(CV_TOP + CV_TOP_WDT_OFFSET, CV_TOP_WDT_VAL);
+
+    val = mmio_read_32(CV_RST_REG);
+    mmio_write_32(CV_RST_REG, val & ~CV_RST_WDT);
+    rt_hw_us_delay(10);
+    mmio_write_32(CV_RST_REG, val | CV_RST_WDT);
+}
+
+rt_inline void cvi_wdt_start_en(unsigned long reg_base)
+{
+    WDT_CR(reg_base) |= CVI_WDT_CR_WDT_ENABLE_En;
+}
+
+rt_inline void cvi_wdt_start_dis(unsigned long reg_base)
+{
+    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_ENABLE_En;
+}
+
+rt_inline uint32_t cvi_wdt_get_start(unsigned long reg_base)
+{
+    return (WDT_CR(reg_base) & CVI_WDT_CR_WDT_ENABLE_Msk);
+}
+
+rt_inline void cvi_wdt_set_timeout(unsigned long reg_base, uint32_t value)
+{
+    WDT_TORR(reg_base) &= ~CVI_WDT_TORR_WDT_TORR_Pos;
+    WDT_TORR(reg_base) = ((value << CVI_WDT_TORR_WDT_ITORR_Pos) | (value << CVI_WDT_TORR_WDT_TORR_Pos));
+}
+
+rt_inline void cvi_wdt_set_respond_system_reset(unsigned long reg_base)
+{
+    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST;
+}
+
+rt_inline void cvi_wdt_set_respond_irq_then_reset(unsigned long reg_base)
+{
+    WDT_CR(reg_base) |= CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST;
+}
+
+rt_inline void cvi_wdt_set_reset_pulse_width(unsigned long reg_base, uint32_t value)
+{
+    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Msk;
+    WDT_CR(reg_base) |= (value << CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Pos);
+}
+
+rt_inline void cvi_wdt_feed_en(unsigned long reg_base)
+{
+    WDT_CRR(reg_base) = CVI_WDT_CRR_FEED_En;
+}
+
+rt_inline uint32_t cvi_wdt_get_counter_value(unsigned long reg_base)
+{
+    return (WDT_CCVR(reg_base) & CVI_WDT_CCVR_COUNTER_Msk);
+}
+
+rt_inline uint32_t cvi_wdt_get_irq_stat(unsigned long reg_base)
+{
+    return (WDT_STAT(reg_base) & CVI_WDT_STAT_IRQ_STAT_Msk);
+}
+
+rt_inline void cvi_wdt_clr_irq_en(unsigned long reg_base)
+{
+    WDT_EOI(reg_base);
+}
+
 struct _cvi_wdt_dev
 {
     struct rt_watchdog_device device;
diff --git a/bsp/cvitek/drivers/drv_wdt.h b/bsp/cvitek/drivers/drv_wdt.h
index 7fbab6f951..65073dec1d 100644
--- a/bsp/cvitek/drivers/drv_wdt.h
+++ b/bsp/cvitek/drivers/drv_wdt.h
@@ -89,76 +89,6 @@ static struct cvi_wdt_regs_t *cvi_wdt_reg = &cv182x_wdt_reg;
 #define CV_RST_REG      (CV_TOP + 0x3004)
 #define CV_RST_WDT      (1U << 16)
 
-rt_inline void cvi_wdt_top_setting()
-{
-    uint32_t val;
-
-    mmio_write_32(CV_TOP + CV_TOP_WDT_OFFSET, CV_TOP_WDT_VAL);
-
-    val = mmio_read_32(CV_RST_REG);
-    mmio_write_32(CV_RST_REG, val & ~CV_RST_WDT);
-    rt_hw_us_delay(10);
-    mmio_write_32(CV_RST_REG, val | CV_RST_WDT);
-}
-
-rt_inline void cvi_wdt_start_en(unsigned long reg_base)
-{
-    WDT_CR(reg_base) |= CVI_WDT_CR_WDT_ENABLE_En;
-}
-
-rt_inline void cvi_wdt_start_dis(unsigned long reg_base)
-{
-    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_ENABLE_En;
-}
-
-rt_inline uint32_t cvi_wdt_get_start(unsigned long reg_base)
-{
-    return (WDT_CR(reg_base) & CVI_WDT_CR_WDT_ENABLE_Msk);
-}
-
-rt_inline void cvi_wdt_set_timeout(unsigned long reg_base, uint32_t value)
-{
-    WDT_TORR(reg_base) &= ~CVI_WDT_TORR_WDT_TORR_Pos;
-    WDT_TORR(reg_base) = ((value << CVI_WDT_TORR_WDT_ITORR_Pos) | (value << CVI_WDT_TORR_WDT_TORR_Pos));
-}
-
-rt_inline void cvi_wdt_set_respond_system_reset(unsigned long reg_base)
-{
-    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST;
-}
-
-rt_inline void cvi_wdt_set_respond_irq_then_reset(unsigned long reg_base)
-{
-    WDT_CR(reg_base) |= CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST;
-}
-
-rt_inline void cvi_wdt_set_reset_pulse_width(unsigned long reg_base, uint32_t value)
-{
-    WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Msk;
-    WDT_CR(reg_base) |= (value << CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Pos);
-}
-
-rt_inline void cvi_wdt_feed_en(unsigned long reg_base)
-{
-    WDT_CRR(reg_base) = CVI_WDT_CRR_FEED_En;
-}
-
-rt_inline uint32_t cvi_wdt_get_counter_value(unsigned long reg_base)
-{
-    return (WDT_CCVR(reg_base) & CVI_WDT_CCVR_COUNTER_Msk);
-}
-
-rt_inline uint32_t cvi_wdt_get_irq_stat(unsigned long reg_base)
-{
-    return (WDT_STAT(reg_base) & CVI_WDT_STAT_IRQ_STAT_Msk);
-}
-
-rt_inline void cvi_wdt_clr_irq_en(unsigned long reg_base)
-{
-    WDT_EOI(reg_base);
-}
-
-
 int rt_hw_wdt_init(void);
 
 #endif /* __DRV_WDT_H__ */