diff options
| author | Grissiom <[email protected]> | 2015-01-05 21:32:21 +0800 |
|---|---|---|
| committer | Grissiom <[email protected]> | 2015-01-06 10:46:32 +0800 |
| commit | 090adcf4c070083e98fce673dcb23c5a97c5bd00 (patch) | |
| tree | 36e107bcfc3e3a9ca72a7c268bdec9e600a72b0d | |
| parent | 21ef733251473f1d7f43cab03d998210a000b844 (diff) | |
lpc43xx: don't set the Clock again in M0 core
M0 core is always booted by the M4 core. It means that if we are running
in M0, the clock is always configured.
| -rw-r--r-- | bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c index c51bd1c67e..3309f50aaf 100644 --- a/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c +++ b/bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c @@ -869,6 +869,7 @@ void SystemCoreClockUpdate (void) { *----------------------------------------------------------------------------*/ void SystemInit (void) { +#ifdef BOOT_PROCESSOR #if (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ @@ -880,9 +881,10 @@ void SystemInit (void) { /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ SetClock(); - /* Update SystemCoreClock variable */ - SystemCoreClockUpdate(); - /* Configure External Memory Controller */ SystemInit_ExtMemCtl (); +#endif + + /* Update SystemCoreClock variable */ + SystemCoreClockUpdate(); } |