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authorBernard Xiong <[email protected]>2016-06-16 17:01:34 +0800
committerGitHub <[email protected]>2016-06-16 17:01:34 +0800
commitbb9bb4ea7940e9adf865fc9595759174f1b0d5e9 (patch)
tree3779bf2aec40d2d426a9a48555974bbde2310842
parent99481cd0ac55c52d4023c50175766a18cefa7064 (diff)
parentc72433560d66ab58c92eaf86b75358c29fb9bea1 (diff)
Merge pull request #641 from kontais/master
[BSP] flush cache after exception code install in loogson 1B/C
-rw-r--r--bsp/ls1bdev/applications/startup.c6
-rw-r--r--bsp/ls1cdev/applications/startup.c6
-rw-r--r--libcpu/mips/loongson_1b/cache.c4
-rw-r--r--libcpu/mips/loongson_1c/cache.c4
4 files changed, 18 insertions, 2 deletions
diff --git a/bsp/ls1bdev/applications/startup.c b/bsp/ls1bdev/applications/startup.c
index bfd8214027..deedf962f6 100644
--- a/bsp/ls1bdev/applications/startup.c
+++ b/bsp/ls1bdev/applications/startup.c
@@ -32,6 +32,9 @@ extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
+extern void rt_hw_cache_init(void);
+extern void invalidate_writeback_dcache_all(void);
+extern void invalidate_icache_all(void);
/**
* This function will startup RT-Thread RTOS.
@@ -51,6 +54,9 @@ void rtthread_startup(void)
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
+ invalidate_writeback_dcache_all();
+ invalidate_icache_all();
+
/* init board */
rt_hw_board_init();
diff --git a/bsp/ls1cdev/applications/startup.c b/bsp/ls1cdev/applications/startup.c
index 5c78776f84..ed2854e97e 100644
--- a/bsp/ls1cdev/applications/startup.c
+++ b/bsp/ls1cdev/applications/startup.c
@@ -33,6 +33,9 @@ extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
+extern void rt_hw_cache_init(void);
+extern void invalidate_writeback_dcache_all(void);
+extern void invalidate_icache_all(void);
/**
* This function will startup RT-Thread RTOS.
@@ -52,6 +55,9 @@ void rtthread_startup(void)
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
+ invalidate_writeback_dcache_all();
+ invalidate_icache_all();
+
/* init board */
rt_hw_board_init();
diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c
index 9b3dfde44d..842f392cb7 100644
--- a/libcpu/mips/loongson_1b/cache.c
+++ b/libcpu/mips/loongson_1b/cache.c
@@ -13,6 +13,7 @@
* 2011-08-08 lgnq modified for LS1B
*/
+#include <rtthread.h>
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
@@ -23,6 +24,7 @@ extern void Invalidate_Icache_Ls1b(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
+extern void enable_cpu_cache(void);
typedef struct cacheinfo_t
{
@@ -151,7 +153,7 @@ void invalidate_dcache_all(void)
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
- Invalidate_Dcache_Fill_Gc3210I(start);
+ Invalidate_Dcache_Fill_Ls1b(start);
start += pcacheinfo->icacheline_size;
}
}
diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c
index 79ab5308d2..bf97db9b4e 100644
--- a/libcpu/mips/loongson_1c/cache.c
+++ b/libcpu/mips/loongson_1c/cache.c
@@ -14,6 +14,7 @@
* 2015-07-08 chinesebear modified for loongson 1c
*/
+#include <rtthread.h>
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
@@ -24,6 +25,7 @@ extern void Invalidate_Icache_Ls1c(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
+extern void enable_cpu_cache(void);
typedef struct cacheinfo_t
{
@@ -152,7 +154,7 @@ void invalidate_dcache_all(void)
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
- Invalidate_Dcache_Fill_Gc3210I(start);
+ Invalidate_Dcache_Fill_Ls1c(start);
start += pcacheinfo->icacheline_size;
}
}