diff options
| author | Bernard Xiong <[email protected]> | 2018-08-01 17:37:27 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2018-08-01 17:37:27 +0800 |
| commit | 1ec998b10a9c4ea66e6a8cab0b63f07c8bdf8db8 (patch) | |
| tree | b6a191d6680230c5c291548cf864fe607afc937b | |
| parent | 90cef4fbac386a9ad3bfcafa86c52019798393d9 (diff) | |
| parent | b46e7f317288e34e779efb4d749d65e96df45637 (diff) | |
Merge pull request #1684 from hichard/master
add rt_hw_cpu_reset for cortex-m cpu
| -rw-r--r-- | libcpu/arm/cortex-m3/cpuport.c | 10 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m4/cpuport.c | 10 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/cpuport.c | 10 |
3 files changed, 30 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index 10989ffc5b..3c7e0ee857 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -110,6 +110,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context)) #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ @@ -352,6 +354,14 @@ void rt_hw_cpu_shutdown(void) RT_ASSERT(0); } +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + #ifdef RT_USING_CPU_FFS /** * This function finds the first bit set (beginning with the least significant bit) diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index dabe4cdb93..ed7102f844 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -187,6 +187,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ @@ -431,6 +433,14 @@ void rt_hw_cpu_shutdown(void) RT_ASSERT(0); } +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + #ifdef RT_USING_CPU_FFS /** * This function finds the first bit set (beginning with the least significant bit) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index dabe4cdb93..ed7102f844 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -187,6 +187,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ @@ -431,6 +433,14 @@ void rt_hw_cpu_shutdown(void) RT_ASSERT(0); } +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + #ifdef RT_USING_CPU_FFS /** * This function finds the first bit set (beginning with the least significant bit) |