diff options
| author | nongxiaoming <[email protected]> | 2018-10-04 17:07:52 +0800 |
|---|---|---|
| committer | nongxiaoming <[email protected]> | 2018-10-04 17:07:52 +0800 |
| commit | 9f3938da1e9f0b02afea0bfec2f918ad8713bf49 (patch) | |
| tree | ff1c4c285661ec6da5a6f8d2f840c49e711d45ab | |
| parent | 4bc36f722c38ec0b104bc5abe3423f9120d352f0 (diff) | |
[bsp][stm32] Fix the warning when using ARM Compiler V6
| -rw-r--r-- | bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c | 2 | ||||
| -rw-r--r-- | bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c b/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c index 63938af735..8db1e630f6 100644 --- a/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c +++ b/bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c @@ -385,7 +385,7 @@ static void SetSysClock(void) RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) { } } diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c index 18fa12b803..1cd0875538 100644 --- a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c @@ -400,7 +400,7 @@ static void SetSysClock(void) RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) { } } |