summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorwdfk-prog <[email protected]>2023-02-07 20:14:35 +0800
committerMan, Jianting (Meco) <[email protected]>2023-02-07 12:05:27 -0500
commit72961172033fcb3a96e6fb1758b5ca0e1aebe455 (patch)
treec58bf27aa328a9dd27df3a6a47740d84a0fed18f
parent7c1d6ffd3c10dfc0af8608ff1546a6a8b0d0b54c (diff)
[cortex-m7]rt_hw_cpu_dcache_ops函数uint32_t替换为rt_uint32_t
-rw-r--r--libcpu/arm/cortex-m7/cpu_cache.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c
index a6c0d62fcf..94e03df5a7 100644
--- a/libcpu/arm/cortex-m7/cpu_cache.c
+++ b/libcpu/arm/cortex-m7/cpu_cache.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -73,15 +73,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
if ((ops & clean_invalid) == clean_invalid)
{
- SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
+ SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
}
else if (ops & RT_HW_CACHE_FLUSH)
{
- SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte);
+ SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
}
else if (ops & RT_HW_CACHE_INVALIDATE)
{
- SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
+ SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
}
else
{