diff options
| author | heyuanjie87 <[email protected]> | 2024-09-20 10:43:13 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2024-09-23 12:57:53 +0800 |
| commit | 8a53e6d63947a0ee0c60da53d322c75e0f5048cc (patch) | |
| tree | 32b03a145076f5d1ca0f1f7d6e826f56bf596915 | |
| parent | af5ca55736c8b4fa9538469afcaddd3453ead8b9 (diff) | |
删除多余空格
| -rw-r--r-- | libcpu/risc-v/t-head/c908/opcode.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/risc-v/t-head/c908/opcode.h b/libcpu/risc-v/t-head/c908/opcode.h index 2952b5465d..90b002dc4e 100644 --- a/libcpu/risc-v/t-head/c908/opcode.h +++ b/libcpu/risc-v/t-head/c908/opcode.h @@ -14,7 +14,7 @@ /** * @brief binary opcode pseudo operations * Used to bypass toolchain restriction on extension ISA - * + * * WARNING: Xuantie ISAs are not compatible to each other in opcode. * It's painful to port this file, and should be really careful. */ @@ -23,9 +23,9 @@ * @brief RISC-V instruction formats */ -/** +/** * R type: .insn r opcode6, func3, func7, rd, rs1, rs2 - * + * * +-------+-----+-----+-------+----+---------+ * | func7 | rs2 | rs1 | func3 | rd | opcode6 | * +-------+-----+-----+-------+----+---------+ |